Semiconductor device and method for manufacturing the same

Abstract

This invention discloses a semiconductor device and a method for manufacturing the same. The semiconductor device includes: a substrate; a first active pattern formed on the substrate; a first gate structure surrounding at least a portion of the first active pattern; a first source / drain region and a second source / drain region respectively disposed on a first side and a second side of the first gate structure facing each other; and a first dielectric pattern disposed on a third side different from the first side and the second side of the first gate structure, wherein the first dielectric pattern includes: a first portion of the first dielectric pattern disposed between the first source / drain region and the first side of the first gate structure; and a second portion of the first dielectric pattern disposed between the second source / drain region and the second side of the first gate structure.

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods for manufacturing the same. Prior Technology

[0002] The content described in this section is merely to provide background information on the technology of this embodiment and does not constitute prior art.

[0003] With the development of semiconductor technology, the demand for higher storage capacity, faster processing systems, and higher performance is gradually increasing. To meet this demand, the semiconductor industry is constantly shrinking the size of semiconductor devices, including planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and fin field-effect transistors (FFETs). This shrinkage increases the complexity of semiconductor manufacturing processes.

[0004] On the other hand, in response to the trend of miniaturization in semiconductor devices, various studies are being conducted to reduce the cell height of field-effect transistors.

[0005] For finned field-effect transistors (FSFETs), a dielectric is placed between the N-type and P-type transistors to reduce cell height. However, in FSFETs, one sidewall of the channel is in contact with the dielectric. In the source / drain region in contact with the dielectric, silicon patterning may not be formed, and the sidewall portion of the channel in contact with the dielectric is not surrounded by the gate, resulting in a degraded electrical performance. Summary of the Invention

[0006] The problem that the invention aims to solve The object of the present invention is to provide a semiconductor device for forming dielectric patterns between transistors of the same type and a method thereof.

[0007] Furthermore, the object of the present invention is to provide a semiconductor device and a method thereof, in a gate-all-around structure, for completely surrounding the channel region by a gate electrode.

[0008] Furthermore, the object of the present invention is to provide a semiconductor device and a method thereof, wherein a silicon pattern is configured to surround the source / drain region.

[0009] The purpose of this invention is not limited to the purposes mentioned above. Other purposes and advantages of this invention not mentioned can be understood through the following description and will become more apparent through the embodiments of this invention. Furthermore, it can be easily understood that the purposes and advantages of this invention can be achieved through the solutions and combinations thereof within the scope of the invention claims.

[0010] Technical means to solve the problem The semiconductor device of this invention includes: a substrate; a first active pattern formed on the substrate; a first gate structure surrounding at least a portion of the first active pattern; a first source / drain region and a second source / drain region respectively disposed on a first side and a second side of the first gate structure facing each other; and a first dielectric pattern disposed on a third side different from the first side and the second side of the first gate structure, wherein the first dielectric pattern includes: a first portion of the first dielectric pattern disposed between the first source / drain region and the first side of the first gate structure; and a second portion of the first dielectric pattern disposed between the second source / drain region and the second side of the first gate structure.

[0011] Furthermore, the first gate structure includes a portion of the first gate structure disposed between the first active pattern and the first dielectric pattern along a second direction intersecting the first direction, wherein the first direction is perpendicular to the first gate structure and the substrate.

[0012] Furthermore, the portion of the first gate structure is disposed between the first portion and the second portion of the first dielectric pattern.

[0013] Furthermore, the present invention further includes: a first silicide pattern disposed between the first source / drain region and the first dielectric pattern; and a second silicide pattern disposed between the second source / drain region and the first dielectric pattern.

[0014] Furthermore, the present invention further includes: a second active pattern formed on the substrate; and a second gate structure surrounding at least a portion of the second active pattern, wherein the first dielectric pattern is disposed between the first gate structure and the second gate structure, and between the first active pattern and the second active pattern, a first region of the first dielectric pattern between the first active pattern and the second active pattern has a first width, a second region of the first dielectric pattern between the first gate structure and the second gate structure has a second width, the first width and the second width are different, and the first region of the first dielectric pattern includes the first portion.

[0015] Furthermore, the first width is greater than the second width.

[0016] Furthermore, the present invention also includes a third source / drain region and a fourth source / drain region, respectively disposed on the fifth and sixth sides of the second gate structure facing each other. The first dielectric pattern includes: a third portion of the first dielectric pattern disposed between the third source / drain region and the fifth side of the second gate structure; and a fourth portion of the first dielectric pattern disposed between the fourth source / drain region and the sixth side of the second gate structure. The first region of the first dielectric pattern includes the third portion.

[0017] Furthermore, the third region of the first dielectric pattern between the first source / drain region and the third source / drain region has a third width, and the fourth region of the first dielectric pattern between the second source / drain region and the fourth source / drain region has a fourth width, wherein the third width is different from the fourth width.

[0018] Furthermore, the first portion of the first gate structure disposed between the first portion and the second portion of the first dielectric pattern has a first width, and the second portion of the first gate structure disposed between the first source / drain and the second source / drain and disposed on the first active pattern has a second width. The first width of the first portion of the first gate structure is different from the second width of the second portion of the first gate structure.

[0019] Furthermore, the first portion of the first dielectric pattern also includes a first recessed portion recessed into the first source / drain region.

[0020] Furthermore, the second portion of the first dielectric pattern also includes a second recessed portion recessed into the first source / drain region.

[0021] The semiconductor device of this invention includes: a substrate; a first transistor of a first type, including a first active pattern on the substrate and a first gate structure surrounding the first active pattern; a second transistor of a second type, including a second active pattern on the substrate and a second gate structure surrounding the second active pattern; a patterned first dielectric pattern disposed between the first transistor and the second transistor; a third transistor of the second type, including a third active pattern on the substrate and a third gate structure surrounding the third active pattern; and a patterned second dielectric pattern disposed between the second transistor and the third transistor, wherein a first region of the second dielectric pattern between the second active pattern and the third active pattern has a first width, and a second region of the second dielectric pattern between the second gate structure and the third gate structure has a second width, wherein the first width and the second width are different.

[0022] Furthermore, the present invention also includes a first source / drain region and a second source / drain region respectively disposed on a first side and a second side facing each other in the first gate structure, and the first dielectric pattern is disposed on a third side different from the first side and the second side. The first dielectric pattern includes: a first portion of the first dielectric pattern disposed between the first source / drain region and the first side of the first gate structure; and a second portion of the first dielectric pattern disposed between the second source / drain region and the second side of the first gate structure.

[0023] Furthermore, the present invention also includes a third source / drain region and a fourth source / drain region respectively disposed on the fifth and sixth sides of the second gate structure facing each other, and the first dielectric pattern includes: a third portion of the first dielectric pattern disposed between the third source / drain region and the fifth side of the second gate structure; and a fourth portion of the first dielectric pattern disposed between the fourth source / drain region and the sixth side of the second gate structure.

[0024] Furthermore, the second dielectric pattern includes: a fifth portion of the second dielectric pattern disposed between the third source / drain region and the fifth side of the second gate structure; and a sixth portion of the second dielectric pattern disposed between the fourth source / drain region and the sixth side of the second gate structure.

[0025] Furthermore, the third region of the first dielectric pattern between the first source / drain region and the third source / drain region has a third width, and the fourth region of the first dielectric pattern between the second source / drain region and the fourth source / drain region has a fourth width, wherein the third width is different from the fourth width.

[0026] Furthermore, the first portion of the first gate structure disposed between the first portion and the second portion of the first dielectric pattern has a first width, and the second portion of the first gate structure disposed between the first source / drain and the second source / drain and disposed on the first active pattern has a second width. The first width of the first portion of the first gate structure is different from the second width of the second portion of the first gate structure.

[0027] Furthermore, the first portion of the first dielectric pattern also includes a first recessed portion recessed into the first source / drain region.

[0028] Furthermore, the second portion of the first dielectric pattern also includes a second recessed portion recessed into the first source / drain region.

[0029] The semiconductor device manufacturing method of this invention includes the following steps: alternatingly stacking a first layer and a second layer on a substrate and then patterning to form a pin pattern; forming a dummy wall surrounding the pin pattern on the substrate; patterning the dummy wall to form a first dummy pattern and a second dummy pattern spaced apart from each other; forming a first dielectric pattern, the first dielectric pattern being formed between the first dummy pattern and the second dummy pattern, covering the sidewalls of the first dummy pattern and the second dummy pattern respectively; removing a portion of the pin pattern on the side of the first dummy pattern to form a first source / drain region; removing the second dummy pattern and the second layer to form a first gate structure surrounding the first layer; and removing the first dummy pattern.

[0030] Furthermore, the present invention also includes the step of forming a silicon pattern between the first dielectric pattern and the first source / drain region after removing the first virtual pattern.

[0031] Furthermore, the first dielectric pattern includes a first portion of the first dielectric pattern disposed between the first source / drain region and the first gate structure.

[0032] Furthermore, the steps of forming the first virtual pattern and the second virtual pattern further include the following steps: forming a third virtual pattern separated from the first virtual pattern and the second virtual pattern, wherein the first dielectric pattern is also formed between the second virtual pattern and the third virtual pattern and covers the sidewall of the third virtual pattern; the semiconductor device manufacturing method further includes the following steps: removing another portion of the pin pattern on the third virtual pattern side to form a second source / drain region; and removing the third virtual pattern.

[0033] Furthermore, the first dielectric pattern includes: a first portion of the first dielectric pattern disposed between the first source / drain region and a first side of the first gate structure; and a second portion of the first dielectric pattern disposed between the second source / drain region and a second side of the first gate structure.

[0034] Compared with the efficacy of previous technologies In the semiconductor device and manufacturing method of the present invention, dielectric patterns are formed between transistors of the same type, thereby reducing chip size.

[0035] Furthermore, in the semiconductor device and manufacturing method of the present invention, in the all-around gate structure, the channel region is completely surrounded by the gate electrode, thereby improving electrical performance.

[0036] In addition to the above, the specific effects of the invention will also be described in the following description of specific embodiments for carrying out the invention. Simple Explanation of the Diagram

[0037] Figure 1 is a partial perspective view of a semiconductor device according to several embodiments of the present invention. Figure 2 is a cross-sectional view taken along line A-A' in Figure 1. Figure 3 is a cross-sectional view taken along line B-B' in Figure 1. Figure 4 is a cross-sectional view taken along line C-C' in Figure 1. Figure 5 is a cross-sectional view taken along line C-C' in Figure 1. Figure 6 is a cross-sectional view taken along line C-C' in Figure 1. Figure 7 is a cross-sectional view taken along line C-C' in Figure 1. Figure 8 is a cross-sectional view taken along line C-C' in Figure 1. Figure 9 is a cross-sectional view taken along line C-C' in Figure 1. Figure 10 is a cross-sectional view taken along line C-C' in Figure 1. Figure 11 is a cross-sectional view taken along line C-C' in Figure 1. Figure 12 is a cross-sectional view taken along line C-C' in Figure 1. Figure 13 is a flowchart illustrating a method for manufacturing a semiconductor device according to several embodiments of the present invention. Figures 14 and 15 are used to illustrate step S100 of Figure 13 and can be perspective views of a semiconductor device. Figure 16 is a diagram illustrating step S200 of Figure 13 and can be a perspective view of the semiconductor device. Figure 17, used to illustrate step S300 of Figure 13, can be a perspective view of the semiconductor device. Figure 18, used to illustrate step S400 of Figure 13, can be a perspective view of the semiconductor device. Figures 19 and 20 are used to illustrate step S500 of Figure 13 and can be perspective views of a semiconductor device. Figures 21 to 24 are diagrams used to illustrate step S600 of Figure 13. Figures 25 to 27 are cross-sectional views taken along the YY line of Figure 21. Implementation

[0038] The terms or words used in this specification and the claims of this invention should not be limited to their general or dictionary meanings. Based on the principle that inventors may appropriately define the concepts of terms or words in order to explain their invention using the most preferred method, they should be interpreted as meanings and concepts consistent with the technical idea of ​​this invention. Furthermore, the embodiments described in this specification and the structures shown in the figures are merely one embodiment of the invention and do not represent the entirety of the technical idea of ​​this invention. It should be understood that at the time of this application, there may be various equivalent technical solutions, modifications, and applicable examples that can replace these.

[0039] The terms "first," "second," "A," and "B," as used in this specification and the claims of this invention, can be used to describe various structural elements, but the structural elements are not limited to these terms. These terms are only used to distinguish between two structural elements. For example, without departing from the scope of protection of this invention, a first structural element may be named a second structural element, and similarly, a second structural element may be named a first structural element. Terms such as "and / or" include a combination of multiple related described items or one of multiple related described items.

[0040] The terminology used in this specification and the claims of this invention is for illustrative purposes only and is not intended to limit the invention. Unless explicitly stated in the context, singular expressions include plural expressions. In this application, terms such as "comprising" or "having" should be understood as not precluding the presence or additional possibilities of features, numbers, steps, actions, structural elements, components, or combinations thereof described in the specification.

[0041] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0042] Terms defined in commonly used dictionaries have the same meaning as in the context of the relevant art, and should not be interpreted as having an ideal or overly formal meaning unless explicitly defined in this application. Furthermore, the structures, processes, steps, or methods included in the various embodiments of this invention can be shared to the extent that they do not conflict with each other technically.

[0043] Hereinafter, semiconductor devices according to various embodiments of the present invention will be described with reference to FIGS. 1 to 4.

[0044] Figure 1 is a partial perspective view of a semiconductor device according to various embodiments of the present invention. Figure 2 is a cross-sectional view taken along line A-A' of Figure 1. Figure 3 is a cross-sectional view taken along line B-B' of Figure 1. Figure 4 is a cross-sectional view taken along line C-C' of Figure 1. Figure 4 is a cross-sectional view taken along a direction parallel to the upper surface of the substrate, showing the first transistor of Figure 1 and other transistors included in the semiconductor device according to various embodiments of the present invention.

[0045] Referring to Figures 1 to 4, the semiconductor device of various embodiments of the present invention may include at least one transistor. Figure 1 is a perspective view showing a first transistor TR1 as a transistor included in the semiconductor device. The semiconductor device of various embodiments of the present invention may also include transistors of the same or different types as the first transistor TR1. For example, when a second transistor (TR2 in Figure 4) is also included, the second transistor TR2 may be configured to have a first dielectric pattern 200 between the first transistor TR1 and the second transistor TR2. And, for example, when a third transistor (TR3 in Figure 4) is also included, the third transistor TR3 may be configured to have a second dielectric pattern (300 in Figure 4) between the second transistor TR2 and the third transistor TR3. Each transistor may include a shape as described with reference to Figures 1 to 3. In Figure 4, the first silicon pattern and the second silicon pattern are omitted for simplicity.

[0046] The first transistor TR1 of the semiconductor device in various embodiments of the present invention may include a substrate 100, a first active pattern 141, a first gate structure 111, a first source / drain region 121, a second source / drain region 122, and a first dielectric pattern 200.

[0047] The substrate 100 may include a first region 101 and a second region 102. The first region 101 of the substrate 100 may be a punch-through stop (PTS) ion implantation region. The second region 102 of the substrate 100 may contain an insulating material.

[0048] The first transistor TR1 of the semiconductor device in various embodiments of the present invention may include a first active pattern 141 on a substrate 100. The first active pattern 141 may be a channel region. A first source / drain region 121 and a second source / drain region 122 may be disposed at both ends of the first active pattern 141. That is, the first active pattern 141 may be disposed between the first source / drain region 121 and the second source / drain region 122. For example, between the first source / drain region 121 and the second source / drain region 122, a plurality of first active patterns 141 may be disposed spaced apart from each other along a first direction D1 perpendicular to the substrate 100.

[0049] The first active pattern 141 may be surrounded by the first gate structure 111. For example, the first gate structure 111 may surround at least a portion of the first active pattern 141.

[0050] The first gate structure 111 may include a first gate electrode 111e and a first gate insulating film 161.

[0051] The first gate electrode 111e may surround at least a portion of the first active pattern 141. The first gate electrode 111e may be spaced apart from the first source / drain region 121 and the second source / drain region 122, respectively. The first gate electrode 111e may be disposed between the first active pattern 141 and the substrate 100. The first gate electrode 111e may be disposed between the first dielectric pattern 200 and the first active pattern 141.

[0052] A first gate insulating film 161 may surround at least a portion of the first gate electrode 111e. The first gate insulating film 161 may surround the first active pattern 141. The first gate insulating film 161 may be disposed between the first dielectric pattern 200 and the first gate electrode 111e. The first gate insulating film 161 may be disposed between the substrate 100 and the first gate electrode 111e. The first gate insulating film 161 may be disposed between the first gate electrode 111e and the first active pattern 141.

[0053] For example, the first gate electrode 111e may contain at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, and Al. Alternatively, the first gate electrode 111e may also be formed of nonmetals such as Si and SiGe.

[0054] The first gate insulating film 161 may comprise at least one film. For example, the first gate insulating film 161 may comprise a silicon oxide film, a silicon oxynitride film, or a silicon nitride film. For example, the first gate insulating film 161 may comprise a high dielectric constant insulating film having a high dielectric material, wherein the dielectric constant of the high dielectric material is greater than the dielectric constant of the silicon oxide film. For example, a high dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate, but is not limited thereto.

[0055] The first gate structure 111 may include a first side 1111S and a second side 1112S facing each other. A first source / drain region 121 may be formed on the first side 1111S of the first gate structure 111. A second source / drain region 122 may be formed on the second side 1112S of the first gate structure 111.

[0056] At least a portion of the first source / drain region 121 may be surrounded by a first silicide pattern 131. The first silicide pattern 131 may be disposed on the sidewalls and top surface of the first source / drain region 121 on the substrate 100. A second silicide pattern 132 may be disposed on the sidewalls and top surface of the second source / drain region 122 on the substrate 100. The first silicide pattern 131 may be disposed between the first source / drain region 121 and the first dielectric pattern 200. The second silicide pattern 132 may be disposed between the second source / drain region 122 and the first dielectric pattern 200.

[0057] A spacer material 170 may be disposed between the first gate structure 111 and the first source / drain region 121. A spacer material 170 may also be disposed between the first gate structure 111 and the second source / drain region 122. The spacer material 170 may surround the remaining region in the first active pattern 141 except for the region surrounded by the first gate structure 111. For example, it may surround a portion of the first active pattern 141 exposed through the first gate structure 111. The spacer material 170 may be disposed on the first dielectric pattern 200 and on the first gate structure 111.

[0058] The first source / drain region 121, the second source / drain region 122, and the first gate structure 111 may each include a contact portion 150. The contact portions 150 may be respectively disposed on the first source / drain region 121, the second source / drain region 122, and the first gate structure 111. A spacer material 170 may be disposed between the contact portions 150.

[0059] For example, the spacer material 170 may contain at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), and combinations thereof.

[0060] The first dielectric pattern 200 may be disposed on the third side 1113S and the fourth side 1114S of the first gate structure 111. The third side 1113S of the first gate structure 111 may be a side surface of the first gate structure 111 that is different from the first side 1111S and the second side 1112S. The third side 1113S and the fourth side 1114S of the first gate structure 111 may face each other.

[0061] A first source / drain region 121, a second source / drain region 122, a first active pattern 141, and a first gate structure 111 can be disposed between the first dielectric pattern 200 on the third side 1113S and the first dielectric pattern 200 on the fourth side 1114S of the first gate structure 111.

[0062] The first dielectric pattern 200 may include a first portion 2001 disposed between the first source / drain region 121 and the first side 1111S of the first gate structure 111. For example, a portion of the first active pattern 141 and the first portion 2001 of the first dielectric pattern 200 may be disposed between the first source / drain region 121 and the first gate structure 111. The first portion 2001 of the first dielectric pattern 200 may overlap with the first gate structure 111 and the first source / drain region 121 along a third direction D3 intersecting the first direction D1.

[0063] The third direction D3 can be the same direction as the direction in which the first active pattern 141 extends between the first source / drain region 121 and the second source / drain region 122.

[0064] The first dielectric pattern 200 may include a second portion 2002 disposed between the second source / drain region 122 and the second side 1112S of the first gate structure 111. For example, a portion of the first active pattern 141 and the second portion 2002 of the first dielectric pattern 200 may be disposed between the second source / drain region 122 and the first gate structure 111. The second portion 2002 of the first dielectric pattern 200 may overlap with the first gate structure 111 and the second source / drain region 122 along a third direction D3.

[0065] The dielectric pattern of the semiconductor device in this embodiment of the invention may include a first portion 2001 and a second portion 2002 of a first dielectric pattern 200 inserted between the source / drain regions 121, 122 and the first gate structure 111. Thus, the first active pattern 141 is surrounded by the first gate structure 111, and the first active pattern 141 is bonded to the first dielectric pattern 200, so that there is no portion of the first active pattern 141 that is not surrounded by the first gate structure 111.

[0066] The first gate structure 111 may include a portion 111P of the first gate structure 111 disposed between the first active pattern 141 and the first dielectric pattern 200. The portion 111P of the first gate structure 111 may overlap with the first active pattern 141 and the first dielectric pattern 200 along a second direction D2. The second direction D2 may be a direction intersecting the first direction D1. The second direction D2 may also be a direction intersecting the direction in which the first active pattern 141 extends between the first source / drain region 121 and the second source / drain region 122 (e.g., a third direction D3).

[0067] A portion 111P of the first gate structure 111 may be disposed between the first portion 2001 and the second portion 2002 of the first dielectric pattern 200.

[0068] The first gate structure 111 may include a first portion 1111 of the first gate structure 111 disposed between a first portion 2001 and a second portion 2002 of the first dielectric pattern 200. The first portion 1111 of the first gate structure 111 may be disposed on a portion 111P of the first gate structure 111. The portion 111P of the first gate structure 111 may be disposed above or below the first portion 1111 of the first gate structure 111. The first portion 1111 of the first gate structure 111 may be a portion that does not overlap with the first active pattern 141 along the first direction D1.

[0069] The second portion 1112 of the first gate structure 111 may be a part of the first gate structure 111 disposed on the first active pattern 141. The second portion 1112 of the first gate structure 111 may be a portion that overlaps with the first active pattern 141 along the first direction D1. The second portion 1112 of the first gate structure 111 may be disposed between the first source / drain region 121 and the second source / drain region 122.

[0070] The first portion 1111 of the first gate structure 111 may have a first width Wg1, and the second portion 1112 of the first gate structure 111 may have a second width Wg2. The first width Wg1 and the second width Wg2 may be values ​​measured along a third direction D3.

[0071] In several embodiments, the first width Wg1 of the first portion 1111 of the first gate structure 111 may be the same as the second width Wg2 of the second portion 1112 of the first gate structure 111.

[0072] A first dielectric pattern 200 may be disposed between a first transistor TR1 and a second transistor TR2. A second dielectric pattern 300 may be disposed between a second transistor TR2 and a third transistor TR3. The first transistor TR1 may be of a first type, and the second transistor TR2 may be of a second type, different from the first type. The third transistor TR3 may be of the second type.

[0073] In the semiconductor device of this invention, patterned dielectric patterns 200 and 300 are provided between a plurality of transistors of the same type, thereby reducing the spacing between the plurality of transistors of the same type and thus reducing the chip size.

[0074] The first dielectric pattern 200 may be disposed between the first source / drain region 121 and the third source / drain region 123. The first dielectric pattern 200 may be disposed between the first active pattern 141 and the second active pattern 142. The first dielectric pattern 200 may be disposed between the first gate structure 111 and the second gate structure 112. The first dielectric pattern 200 may be disposed between the second source / drain region 122 and the fourth source / drain region 124.

[0075] The first silicide pattern 131 (omitted in Figure 4) can be disposed between the first dielectric pattern 200 and the first source / drain region 121. The second silicide pattern 132 (omitted in Figure 4) can be disposed between the first dielectric pattern 200 and the second source / drain region 122. The silicide patterns disposed in the third source / drain region 123 and the fourth source / drain region 124 can also be disposed between the first dielectric pattern 200 and the third source / drain region 123 and the fourth source / drain region 124, respectively.

[0076] The second transistor TR2 of the semiconductor device in various embodiments of the present invention may include a second active pattern 142, a second gate structure 112, a third source / drain region 123 and a fourth source / drain region 124 on a substrate 100.

[0077] The description of the first transistor TR1 is applicable to the description of the second transistor TR2 and the third transistor TR3. Hereinafter, portions that overlap with the description are simplified or omitted.

[0078] The second gate structure 112 may surround at least a portion of the second active pattern 142. The second gate structure 112 may include a second gate electrode 112e and a second gate insulating film 162.

[0079] A third source / drain region 123 and a fourth source / drain region 124 may be respectively provided on the fifth side 1125S and the sixth side 1126S facing each other in the second gate structure 112.

[0080] The third transistor TR3 of the semiconductor device in various embodiments of the present invention may include a third active pattern 143, a third gate structure 113, a fifth source / drain region 125 and a sixth source / drain region 126 on a substrate 100.

[0081] The third gate structure 113 may surround at least a portion of the third active pattern 143. The third gate structure 113 may include a third gate electrode 113e and a third gate insulating film 163.

[0082] A third active pattern 143 and a third gate structure 113 may be disposed between the fifth source / drain region 125 and the sixth source / drain region 126.

[0083] The first dielectric pattern 200 may include a third portion 2003 disposed between the third source / drain region 123 and the fifth side 1125S of the second gate structure 112. The third portion 2003 of the first dielectric pattern 200 may overlap with the third source / drain region 123 and the second gate structure 112 along a third direction D3.

[0084] The first dielectric pattern 200 may include a fourth portion 2004 disposed between the fourth source / drain region 124 and the sixth side 1126S of the second gate structure 112. The fourth portion 2004 of the first dielectric pattern 200 may overlap with the fourth source / drain region 124 and the second gate structure 112 along the third direction D3.

[0085] The first dielectric pattern 200 may include a first region 200R1 of the first dielectric pattern 200 disposed between the first active pattern 141 and the second active pattern 142. The first region 200R1 of the first dielectric pattern 200 may include a first portion 2001 and a third portion 2003 of the first dielectric pattern 200.

[0086] The first dielectric pattern 200 may include a second region 200R2 of the first dielectric pattern 200 disposed between the first gate structure 111 and the second gate structure 112.

[0087] The first dielectric pattern 200 may include a third region 200R3 of the first dielectric pattern 200 disposed between the first source / drain region 121 and the third source / drain region 123.

[0088] The first dielectric pattern 200 may include a fourth region 200R4 of the first dielectric pattern 200 disposed between the second source / drain region 122 and the fourth source / drain region 124.

[0089] The first length W1 of the first region 200R1 of the first dielectric pattern 200 may be different from the second length W2 of the second region 200R2 of the first dielectric pattern 200.

[0090] In several embodiments, the first length W1 of the first region 200R1 of the first dielectric pattern 200 may be greater than the second length W2 of the second region 200R2 of the first dielectric pattern 200.

[0091] In several embodiments, the third length W3 of the third region 200R3 of the first dielectric pattern 200 may be the same as or different from the fourth length W4 of the fourth region 200R4 of the first dielectric pattern 200.

[0092] The first length W1 of the first dielectric pattern 200 may be greater than the second length W2, the third length W3 and the fourth length W4.

[0093] Among them, the first length W1, the second length W2, the third length W3, and the fourth length W4 can be values ​​measured along the second direction D2.

[0094] The second dielectric pattern 300 may include a fifth portion 3001 of the second dielectric pattern 300 disposed on the fifth side 1125S of the third source / drain region 123 and the second gate structure 112. The second dielectric pattern 300 may include a sixth portion 3002 of the second dielectric pattern 300 disposed on the sixth side 1126S of the fourth source / drain region 124 and the second gate structure 112.

[0095] The fifth portion 3001 of the second dielectric pattern 300 may overlap with the third source / drain region 123 and the second gate structure 112 along the third direction D3. The sixth portion 3002 of the second dielectric pattern 300 may overlap with the fourth source / drain region 124 and the second gate structure 112 along the third direction D3.

[0096] The second dielectric pattern 300 may include a first region 300R1 of the second dielectric pattern 300 disposed between the second active pattern 142 and the third active pattern 143. The second dielectric pattern 300 may include a second region 300R2 of the second dielectric pattern 300 disposed between the second gate structure 112 and the third gate structure 113. The second region 300R2 of the second dielectric pattern 300 may include a fifth portion 3001 of the second dielectric pattern 300.

[0097] The first region 300R1 of the second dielectric pattern 300 may have a fifth length W5, and the second region 300R2 of the second dielectric pattern 300 may have a sixth length W6. The fifth length W5 and the sixth length W6 may be different. For example, the fifth length W5 may be greater than the sixth length W6. The fifth length W5 and the sixth length W6 may be values ​​measured along the second direction D2.

[0098] Hereinafter, semiconductor devices according to various embodiments of the present invention will be described with reference to FIGS. 1, 2, 3 and 5. For clarity, parts that are repeated in the description will be simplified or omitted.

[0099] Figure 5 is a cross-sectional view taken along line C-C' in Figure 1.

[0100] Referring to Figures 1, 2, 3, and 5, each portion of the gate structure included in the semiconductor device of various embodiments of the present invention may have a different width. For example, the first width Wg1 of the first portion 1111 of the first gate structure 111 may be different from the second width Wg2 of the second portion 1112 of the first gate structure 111.

[0101] In the first gate structure 111, the first width Wg1 of the first portion 1111 that overlaps with the first portion 2001 and the second portion 2002 of the first dielectric pattern 200 along the third direction D3 may be different from the second width Wg2 of the second portion 1112 on the first active pattern 141.

[0102] In several embodiments, the first width Wg1 may be smaller than the second width Wg2.

[0103] The description of the first gate structure 111 can also be applied to the second gate structure 112 and the third gate structure 113.

[0104] Hereinafter, semiconductor devices according to various embodiments of the present invention will be described with reference to Figures 1, 2, 3, and 6. For clarity, parts that overlap with the description will be simplified or omitted.

[0105] Figure 6 is a cross-sectional view taken along line C-C' in Figure 1.

[0106] Referring to Figures 1, 2, 3, and 6, each portion of the gate structure included in the semiconductor device of various embodiments of the present invention has a different width. For example, the first width Wg1 of the first portion 1111 of the first gate structure 111 may be different from the second width Wg2 of the second portion 1112 of the first gate structure 111.

[0107] In the first gate structure 111, the first width Wg1 of the first portion 1111 that overlaps with the first portion 2001 and the second portion 2002 of the first dielectric pattern 200 along the third direction D3 may be different from the second width Wg2 of the second portion 1112 on the first active pattern 141.

[0108] In several embodiments, the first width Wg1 may be greater than the second width Wg2.

[0109] The description of the first gate structure 111 is also applicable to the second gate structure 112 and the third gate structure 113.

[0110] Hereinafter, semiconductor devices according to various embodiments of the present invention will be described with reference to FIGS. 1, 2, 3 and 7. For clarity, parts that are repeated in the description will be simplified or omitted.

[0111] Figure 7 is a cross-sectional view taken along line C-C' in Figure 1.

[0112] Referring to Figures 1, 2, 3, and 7, each portion of the source / drain region included in the semiconductor device of various embodiments of the present invention may have a different width. For example, a portion of the first source / drain region 121 that overlaps with a first portion 2001 of the first dielectric pattern 200 along a third direction D3 may have a first width Ws1. Other portions of the first source / drain region 121 that overlap with the first active pattern along a third direction D3 may have a second width Ws2. The first width Ws1 and the second width Ws2 may be values ​​measured along the third direction D3.

[0113] In several embodiments, the first width Ws1 may be smaller than the second width Ws2.

[0114] A first portion 2001 of the first dielectric pattern 200 may include a first recessed portion 2001i recessed into a first source / drain region 121. A second portion 2002 of the first dielectric pattern 200 may include a second recessed portion 2002i recessed into a second source / drain region 122.

[0115] Due to the first recessed portion 2001i and the second recessed portion 2002i, each portion of the source / drain region can have a different width.

[0116] The description of the first dielectric pattern 200 can also be applied to the second dielectric pattern 300. The description of the first source / drain region 121 and the second source / drain region 122 can also be applied to the third source / drain region 123, the fourth source / drain region 124, the fifth source / drain region 125 and the sixth source / drain region 126.

[0117] Hereinafter, semiconductor devices according to various embodiments of the present invention will be described with reference to FIGS. 1, 2, 3 and 8. For clarity, parts that are repeated in the description will be simplified or omitted.

[0118] Figure 8 is a cross-sectional view taken along line C-C' in Figure 1.

[0119] Referring to Figures 1, 2, 3 and 8, in the semiconductor device of various embodiments of the present invention, a spacer material may also be provided between the source / drain region and the dielectric pattern.

[0120] For example, a spacer material 170 may be disposed between the first source / drain region 121 and the third region 200R3 of the first dielectric pattern 200. For example, a spacer material 170 may be disposed between the second source / drain region 122 and the fourth region 200R4 of the first dielectric pattern 200. For example, a spacer material 170 may be disposed between the third source / drain region 123 and the second dielectric pattern 300. For example, a spacer material 170 may be disposed between the fourth source / drain region 124 and the second dielectric pattern 300.

[0121] Although the illustration is omitted, in this embodiment, the silicate patterns 131 and 132 can be disposed between the source / drain region and the spacer material.

[0122] The third length W3 of the third region 200R3 of the first dielectric pattern 200 and the fourth length W4 of the fourth region 200R4 may be the same or different.

[0123] With the spacer material 170 disposed between the dielectric pattern and the source / drain region, space for the spacer material 170 can be ensured, thus ensuring profitability in the semiconductor device manufacturing process.

[0124] Hereinafter, semiconductor devices according to various embodiments of the present invention will be described with reference to FIGS. 1, 2, 3 and 9. For clarity, parts that are repeated in the description will be simplified or omitted.

[0125] Figure 9 is a cross-sectional view taken along line C-C' in Figure 1.

[0126] Referring to Figures 1, 2, 3, and 9, the source / drain regions of the semiconductor devices in various embodiments of the present invention can have different lengths depending on their location. For example, a portion of the first source / drain region 121 that overlaps with a first portion 2001 of the first dielectric pattern 200 along a third direction D3 may have a first length L1. A portion of the second source / drain region 122 that overlaps with a second portion 2002 of the first dielectric pattern 200 along a third direction D3 may have a second length L2. A portion of the third source / drain region 123 that overlaps with a third portion 2003 of the first dielectric pattern 200 along a third direction D3 may have a third length L3. A portion of the fourth source / drain region 124 that overlaps with a fourth portion 2004 of the first dielectric pattern 200 along a third direction D3 may have a fourth length L4.

[0127] In several embodiments, the second length L2 of a portion of the second source / drain region 122 may be greater than the first length L1 of a portion of the first source / drain region 121. The third length L3 of a portion of the third source / drain region 123 may be greater than the fourth length L4 of a portion of the fourth source / drain region 124. The third length L3 of a portion of the third source / drain region 123 may be greater than the first length L1 of a portion of the first source / drain region 121. The second length L2 of a portion of the second source / drain region 122 may be greater than the fourth length L4 of a portion of the fourth source / drain region 124.

[0128] For example, a contact portion 150 may be provided on a portion of the third source / drain region 123 having a third length L3. For example, a contact portion 150 may be provided on a portion of the second source / drain region 122 having a second length L2.

[0129] The third length W3 of the third region 200R3 of the first dielectric pattern 200 and the fourth length W4 of the fourth region 200R4 of the first dielectric pattern 200 may be the same or different.

[0130] Hereinafter, semiconductor devices according to various embodiments of the present invention will be described with reference to FIGS. 1, 2, 3 and 10. For clarity, parts that are repeated in the description will be simplified or omitted.

[0131] Figure 10 is a cross-sectional view taken along line C-C' in Figure 1.

[0132] Referring to Figures 1, 2, 3 and 10, the source / drain regions of the semiconductor devices in various embodiments of the present invention can have different lengths depending on their location.

[0133] In several embodiments, the second length L2 of a portion of the second source / drain region 122 may be substantially the same as the first length L1 of a portion of the first source / drain region 121. The third length L3 of a portion of the third source / drain region 123 may be less than the fourth length L4 of a portion of the fourth source / drain region 124.

[0134] For example, a contact portion 150 may be provided on a portion of the first source / drain region 121 having a first length L1.

[0135] The third length W3 of the third region 200R3 of the first dielectric pattern 200 may be different from the fourth length W4 of the fourth region 200R4 of the first dielectric pattern 200. The third length W3 of the third region 200R3 of the first dielectric pattern 200 may be greater than the fourth length W4 of the fourth region 200R4 of the first dielectric pattern 200. The second length W2 of the second region 200R2 of the first dielectric pattern 200 may substantially be the same as the fourth length W4 of the fourth region 200R4 of the first dielectric pattern 200.

[0136] Hereinafter, semiconductor devices according to various embodiments of the present invention will be described with reference to FIGS. 1, 2, 3 and 11. For clarity, parts that are repeated in the description will be simplified or omitted.

[0137] Figure 11 is a cross-sectional view taken along line C-C' in Figure 1.

[0138] Referring to Figures 1, 2, 3, and 11, in various embodiments of the semiconductor device of the present invention, the fourth length W4 of the fourth region 200R4 of the first dielectric pattern 200 may be greater than the third length W3 of the third region 200R3 of the first dielectric pattern 200. The fourth length W4 of the fourth region 200R4 of the first dielectric pattern 200 may be greater than the second length W2 of the second region 200R2 of the first dielectric pattern 200. The fourth length W4 of the fourth region 200R4 of the first dielectric pattern 200 may be less than the first length W1 of the first region 200R1 of the first dielectric pattern 200.

[0139] A spacer material 170 may be disposed between the third region 200R3 of the first dielectric pattern 200 and the first source / drain region 121. A spacer material 170 may be disposed between the third region 200R3 of the first dielectric pattern 200 and the third source / drain region 123.

[0140] Hereinafter, semiconductor devices according to various embodiments of the present invention will be described with reference to FIG1, FIG2, FIG3 and FIG12. For clarity of description, parts that are repeated in the description will be simplified or omitted.

[0141] Figure 12 is a cross-sectional view taken along line C-C' in Figure 1.

[0142] Referring to Figures 1, 2, 3, and 12, the third length W3 of the third region 200R3 of the first dielectric pattern 200 of the semiconductor device according to various embodiments of the present invention may be substantially the same as the fourth length W4 of the fourth region 200R4 of the first dielectric pattern 200. The third length W3 of the third region 200R3 of the first dielectric pattern 200 and the fourth length W4 of the fourth region 200R4 of the first dielectric pattern 200 may be less than the first length W1 of the first region 200R1 of the first dielectric pattern 200.

[0143] A spacer material 170 may be disposed between the third region 200R3 of the first dielectric pattern 200 and the first source / drain region 121. A spacer material 170 may be disposed between the fourth region 200R4 of the first dielectric pattern 200 and the fourth source / drain region 124.

[0144] Hereinafter, a method for manufacturing a semiconductor device according to several embodiments of the present invention will be described with reference to Figures 13 to 27. For clarity, parts that are repeated in the description will be simplified or omitted.

[0145] Figure 13 is a flowchart illustrating a method for manufacturing a semiconductor device according to several embodiments of the present invention.

[0146] Referring to FIG13, a method for manufacturing a semiconductor device according to several embodiments of the present invention may include step S100 of forming a pin pattern.

[0147] Figures 14 and 15 are used to illustrate step S100 of Figure 13 and can be perspective views of a semiconductor device.

[0148] Referring to Figures 13 and 14, a first layer 501 and a second layer 502 can be alternately stacked on a substrate. For example, the substrate with alternately stacked first layers 501 and second layers 502 can be a punch-stop (PTS) ion implantation region serving as a first region 101 of the substrate. For example, a first layer 501 and a second layer 502 can be alternately stacked on a first region 101 of the substrate.

[0149] Referring to Figures 13 and 15, a lead pattern FP can be formed. For example, a structure with alternating layers of first layer 501 and second layer 502 is patterned to form a lead pattern FP, and a second region 102 is formed below the lead pattern FP, thereby forming a substrate 100.

[0150] Referring again to FIG13, the manufacturing method of a semiconductor device according to several embodiments of the present invention may include step S200 of forming a dummy wall.

[0151] Figure 16 is a diagram illustrating step S200 of Figure 13 and can be a perspective view of the semiconductor device.

[0152] Referring to Figures 13 and 16, a virtual wall (DW) surrounding the lead pattern FP can be formed on the substrate 100. The virtual wall (DW) can be formed on a second region 102 of the substrate 100. The virtual wall (DW) can cover all sidewalls and the top surface of the lead pattern FP.

[0153] Referring again to FIG13, a method for manufacturing a semiconductor device according to several embodiments of the present invention may include step S300 of forming a first virtual pattern and a second virtual pattern spaced apart from each other.

[0154] Figure 17, used to illustrate step S300 of Figure 13, can be a perspective view of the semiconductor device.

[0155] Referring to Figures 13 and 17, the virtual wall DW is patterned and can form a first virtual pattern DW1, a second virtual pattern DW2, and a third virtual pattern DW3 that are spaced apart from each other. The virtual wall DW can be patterned using a mask pattern MP. The first virtual pattern DW1, the second virtual pattern DW2, and the third virtual pattern DW3 can expose a portion of the second region 102 of the substrate 100.

[0156] Referring again to FIG13, a method for manufacturing a semiconductor device according to several embodiments of the present invention may include step S400 of forming a first dielectric pattern.

[0157] Figure 18, used to illustrate step S400 of Figure 13, can be a perspective view of the semiconductor device.

[0158] Referring to Figures 13 and 18, the mask pattern MP of Figure 17 can be removed, and a portion of each of the first virtual pattern DW1, the second virtual pattern DW2, and the third virtual pattern DW3 can be removed to expose the upper surface of the second layer 502. A first dielectric pattern 200 can be formed between the first virtual pattern DW1 and the second virtual pattern DW2. The first dielectric pattern 200 can be formed between the second virtual pattern DW2 and the third virtual pattern DW3. The first dielectric pattern 200 can cover the sidewalls of each of the first virtual pattern DW1, the second virtual pattern DW2, and the third virtual pattern DW3. The first dielectric pattern can be formed on a portion of the second region 102 of the substrate 100 exposed when the first virtual pattern DW1, the second virtual pattern DW2, and the third virtual pattern DW3 are formed.

[0159] Referring again to FIG13, a method for manufacturing a semiconductor device according to several embodiments of the present invention may include step S500 of forming a first source / drain region.

[0160] Figures 19 and 20 are used to illustrate step S500 of Figure 13 and can be perspective views of a semiconductor device.

[0161] Referring to Figures 13 and 19, a dummy gate DG can be formed on the structure of Figure 18. For example, the dummy gate DG can be formed on a second dummy pattern DW2.

[0162] The second part 2002 of the first dielectric pattern 200 can be formed by forming a virtual gate DG.

[0163] Referring to Figures 13 and 20, portions of the first layer 501 and the second layer 502 exposed through the virtual gate DG can each be removed. Spacer material can be filled into the sidewalls of the virtual gate DG to form free spacers 170p. The free spacers 170p can be formed side-by-side with the second portion 2002 of the first dielectric pattern 200.

[0164] A first source / drain region 121 can be formed between the first virtual patterns DW1, and a second source / drain region 122 can be formed between the third virtual patterns DW3. The first source / drain region 121 can be formed on one sidewall of the free spacer 170p on the first region 101 of the substrate 100. The second source / drain region 122 can be formed on the other sidewall of the free spacer 170p on the first region 101 of the substrate 100.

[0165] Referring again to FIG13, a method for manufacturing a semiconductor device according to several embodiments of the present invention may include step S600 of forming a first gate structure surrounding a first layer.

[0166] Figures 21 to 24 are diagrams used to illustrate step S600 of Figure 13.

[0167] Referring to Figures 13 and 21, a spacer material 170 can be formed. The spacer material 170 can be formed on one sidewall of the free spacer 170p, the upper surface of the first source / drain region 121, the upper surface of the first dummy pattern DW1, a portion of the sidewall of the first dummy pattern DW1, and a portion of the upper surface of the first dielectric pattern 200. The spacer material 170 can also be formed on the other sidewall of the free spacer 170p, the upper surface of the second source / drain region 122, the upper surface of the third dummy pattern DW3, a portion of the sidewall of the third dummy pattern DW3, and another portion of the upper surface of the first dielectric pattern 200.

[0168] The virtual gate (DG) can be removed.

[0169] Figure 22 is a cross-sectional view cut along line XX of Figure 21.

[0170] Referring to Figures 13 and 22, by removing the second virtual pattern DW2, a second virtual hole DW2H can be formed between the first dielectric pattern 200 and the pin pattern FP.

[0171] Figure 23 is a cross-sectional view cut along the XX line of Figure 21.

[0172] Referring to Figures 13 and 23, after forming the second virtual hole DW2H, the second layer 502 of the pin pattern FP can be removed.

[0173] Figure 24 is a cross-sectional view taken along line XX of Figure 21.

[0174] Referring to Figures 13 and 24, a first gate structure 111 can be formed in the portion where the second layer 502 is removed.

[0175] The first gate insulating film 161 can be formed on the portion exposed by removing the second layer 502. For example, the first gate insulating film 161 can surround the first layer 501. The first gate insulating film 161 can be formed on the substrate 100. The first gate insulating film 161 can be formed along the sidewall of the first dielectric pattern 200.

[0176] The first gate electrode 111e can be formed to fill the portion remaining after the formation of the first gate insulating film 161. The first gate electrode 111e can surround the first layer 501. The first gate electrode 111e can be formed between the substrate 100 and the first layer 501, and can be formed between the first layer 501 and the first dielectric pattern 200.

[0177] Referring again to FIG13, a method for manufacturing a semiconductor device according to several embodiments of the present invention may include step S700 of removing a first virtual pattern.

[0178] Figures 25 to 27 are cross-sectional views taken along the YY line of Figure 21.

[0179] Referring to Figures 13, 25, and 26, the first dummy pattern DW1 between the first source / drain region 121 and the first dielectric pattern 200 can be removed. The third dummy pattern DW3 between the second source / drain region 122 and the first dielectric pattern 200 can also be removed.

[0180] A first virtual hole DW1H can be formed by removing the first virtual pattern DW1. A third virtual hole can also be formed by removing the portion containing the third virtual pattern DW3.

[0181] Referring to Figures 13 and 27, a first silicate pattern 131 can be formed in the first virtual via DW1H. The first silicate pattern 131 can be formed between the first source / drain region 121 and the first dielectric pattern 200, and can also be formed on the first source / drain region 121.

[0182] In the semiconductor device and manufacturing method of the present invention, a patterned dielectric pattern is provided between a plurality of transistors of the same type, thereby reducing the spacing between the plurality of transistors of the same type. Furthermore, in the semiconductor device and manufacturing method of the present invention, a portion of the dielectric pattern (e.g., first portion 2001 and second portion 2002) is provided between the gate structure and the source / drain pattern, thereby completely surrounding the active pattern operating in the channel region with the gate structure, thereby improving the control capability of the gate and reducing electrical losses. Additionally, in the semiconductor device and manufacturing method of the present invention, a silicon pattern is provided between the dielectric pattern and the source / drain region, thereby reducing parasitic resistance.

[0183] The above description is merely illustrative of the technical concept of this embodiment. Those skilled in the art can make various modifications and variations without departing from the essential characteristics of this embodiment. Therefore, this embodiment is not intended to limit the technical concept of this embodiment, and the scope of the technical concept of this embodiment is not limited to this embodiment. The scope of protection of this embodiment is explained by the following claims of the invention; all technical concepts within the equivalent scope should be included within the scope of protection of this embodiment.

[0184] 100:Substrate 101: Area 1 102: Second Area 111: First gate structure 111e: First gate electrode 111P: Part of the first gate structure 112: Second gate structure 112e: Second gate electrode 113: Third gate structure 113e: Third gate electrode 121: First source / drain region 122: Second source / drain region 123: Third source / drain region 124: Fourth source / drain region 125: Fifth source / drain region 126: Sixth source / drain region 131: First silicate pattern 132: Second silicate pattern 141: First active pattern 142: Second active pattern 143: Third Active Pattern 150:Contact Department 161: First gate insulating film 162: Second gate insulating film 163: Third gate insulating film 170: Spacing material 170p: Free Spacer 200: First dielectric pattern 200R1: First region of the first dielectric pattern 200R2: Second region of the first dielectric pattern 200R3: The third region of the first dielectric pattern 200R4: The fourth region of the first dielectric pattern 300: Second dielectric pattern 300R1: First region of the second dielectric pattern 300R2: Second region of the second dielectric pattern 501: Alternating stacking of the first layer 502: Alternating layers of the second layer TR1: First transistor TR2: Second transistor TR3: Third transistor 1111: First part of the first gate structure 1112: The second part of the first gate structure 1111S: First side of the first gate structure 1112S: The second side of the first gate structure 1113S: The third side of the first gate structure 1114S: The fourth side of the first gate structure 1125S: The fifth side of the second gate structure 1126S: The sixth side of the second gate structure 2001: First part of the first dielectric pattern 2001i: First recessed portion 2002: Second part of the first dielectric pattern 2002i: Second recessed portion 2003: Part 3 of the first dielectric pattern 2004: Part Four of the First Dielectric Pattern 3001: The fifth part of the second dielectric pattern 3002: The sixth part of the second dielectric pattern S100, S200, S300, S400, S500, S600, S700: Steps FP: Pin pattern DG: Virtual Gate DW: Virtual Wall DW1: First Virtual Pattern DW1H: First virtual hole DW2: Second Virtual Pattern DW2H: Second virtual hole DW3: Third Virtual Pattern MP: Mask pattern

Claims

1. A semiconductor device, wherein, include: substrate; A first active pattern is formed on the substrate; A first gate structure surrounds at least a portion of the first active pattern; The first source / drain region and the second source / drain region are respectively disposed on the first side and the second side facing each other of the first gate structure; And a first dielectric pattern, disposed on a third side that is different from the first side and the second side of the first gate structure, the first dielectric pattern comprising: a first portion of the first dielectric pattern disposed between the first source / drain region and the first side of the first gate structure; And a second portion of the first dielectric pattern is disposed between the second source / drain region and the second side of the first gate structure.

2. The semiconductor device as claimed in claim 1, wherein, The first gate structure includes a portion of the first gate structure disposed between the first active pattern and the first dielectric pattern along a second direction intersecting the first direction, the first direction being perpendicular to the first gate structure and the substrate.

3. The semiconductor device as claimed in claim 2, wherein, The portion of the first gate structure is disposed between the first portion and the second portion of the first dielectric pattern.

4. The semiconductor device as claimed in claim 1, wherein, It also includes: a first silicide pattern disposed between the first source / drain region and the first dielectric pattern; and a second silicide pattern disposed between the second source / drain region and the first dielectric pattern.

5. The semiconductor device as claimed in claim 1, wherein, It also includes: a second active pattern formed on the substrate; and a second gate structure surrounding at least a portion of the second active pattern, wherein the first dielectric pattern is disposed between the first gate structure and the second gate structure, and between the first active pattern and the second active pattern, wherein a first region of the first dielectric pattern between the first active pattern and the second active pattern has a first width, and a second region of the first dielectric pattern between the first gate structure and the second gate structure has a second width, wherein the first width and the second width are different, and the first region of the first dielectric pattern includes the first portion.

6. The semiconductor device as claimed in claim 5, wherein, The first width is greater than the second width.

7. The semiconductor device as claimed in claim 5, wherein, It also includes a third source / drain region and a fourth source / drain region, respectively disposed on the fifth and sixth sides of the second gate structure facing each other. The first dielectric pattern includes: a third portion of the first dielectric pattern disposed between the third source / drain region and the fifth side of the second gate structure; and a fourth portion of the first dielectric pattern disposed between the fourth source / drain region and the sixth side of the second gate structure. The first region of the first dielectric pattern includes the third portion.

8. The semiconductor device as claimed in claim 7, wherein, The third region of the first dielectric pattern between the first source / drain region and the third source / drain region has a third width, and the fourth region of the first dielectric pattern between the second source / drain region and the fourth source / drain region has a fourth width, wherein the third width and the fourth width are different.

9. The semiconductor device as claimed in claim 1, wherein, The first portion of the first gate structure disposed between the first portion and the second portion of the first dielectric pattern has a first width, and the second portion of the first gate structure disposed between the first source / drain and the second source / drain and disposed on the first active pattern has a second width. The first width of the first portion of the first gate structure is different from the second width of the second portion of the first gate structure.

10. The semiconductor device as claimed in claim 1, wherein, The first portion of the first dielectric pattern further includes a first recessed portion recessed into the first source / drain region.

11. The semiconductor device as claimed in claim 10, wherein, The second portion of the first dielectric pattern further includes a second recessed portion recessed into the first source / drain region.

12. A semiconductor device, wherein, include: substrate; A first transistor of the first type includes a first active pattern on the substrate and a first gate structure surrounding the first active pattern; A second transistor of the second type includes a second active pattern on the substrate and a second gate structure surrounding the second active pattern; a patterned first dielectric pattern is disposed between the first transistor and the second transistor; a third transistor of the second type includes a third active pattern on the substrate and a third gate structure surrounding the third active pattern; and a patterned second dielectric pattern is disposed between the second transistor and the third transistor, wherein a first region of the second dielectric pattern between the second active pattern and the third active pattern has a first width, and a second region of the second dielectric pattern between the second gate structure and the third gate structure has a second width, wherein the first width and the second width are different.

13. The semiconductor device as claimed in claim 12, wherein, It also includes a first source / drain region and a second source / drain region respectively disposed on a first side and a second side facing each other in the first gate structure. The first dielectric pattern is disposed on a third side that is different from the first side and the second side. The first dielectric pattern includes: a first portion of the first dielectric pattern disposed between the first source / drain region and the first side of the first gate structure; and a second portion of the first dielectric pattern disposed between the second source / drain region and the second side of the first gate structure.

14. The semiconductor device as claimed in claim 13, wherein, It also includes a third source / drain region and a fourth source / drain region respectively disposed on the fifth and sixth sides of the second gate structure facing each other. The first dielectric pattern includes: a third portion of the first dielectric pattern disposed between the third source / drain region and the fifth side of the second gate structure; and a fourth portion of the first dielectric pattern disposed between the fourth source / drain region and the sixth side of the second gate structure.

15. The semiconductor device as claimed in claim 14, wherein, The second dielectric pattern includes: a fifth portion of the second dielectric pattern disposed between the third source / drain region and the fifth side of the second gate structure; and a sixth portion of the second dielectric pattern disposed between the fourth source / drain region and the sixth side of the second gate structure.

16. The semiconductor device as claimed in claim 14, wherein, The third region of the first dielectric pattern between the first source / drain region and the third source / drain region has a third width, and the fourth region of the first dielectric pattern between the second source / drain region and the fourth source / drain region has a fourth width, wherein the third width and the fourth width are different.

17. The semiconductor device as claimed in claim 13, wherein, The first portion of the first gate structure disposed between the first portion and the second portion of the first dielectric pattern has a first width, and the second portion of the first gate structure disposed between the first source / drain and the second source / drain and disposed on the first active pattern has a second width. The first width of the first portion of the first gate structure is different from the second width of the second portion of the first gate structure.

18. The semiconductor device as claimed in claim 13, wherein, The first portion of the first dielectric pattern further includes a first recessed portion recessed into the first source / drain region.

19. The semiconductor device as claimed in claim 18, wherein, The second portion of the first dielectric pattern further includes a second recessed portion recessed into the first source / drain region.

20. A method for manufacturing a semiconductor device, wherein, The process includes the following steps: patterning a lead pattern after alternately stacking a first layer and a second layer on a substrate; forming a dummy wall surrounding the lead pattern on the substrate; patterning the dummy wall to form a first dummy pattern and a second dummy pattern spaced apart from each other; and forming a first dielectric pattern between the first dummy pattern and the second dummy pattern, covering the sidewalls of the first dummy pattern and the second dummy pattern, respectively. A portion of the pin pattern on the first virtual pattern side is removed to form the first source / drain region; Remove the second dummy pattern and the second layer to form a first gate structure surrounding the first layer; And remove the first virtual pattern.

21. A method for manufacturing a semiconductor device as claimed in claim 20, wherein, It also includes the step of forming a silicon pattern between the first dielectric pattern and the first source / drain region after removing the first virtual pattern.

22. A method for manufacturing a semiconductor device as claimed in claim 20, wherein, The first dielectric pattern includes a first portion of the first dielectric pattern disposed between the first source / drain region and the first gate structure.

23. A method for manufacturing a semiconductor device as claimed in claim 20, wherein, The steps of forming the first virtual pattern and the second virtual pattern further include the steps of forming a third virtual pattern separated from the first virtual pattern and the second virtual pattern, wherein the first dielectric pattern is also formed between the second virtual pattern and the third virtual pattern and covers the sidewall of the third virtual pattern, and the method of manufacturing the semiconductor device further includes the steps of removing another portion of the pin pattern on the third virtual pattern side to form a second source / drain region; and removing the third virtual pattern.

24. A method for manufacturing a semiconductor device as claimed in claim 23, wherein, The first dielectric pattern includes: a first portion of the first dielectric pattern disposed between the first source / drain region and a first side of the first gate structure; and a second portion of the first dielectric pattern disposed between the second source / drain region and a second side of the first gate structure.

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