Semiconductor structure

Abstract

A semiconductor structure includes a carrier wafer and a plurality of wafers. The plurality of wafers are stacked on the carrier wafer. Adjacent wafers are bonded to each other. Each wafer includes a plurality of memory arrays and a plurality of input / output circuits. The plurality of input / output circuits are located next to the plurality of memory arrays. Adjacent input / output circuits are mirror-symmetrical.

Claims

1. A semiconductor structure, comprising: Carrying wafer; And multiple chips, stacked on the carrier wafer, wherein two adjacent chips are bonded to each other, each chip includes multiple memory arrays and multiple input / output circuits, the multiple input / output circuits are located next to the multiple memory arrays, and two adjacent input / output circuits are mirror symmetrical.

2. The semiconductor structure as claimed in claim 1, wherein the carrier wafer includes a controller wafer.

3. The semiconductor structure as claimed in claim 1, wherein the plurality of memory arrays include a plurality of dynamic random access memory arrays.

4. The semiconductor structure as claimed in claim 1, wherein the plurality of said input / output circuits are located between the plurality of said memory arrays.

5. The semiconductor structure as claimed in claim 1, wherein each of the wafers further comprises: Multiple decoders, wherein each decoder is located between the corresponding input / output circuit and the corresponding memory array.

6. The semiconductor structure as claimed in claim 5, wherein each of the wafers further comprises: Multiple multiplexers, wherein each multiplexer is located between the corresponding input / output circuit and the corresponding decoder.

7. The semiconductor structure as claimed in claim 1, wherein the wafer closest to the carrier wafer is bonded to the carrier wafer.

8. The semiconductor structure of claim 1, wherein the front side of the wafer most adjacent to the carrier wafer is bonded to the front side of the carrier wafer.

9. The semiconductor structure of claim 1, wherein the interface between the wafer and the carrier wafer closest to the carrier wafer includes a hybrid bonding interface.

10. The semiconductor structure of claim 1, wherein the interface between the wafer and the carrier wafer most adjacent to the carrier wafer includes a bump bonding interface.

11. The semiconductor structure of claim 1, wherein the back side of one of two adjacent wafers is bonded to the back side of the other of two adjacent wafers.

12. The semiconductor structure of claim 1, wherein the front side of one of two adjacent wafers is bonded to the front side of the other of two adjacent wafers.

13. The semiconductor structure of claim 1, wherein the front side of one of two adjacent wafers is bonded to the back side of the other of two adjacent wafers.

14. The semiconductor structure as claimed in claim 1, wherein the interface between two adjacent wafers includes a hybrid bonding interface.

15. The semiconductor structure of claim 1, wherein the interface between two adjacent wafers includes a bump bonding interface.

16. The semiconductor structure of claim 1, wherein the stacking structure of the wafer and the carrier wafer most adjacent to the carrier wafer includes a wafer-on-wafer stacking structure.

17. The semiconductor structure of claim 1, wherein the stacking structure of the wafer and the carrier wafer most adjacent to the carrier wafer includes a wafer-on-wafer stacking structure.

18. The semiconductor structure of claim 1, wherein the stacked structure of the plurality of said wafers includes a wafer-on-wafer stacked structure.

19. The semiconductor structure of claim 1, wherein the stacked structure of the plurality of said wafers includes a wafer-on-wafer stack.

20. The semiconductor structure of claim 1, wherein the stacking structure of the plurality of said wafers and the carrier wafer includes a wafer-on-wafer stacking structure.

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