Semiconductor device and method of manufacturing the same

Abstract

A method of manufacturing a semiconductor device includes forming a device isolation structure within a substrate to define an active region, wherein the active region includes an edge region and a central region located between the edge regions; then forming a well region within the active region; first forming a plurality of lightly doped drain (LDD) regions within the well region; and then forming a gate structure across the active region on the substrate. The LDD regions are used to ensure that the average doping concentration of the edge regions below the gate structure is less than the average doping concentration of the central region below the gate structure. Source / drain regions are formed within the LDD regions.

Claims

1. A method for manufacturing a semiconductor device, comprising: A device isolation structure is formed within a substrate to define an active region, wherein the active region includes an edge region and a central region located between the edge regions; a well region is formed within the active region; a plurality of lightly doped drain (LDD) regions are formed within the well region; a gate structure is formed on the substrate spanning the active region, and the average doping concentration of the edge region below the gate structure is less than the average doping concentration of the central region below the gate structure by means of the plurality of LDD regions, wherein the average doping concentration is the average of the doping concentrations of the plurality of LDD regions and the well region; and a source / drain region is formed within the plurality of LDD regions.

2. A method of manufacturing a semiconductor device as claimed in claim 1, wherein the method of forming the plurality of LDD regions includes forming a doped region having a first width in the edge region and forming a doped region having a second width in the central region, wherein the first width is smaller than the second width.

3. A method of manufacturing a semiconductor device as claimed in claim 2, wherein, in a top view, the edge of the doped region having the first width is aligned with the sidewall of the gate structure.

4. A method of manufacturing a semiconductor device as claimed in claim 2, wherein, in a top view, the doped region having the first width partially overlaps with the gate structure.

5. A method of manufacturing a semiconductor device as claimed in claim 2, wherein, in a top view, the doped region having the first width does not overlap with the gate structure.

6. A method of manufacturing a semiconductor device as claimed in claim 1, wherein, in a top view, the plurality of LDD regions are two asymmetric L-shaped doped regions.

7. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the method for forming the plurality of LDD regions comprises: Two rectangular doped regions were formed within this well area; And perform a dedoping process on the two rectangular doped regions within the edge region to reduce the average doping concentration of the edge region.

8. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the method for forming the plurality of LDD regions comprises: Two rectangular doped regions were formed within this well area; And another ion implantation process is performed on the two rectangular doped regions in the central region to increase the average doping concentration in the central region.

9. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of forming the gate structure includes: A gate oxide layer, a high dielectric constant material layer, a barrier layer, a polysilicon layer, a dummy gate layer, and a hard mask layer are sequentially formed on the surface of the substrate; the hard mask layer is patterned; the patterned hard mask layer is used as an etching mask to etch the dummy gate layer, the barrier layer, the high dielectric constant material layer, and the gate oxide layer; and the dummy gate layer is replaced with a metal gate using a gate replacement process.

10. A method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of forming the gate structure includes: A gate oxide layer, a gate layer, and a hard mask layer are sequentially formed on the surface of the substrate. Pattern the rigid mask layer; The patterned hard mask layer is used as an etching mask to etch the gate layer and the gate oxide layer; and the hard mask layer is removed.

11. A semiconductor device, comprising: Base; A device isolation structure is formed on the substrate to define an active region, wherein the active region includes an edge region and a central well region located between the edge regions, formed within the active region; a gate structure is formed on the surface of the substrate and spans the active region; a plurality of lightly doped drain (LDD) regions are formed within the well region such that the average doping concentration of the edge region below the gate structure is less than the average doping concentration of the central region below the gate structure, wherein the average doping concentration is the average of the doping concentrations of the plurality of LDD regions and the well region; and a source / drain region is formed within the plurality of LDD regions.

12. The semiconductor device of claim 11, wherein the plurality of LDD regions include a doped region having a first width in the edge region and a doped region having a second width in the central region, and the first width is smaller than the second width.

13. The semiconductor device of claim 12, wherein, in a top view, the edge of the doped region having the first width is aligned with the sidewall of the gate structure.

14. The semiconductor device of claim 12, wherein, in a top view, the doped region having the first width partially overlaps with the gate structure.

15. The semiconductor device of claim 12, wherein, in a top view, the doped region having the first width does not overlap with the gate structure.

16. The semiconductor device of claim 11, wherein the plurality of LDD regions are two asymmetric L-shaped doped regions.

17. The semiconductor device of claim 11, wherein the gate structure comprises an HKMG structure or a poly-SiON structure.

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