Non-volatile memory and programming method thereof

Abstract

This invention provides a non-volatile memory and a programming method thereof. The non-volatile memory can be a three-dimensional NAND flash memory with high capacity and high performance. The non-volatile memory includes a memory cell array and control circuitry. During programming of multiple memory cells of a current word line, the control circuitry reads at least one critical voltage of at least one adjacent word line. The control circuitry checks the at least one critical voltage of the at least one adjacent word line to generate a check result. Based on the check result, the control circuitry adjusts the programming verification voltage used to verify the current word line during programming.

Claims

1. A non-volatile memory, comprising: A memory cell array having a plurality of memory cells, wherein each of a plurality of word lines is coupled to a plurality of memory cells in a corresponding column of the memory cells, and each of a plurality of bit lines is coupled to a plurality of memory cells in a corresponding row of the memory cells. A control circuit coupled to the memory cell array, wherein, during a programming process of multiple memory cells programming a current character line among the character lines, the control circuit reads at least one critical voltage of at least one adjacent character line adjacent to the current character line; the control circuit checks the at least one critical voltage of the at least one adjacent character line to generate a check result; based on the check result, the control circuit adjusts a programming verification voltage used to verify the current character line during the programming process; the programming process includes multiple programming loops; the control circuit reads the at least one critical voltage of the at least one adjacent character line in a selected programming loop among the programming loops; and in the selected programming loop, and in other programming loops after the selected programming loop, the control circuit adjusts the programming verification voltage used to verify the current character line based on the check result.

2. The non-volatile memory as claimed in claim 1, wherein during the programming period, the control circuit reads the at least one threshold voltage of the at least one adjacent word line only in the selected programming cycle.

3. The non-volatile memory as claimed in claim 1, wherein the selected programming cycle includes a programming phase, a read phase, and a programming verification phase, the control circuit programs the memory cells of the current character line in the programming phase, the control circuit reads the at least one threshold voltage of the at least one adjacent character line in the read phase, and the control circuit adjusts the programming verification voltage used to verify the current character line based on the check result in the programming verification phase.

4. The non-volatile memory as claimed in claim 1, wherein the selected programming cycle includes a programming phase and a programming verification phase, the programming verification phase including a read period and a programming verification period, the control circuit programming the memory cells of the current character line in the programming phase, the control circuit reading the at least one threshold voltage of the at least one adjacent character line in the read period of the programming verification phase, and the control circuit adjusting the programming verification voltage used to verify the current character line according to the check result in the programming verification period of the programming verification phase.

5. The non-volatile memory as claimed in claim 1, wherein the at least one adjacent character line includes a first adjacent character line, the control circuit compares a first threshold voltage of the first adjacent character line with a threshold to generate the check result; in response to the first threshold voltage being less than the threshold, the control circuit sets the programmed verification voltage used to verify the current character line to a first verification voltage level; and in response to the first threshold voltage being greater than the threshold, the control circuit sets the programmed verification voltage used to verify the current character line to a second verification voltage level less than the first verification voltage level.

6. The non-volatile memory as claimed in claim 1, wherein the at least one adjacent word line includes a first adjacent word line and a second adjacent word line, the control circuit compares a first threshold voltage of the first adjacent word line, a second threshold voltage of the second adjacent word line, and a threshold to generate the check result; in response to the first threshold voltage being less than the threshold and in response to the second threshold voltage being less than the threshold, the control circuit sets the programmed verification voltage used to verify the current word line to a first verification voltage level; in response to the first threshold voltage being less than the threshold and in response to the second threshold voltage being greater than the threshold, the control circuit sets the programmed verification voltage used to verify the current word line to a second verification voltage level less than the first verification voltage level; In response to the first threshold voltage being greater than the threshold and in response to the second threshold voltage being less than the threshold, the control circuit sets the programmed verification voltage used to verify the current character line to the second verification voltage level; and in response to the first threshold voltage being greater than the threshold and in response to the second threshold voltage being greater than the threshold, the control circuit sets the programmed verification voltage used to verify the current character line to a third verification voltage level that is less than the second verification voltage level.

7. A programming method applicable to a non-volatile memory, the programming method comprising: During a programming process that programs a plurality of first memory cells of a current character line, at least one threshold voltage of at least one adjacent character line is read; the at least one threshold voltage of the at least one adjacent character line is checked to generate a check result; based on the check result, a programming verification voltage used to verify the current character line during the programming process is adjusted, wherein the programming process includes a plurality of programming loops; in a selected programming loop of the programming loops, the at least one threshold voltage of the at least one adjacent character line is read; and in the selected programming loop and in other programming loops following the selected programming loop, the programming verification voltage used to verify the current character line is adjusted based on the check result.

8. The programming method as described in claim 7, wherein during the programming period, the at least one critical voltage of the at least one adjacent word line is read only in the selected programming cycle.

9. The programming method as described in claim 7, wherein the selected programming loop includes a programming phase, a reading phase, and a programming verification phase, the programming method further comprising: In this programming phase, these memory cells of the current character line are programmed; In the read phase, the at least one critical voltage of the at least one adjacent character line is read; and in the programmable verification phase, the programmable verification voltage used to verify the current character line is adjusted based on the check result.

10. The programming method as described in claim 7, wherein the selected programming loop includes a programming phase and a programming verification phase, the programming verification phase including a read period and a programming verification period, the programming method further including: The programmable phase programs the memory cells of the current character line; the programmable verification phase reads the at least one critical voltage of the at least one adjacent character line during the read phase; and the programmable verification phase adjusts the programmable verification voltage used to verify the current character line based on the check result during the programmable verification phase.

11. The programming method as described in claim 7, wherein the at least one adjacent character line includes a first adjacent character line, the programming method further comprising: The check result is generated by comparing a first threshold voltage of the first adjacent character line with a threshold; in response to the first threshold voltage being less than the threshold, the programmed verification voltage used to verify the current character line is set to a first verification voltage level; and in response to the first threshold voltage being greater than the threshold, the programmed verification voltage used to verify the current character line is set to a second verification voltage level less than the first verification voltage level.

12. The programming method as described in claim 7, wherein the at least one neighboring character line includes a first neighboring character line and a second neighboring character line, the programming method further comprising: The check result is generated by comparing a first threshold voltage of the first adjacent character line, a second threshold voltage of the second adjacent character line, and a threshold. In response to the first threshold voltage being less than the threshold and the second threshold voltage being less than the threshold, the programmed verification voltage used to verify the current character line is set to a first verification voltage level. In response to the first threshold voltage being less than the threshold and the second threshold voltage being greater than the threshold, the programmed verification voltage used to verify the current character line is set to a second verification voltage level lower than the first verification voltage level. In response to the first threshold voltage being greater than the threshold and the second threshold voltage being less than the threshold, the programmed verification voltage used to verify the current character line is set to the second verification voltage level. And in response to the first threshold voltage being greater than the threshold and the second threshold voltage being greater than the threshold, the programmed verification voltage used to verify the current character line is set to a third verification voltage level lower than the second verification voltage level.

Images