Memory device

Abstract

To reduce the manufacturing cost of memory devices. The implemented memory device includes first and second conductive members, a plurality of memory cells, and shielding electrodes. Each of the first and second conductive members is arranged extending in a first direction. The first and second conductive members are arranged side-by-side in a second direction. The plurality of memory cells are arranged side-by-side in the first direction. Each of the plurality of memory cells includes a first and a second transistor arranged side-by-side in the second direction. The first transistor has a gate electrode and a channel region electrically connected to the first conductive member. The second transistor has a channel region electrically connected to the aforementioned second conductive member and a gate electrode electrically connected to the channel region of the aforementioned first transistor. The shielding electrode is located between two adjacent memory cells in the first direction, and is electrically connected to the aforementioned second conductive member, and is arranged to overlap with the gate electrode of the second transistor in the first direction.

Description

[Technical Field]

[0001] Implementation form relates to a memory device. [Previous Technology]

[0002] It is well known that DRAM (Dynamic Random Access Memory) has memory cells that are stacked in 3D. [Summary of the Invention]

[0003] A low-cost 3D laminated memory is provided. An embodiment of the memory device includes a substrate, a first conductive member and a second conductive member, a plurality of memory cells, and a shielding electrode. Each of the first and second conductive members is disposed extending in a first direction intersecting the surface of the substrate. The first and second conductive members are arranged side-by-side in a second direction parallel to the surface of the substrate. The plurality of memory cells are arranged side-by-side in the first direction. Each of the plurality of memory cells includes a first transistor and a second transistor arranged side-by-side in the second direction. The first transistor has a gate electrode and a channel region electrically connected to the first conductive member. The second transistor has a channel region electrically connected to the aforementioned second conductive member and a gate electrode electrically connected to the channel region of the aforementioned first transistor. The shielding electrode is located at each of two adjacent memory cells in the first direction among a plurality of memory cells, is electrically connected to the second conductive member, and is arranged in such a way that it overlaps with the gate electrode of the second transistor in the first direction.

Implementation Method

[0005] Hereinafter, various embodiments will be described with reference to the drawings. Each embodiment is an example of a device and method used to concretize the technical idea of ​​the invention. The drawings are schematic or conceptual. The dimensions and proportions of each drawing are not necessarily identical to those of the actual object. In the following description, the same element symbols are added for constituent elements that have slightly similar functions and structures.

[0006] In this specification, a specific direction parallel to the top surface of the substrate is referred to as the "X direction". A direction parallel to the top surface of the substrate and perpendicular to the X direction is referred to as the "Y direction". A direction perpendicular to the top surface of the substrate is referred to as the "Z direction". A cross-section parallel to both the X and Z directions is referred to as the "XZ cross-section". A cross-section parallel to both the X and Y directions is referred to as the "XY cross-section". Furthermore, in this specification, the terms "up" or "down" are used with the substrate as a reference. For example, if the direction moving away from the substrate along the Z direction is called "up", then the direction moving towards the substrate along the Z direction is called "down". Also, when referring to a particular configuration as "below" or "lower end", it refers to the side surface or end of the substrate of that configuration. When referring to a particular component as "top" or "upper end," it means the side or end of that component opposite to the substrate. Furthermore, the surface intersecting the X or Y direction is called the "side surface."

[0007] <1> First Embodiment The memory device 100 of the first embodiment is a type of DRAM (Dynamic Random Access Memory) having memory cells that are stacked in three dimensions. Hereinafter, the memory device 100 of the first embodiment will be described in detail.

[0008] <1-1>Construction First, the construction of the memory device 100 in the first embodiment will be explained using Figures 1 to 6.

[0009] <1-1-1> Figure 1 is a block diagram illustrating one example of the configuration of a memory system 1 having the memory device 100 of the first embodiment. As shown in Figure 1, the memory system 1 includes, for example, a memory device 100 and a memory controller 200. The memory device 100 is connected to the memory controller 200 and is configured to read and write data based on commands from the memory controller 200. The memory device 100, for example, receives an address ADR, an instruction CMD, data DT, and a control signal CNT from the memory controller 200. The memory device 100 sends the control signal CNT and the data DT to the memory controller 200. The memory device 100, for example, includes a memory cell array 110, a row control circuit 120, a column control circuit 130, a read / write circuit 140, an input / output circuit 150, and a control circuit 160.

[0010] The memory cell array 110 is a circuit used for storing data. Although not illustrated, the memory cell array 110, for example, includes a plurality of memory cells MC, a plurality of word lines, and a plurality of bit lines. Each memory cell MC is capable of storing at least 1 bit of data. The plurality of word lines includes a plurality of write word lines WWL and a plurality of read word lines RWL. The plurality of bit lines includes a plurality of write bit lines WBL and a plurality of read bit lines RBL. Each memory cell MC is connected to a pair of write word lines WWL and read word lines RWL and a pair of write bit lines WBL and read bit lines RBL. At the pair of write word lines WWL and read word lines RWL, for example, a row address is allocated. At the pair of write bit lines WBL and read bit lines RBL, for example, column addresses are allocated. Each memory cell (MC) can be identified by its row address and column address.

[0011] The row control circuit 120 controls the wiring (write character line WWL and read character line RWL) allocated in the row direction at the memory cell array 110. The row control circuit 120 selects (activates) character lines in response to the address ADR. Furthermore, the row control circuit 120 sets unselected character lines to an inactive state. Then, the row control circuit 120 supplies specific voltages to each of the selected and unselected character lines. The row control circuit 120, for example, includes a drive circuit for generating voltages applied to the character lines WL and an address decoder for decoding the address ADR. The row control circuit 120 is capable of selecting a pair of write character lines WWL and read character lines RWL based on the decoding result of the address ADR.

[0012] The column control circuit 130 controls the wiring (bit lines BL) allocated in the column direction at the memory cell array 110. The column control circuit 130, for example, includes an address decoder for decoding the address ADR and a sense amplifier. The sense amplifier amplifies the voltage of the read bit line RBL. For example, if the read word line RWL is activated by the row control circuit 120, the voltage of the read bit line RBL changes in response to the data (charge) stored in the interconnected memory cells MC. In this way, the sense amplifier amplifies the change in the voltage of the read bit line RBL to a voltage that can be read by the read / write circuit 140. Furthermore, the column control circuit 130 applies a voltage corresponding to the data to be written into the memory cell MC to the write bit line WBL. If the write character line WWL is activated by the row control circuit 120, then data (charge) is stored in the memory cell MC that is associated with the write character line WBL and the activated write character line WWL.

[0013] The read / write circuit 140 is configured to perform data writing to and data reading from the memory cell array 110. For example, when writing data, the read / write circuit 140 sends a signal (voltage or current) corresponding to "data requested to be written to the memory cell array 110" to the memory cell array 110 via the column control circuit 130. Similarly, when reading data, the read / write circuit 140 receives a signal (voltage or current) corresponding to "data read from the memory cell array 110" from the memory cell array 110 via the column control circuit 130. Then, the read / write circuit 140 reads (determines) the data stored in the memory cell MC by detecting changes in the voltage or current of the read bit line RBL. In addition, the memory device 100 may also have circuits for writing data and circuits for reading data that are independent of each other.

[0014] Input / output circuit 150 is an interface circuit that manages communication between memory device 100 and memory controller 200. Input / output circuit 150 receives instructions CMD, address ADR, data DT (e.g., data requested to be written to memory cell array 110) and multiple control signals CNT from memory controller 200. Input / output circuit 150 sends control signals CNT and data DT (e.g., data read from memory cell array 110) to memory controller 200.

[0015] The control circuit 160, based on the instruction CMD and the control signal CNT, controls the row control circuit 120, column control circuit 130, read / write circuit 140, etc., and performs the actions required by the memory device 100. The control circuit 160 controls the row control circuit 120, column control circuit 130, read / write circuit 140, etc., at a timing synchronized with the clock signal CLK. In the memory device 100, data writing and data reading are performed at a timing synchronized with the clock signal CLK. The clock signal CLK can be generated internally in the memory device 100 or supplied externally. Furthermore, the control circuit 160 can also be referred to as a sequencer, internal controller, etc.

[0016] <1-1-2> Structure of Memory Device 100 The structure of the memory device 100 according to the first embodiment will be described below. The following description pertains to the case where "the extension direction of the memory cell MC corresponds to the X direction, the extension direction of each of the write word line WWL and the read word line RWL corresponds to the Y direction, and the extension direction of each of the write bit line WBL and the read bit line RBL corresponds to the Z direction".

[0017] FIG2 is a perspective view showing one example of the structure of the memory device 100 according to the first embodiment. As shown in FIG2, the memory device 100 includes a semiconductor substrate SUB. A memory cell array 110 is disposed above the semiconductor substrate SUB. Hereinafter, the area where the memory cell array 110 is disposed will be referred to as the "memory region (MR)". The semiconductor substrate SUB is, for example, a silicon (Si) substrate containing P-type impurities such as boron (B). An insulating layer and an electrode layer (not shown) are disposed above the semiconductor substrate SUB. These insulating layers and electrode layers constitute a control circuit for controlling the memory device 100. For example, a sense amplifier is disposed in the area directly below the memory cell array 110.

[0018] The memory cell array 110 includes a plurality of memory cells MC, a plurality of write word lines WWL, a plurality of read word lines RWL, and a plurality of ground lines GND. Furthermore, the memory cell array 110 includes a plurality of memory layers ML arranged side-by-side in the Z direction. Each memory layer ML includes a pair of write word lines WWL and read word lines RWL arranged side-by-side in the X direction, and a plurality of memory cells MC arranged side-by-side in the Y direction. At each memory layer ML, each of the plurality of memory cells MC is respectively configured between a pair of write word lines WWL and read word lines RWL. Moreover, each of the plurality of memory cells MC is electrically connected to a pair of write word lines WWL and read word lines RWL.

[0019] At the memory region MR, a pair of write bit lines WBL and read bit lines RBL are arranged side by side in the X direction. At the memory region MR, a plurality of write bit lines WBL are arranged side by side in the Y direction. At the memory region MR, a plurality of read bit lines RBL are arranged side by side in the Y direction. A ground line GND is provided between each of the pair of write bit lines WBL and read bit lines RBL. That is, at the memory region MR, a plurality of ground lines GND are arranged side by side in the Y direction. Furthermore, the ground line GND is provided extending in the Z direction. Each of the "pair of write bit lines WBL and read bit lines RBL" and the "ground line GND which is connected to each other" is electrically connected to a memory cell MC at each memory layer ML.

[0020] Furthermore, the structure of the memory device 100 in the first embodiment is not limited to the structure shown in FIG2. In the memory region MR, the number of write word lines (WWL) arranged side-by-side in the Z direction and the number of read word lines (RWL) arranged side-by-side in the Z direction are each only two or more. Also, in the memory region MR, the number of write bit lines (WBL) arranged side-by-side in the Y direction and the number of read bit lines (RBL) arranged side-by-side in the Y direction are each only two or more.

[0021] <1-1-3> Circuit configuration diagram of memory cell MC: Figure 3 is a circuit diagram showing one example of the circuit configuration of the memory cell MC included in the memory device 100 of the first embodiment. Figure 3 shows one memory cell MC, a pair of write word lines WWL and read word lines RWL, a pair of write bit lines WBL and read bit lines RBL, and a ground line GND. As shown in Figure 3, the memory cell MC has a 3TOC (3 transistors, 0 capacitors) configuration. Specifically, the memory cell MC, for example, includes a write transistor WT, read transistors RT1 and RT2, and a storage node SN.

[0022] The write transistor WT is, for example, a field-effect type NMOS transistor. The gate electrode of the write transistor WT is connected to the write word line WWL. One electrode of the write transistor WT is connected to the write bit line WBL. The other electrode of the write transistor WT is connected to the storage node SN. Each of the electrodes of the write transistor WT functions as a source electrode or a drain electrode in response to the voltage supplied (applied) to the write transistor WT.

[0023] The readout transistor RT1 is, for example, a field-effect type NMOS transistor. The gate electrode of the readout transistor RT1 corresponds to the storage node SN. One electrode of the readout transistor RT1 is connected to the ground line GND. The other electrode of the readout transistor RT1 is connected to one electrode of the readout transistor RT2. Each of the electrodes of the readout transistor RT1 and the other electrode functions as a source electrode or a drain electrode in response to the voltage supplied (applied) to the readout transistor RT1.

[0024] The readout transistor RT2 is, for example, a field-effect type NMOS transistor. The gate electrode of the readout transistor RT2 is connected to the read word line RWL. The other electrode of the readout transistor RT2 is connected to the read bit line RBL. Each of the electrodes of the readout transistor RT2 functions as a source electrode or a drain electrode in response to the voltage supplied (applied) to the readout transistor RT2.

[0025] The storage node SN, for example, has a parasitic capacitance (<1 fF). The memory cell MC is capable of storing data in response to the potential of the parasitic capacitance of the storage node SN, that is, in response to the amount of charge stored in the storage node SN. In this way, data is written into the parasitic capacitance of the storage node SN. The leakage current from the storage node SN is regulated by the leakage current of the writing transistor WT. Therefore, during the read operation, the memory device 100 can read the data of the memory cell MC non-destructively by reading the current of the read transistor RT1 corresponding to the potential of the storage node SN.

[0026] In the memory device 100 of the first embodiment, a shielding electrode SH is provided near the memory cell MC. The shielding electrode SH is electrically connected to the ground wire GND. The shielding electrode SH is arranged opposite to the storage node SN and suppresses interference between two adjacent memory cells MC in the Z direction. In FIG3, the parasitic capacitance between the storage node SN and the shielding electrode SH is shown as the parasitic capacitance SC. The detailed arrangement between the two adjacent memory cells MC and the shielding electrode SH in the Z direction will be described later.

[0027] During the write operation, the control circuit 160 applies, for example, a specific voltage VON1 that is higher than the power supply voltage VDD and exceeds the threshold voltage of the write transistor WT for the write character line WWL that is the target of the write operation among the plurality of write character lines WWL, and applies a ground voltage VSS or a voltage VOFF1 that is lower than VSS for the other write character lines WWL. Thus, the write transistor WT, to which the specific voltage VON1 is applied, can be turned ON. Furthermore, the control circuit 160 applies either the power supply voltage VDD or the ground voltage VSS to the write character line WBL that is the target of the write operation among the plurality of write character lines WBL, depending on the data to be written. Additionally, during the write operation, all write character lines WBL within the memory cell array 110 can be the target of the write operation, or only a portion of the write character lines WBL can be the target of the write operation. The control circuit 160 can also set the write bit line WBL, which will not be the object of the write operation, to a floating state.

[0028] During the readout operation, the control circuit 160, for example, applies a power supply voltage VDD or a specific voltage VON2 that is higher than VDD and exceeds the threshold voltage of the readout transistor RT2 to the readout character line RWL that is the target of the readout operation among the plurality of readout character lines RWL, and applies a ground voltage VSS or a voltage VOFF2 that is lower than VSS to the other readout character lines RWL. Thus, the readout transistor RT2, to which the power supply voltage VDD is applied, can be in the ON state. Furthermore, the control circuit 160 sets the readout character line RBL that is the target of the readout operation to a floating state, for example, after applying VDD. Alternatively, the control circuit 160 can fix the ground wire GND to VDD and set the readout character line RBL that is the target of the readout operation to a floating state, for example, after applying VSS. Therefore, when the storage node SN of the memory cell MC, which is the target of the read operation, is charged by the power supply voltage VDD, the read transistor RT1 is in the ON state. In this case, current flows from the read bit line RBL to the ground line GND via the read transistors RT1 and RT2, or the read bit line RBL is discharged. On the other hand, when the storage node SN of the memory cell MC, which is the target of the read operation, is discharged by the ground voltage VSS, the read transistor RT1 is in the OFF state. In this case, no current flows from the read transistors RT1 and RT2 to the read bit line RBL, and the read bit line RBL is not discharged. Furthermore, during the read operation, all the read bit lines RBL within the memory cell array 110 can be used as the target of the read operation, or only a portion of the read bit lines RBL can be used as the target of the read operation. The control circuit 160 can also apply, for example, a power supply voltage VDD or a ground voltage VSS to the read bit line RBL that is not the object of the read operation.

[0029] <1-1-4> The structures of the memory cell array 110 are shown in Figures 4 to 6, which are cross-sectional views illustrating one example of the structure of the memory cell array 110 provided in the memory device 100 of the first embodiment. Figure 4 is an XZ cross-section corresponding to the memory cell array 110 disposed at the memory region MR in the first embodiment, and the region containing two adjacent memory cells MC in the Z direction is shown. Figure 5 is a cross-section corresponding to line VV in Figure 4. Figure 6 is a cross-section corresponding to line VI-VI in Figure 4.

[0030] As shown in Figure 4, in the memory region MR, a separation layer SL is provided between two adjacent memory cells MC in the Z direction. That is, in the memory region MR, the memory layer ML and the separation layer SL are alternately laminated in the Z direction. The separation layer SL is configured to isolate two adjacent memory cells MC in the Z direction. Two adjacent memory cells MC in the Z direction are isolated and insulated by the separation layer SL. Furthermore, the memory cell array 110, in the memory region MR, includes, for example, an insulating layer 10, conductive members 20, 21 and 22, semiconductor layers 30 and 31, insulating layers 40 and 41, conductive layers 50 and 51, conductive layer 60, insulating layer 61, and conductive layers 70-73.

[0031] An insulating layer 10 is disposed at each of a plurality of isolation layers SL arranged side by side in the Z direction. That is, at the memory region MR, a plurality of insulating layers 10 are arranged side by side in the Z direction. The insulating layer 10, for example, is an insulator containing silicon oxide (SiO2) or the like.

[0032] Each of the conductive members 20, 21, and 22 is a cylindrical through-hole wiring that extends in the Z direction and passes through the memory layer ML and the isolation layer SL, which are alternately laminated. The conductive members 20, 21, and 22 are arranged side by side in the X direction. The conductive member 20 functions as the write bit line WBL. The conductive member 21 functions as the ground line GND. The conductive member 22 functions as the read bit line RBL. Each of the conductive members 20, 21, and 22, for example, has, in planar view, a metal disposed at the center, a barrier conductive film disposed on the side of the metal pillar, and a conductive oxide film disposed on the side of the barrier conductive film. For example, in each of the conductive components 20, 21 and 22, the metal system at the center includes tungsten (W) or the like, the barrier conductive film system includes titanium nitride (TiN) or the like, and the conductive oxide film system includes conductive oxides.

[0033] In each of the conductive members 20, 21, and 22, the metal at the center extends in the Z direction and is configured as a columnar shape. In each of the conductive members 20, 21, and 22, the barrier conductive film extends in the Z direction and is configured as a slightly cylindrical shape. In each of the conductive members 20, 21, and 22, the conductive oxide extends along the outer peripheral surface (side surface) in the Z direction and is configured as a slightly cylindrical shape. Alternatively, each of the conductive members 20, 21, and 22 may contain ruthenium (Ru), iridium (Ir), or other metals instead of a conductive oxide film. Furthermore, each of the conductive members 20, 21, and 22 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir), or other metals.

[0034] The semiconductor layer 30 has a cylindrical first portion extending in the Z direction and disposed on the side of the conductive member 20, and a second portion extending in the X direction at the memory layer ML. The semiconductor layer 30 may, for example, be an oxide semiconductor containing at least one of gallium (Ga) and aluminum (Al), and indium (In), zinc (Zn), and oxygen (O). Alternatively, the semiconductor layer 30 may also be other oxide semiconductors.

[0035] The insulating layer 40 has a cylindrical first portion extending in the Z direction and disposed on the side of the first portion of the semiconductor layer 30, and a second portion disposed on the top, bottom, both sides in the Y direction, and one side (conductor layer 70 side) of the second portion of the semiconductor layer 30 in the memory layer ML. The insulating layer 40 may, for example, contain an insulator such as silicon oxide (SiO2).

[0036] The conductive layer 50 is disposed at each of the memory layers ML and surrounds the conductive member 20 when viewed in plan view. Specifically, the conductive layer 50 of each memory layer ML has a disk-shaped structure that surrounds a portion of the semiconductor layer 30 and the insulating layer 40 and is penetrated by the conductive member 20. More specifically, the conductive layer 50 is disposed at each memory layer ML on the upper, lower, Y-direction sides, and one side (conductive layer 70 side) of the second portion of the insulating layer 40. The conductive layer 50 faces the upper, lower, Y-direction sides, and one side (conductive layer 70 side) of the second portion of the semiconductor layer 30, separated by the insulating layer 40. The conductive layer 50 may be, for example, a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO).

[0037] At each memory layer ML, the semiconductor layer 30, insulating layer 40, and conductive layer 50 disposed around the conductive member 20 constitute a disk-shaped transistor with a GAA (Gate-All-Around) structure. The semiconductor layer 30, insulating layer 40, and conductive layer 50 disposed around the conductive member 20 function as a write transistor WT. Specifically, the portion of the semiconductor layer 30 that faces the conductive layer 50 across the insulating layer 40 functions as a channel region for writing the transistor WT. The portion of the insulating layer 40 that is sandwiched between the semiconductor layer 30 and the conductive layer 50 functions as a gate insulating film for the write transistor WT. The conductive layer 50 functions as the gate electrode for the write transistor WT.

[0038] Semiconductor layer 31 has a cylindrical first portion extending in the Z direction and disposed on the side of conductive member 21, a second portion extending in the X direction at memory layer ML, and a cylindrical third portion extending in the Z direction and disposed on the side of conductive member 22. Semiconductor layer 30 may, for example, be an oxide semiconductor containing at least one element selected from gallium (Ga) and aluminum (Al), and indium (In), zinc (Zn), and oxygen (O). Alternatively, semiconductor layer 31 may also be other oxide semiconductors.

[0039] The insulating layer 41 has a cylindrical first portion extending in the Z direction and disposed on the side of the third portion of the semiconductor layer 31, and a second portion disposed on the top, bottom, two sides in the Y direction, and two sides in the X direction of the second portion of the semiconductor layer 31 at the memory layer ML. The insulating layer 41 may be, for example, an insulator containing silicon oxide (SiO2) or the like.

[0040] Conductor layer 51 is disposed at each of the memory layers ML and surrounds the conductive member 21 when viewed in a planar view. Conductor layer 52 is disposed at each of the memory layers ML and surrounds the conductive member 22 when viewed in a planar view. At each memory layer ML, conductor layers 51 and 52 are separated in the X direction.

[0041] The conductive layer 51 of each memory layer ML has a disk-shaped structure that surrounds a portion of the semiconductor layer 31 and the insulating layer 41 and is penetrated by the conductive member 21. Specifically, the conductive layer 51 is disposed in the second portion of the insulating layer 41 at the "top, bottom, both sides in the Y direction, and one side (conductor layer 70 side) near the conductive member 21". The conductive layer 51 is separated from the insulating layer 41 and faces the "top, bottom, both sides in the Y direction, and one side (conductor layer 70 side) near the conductive member 21" in the second portion of the semiconductor layer 31. The side of the conductive layer 51 in the X direction is connected to the semiconductor layer 30. Therefore, the plurality of conductive layers 51 arranged side by side in the Z direction are connected to the conductive member 20 through the semiconductor layer 30. The conductive layer 51 may be, for example, a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO). Alternatively, the conductive layer 51 may also contain ruthenium (Ru), iridium (Ir), or other metals.

[0042] The conductive layer 52 of each memory layer ML has a disk-shaped structure that surrounds another part of the semiconductor layer 31 and the insulating layer 41 and is penetrated by the conductive member 22. Specifically, the conductive layer 52 is disposed in the second part of the insulating layer 41 at the "top, bottom, two sides in the Y direction, and the other side (conductor layer 72 side) near the conductive member 22". The conductive layer 52 is separated from the insulating layer 41 and faces the "top, bottom, two sides in the Y direction, and the other side (conductor layer 72 side) near the conductive member 22" in the second part of the semiconductor layer 31. The conductive layer 52 is, for example, a conductive material including titanium nitride (TiN) or a conductive oxide including indium tin oxide (ITO).

[0043] At each memory layer ML, the semiconductor layer 31, insulating layer 41, and conductive layer 51 disposed around the conductive member 21 constitute a disk-shaped transistor with a GAA structure. The semiconductor layer 31, insulating layer 41, and conductive layer 51 disposed around the conductive member 21 function as a readout transistor RT1. Specifically, the portion of the semiconductor layer 31 that faces the conductive layer 51 across the insulating layer 41 functions as a channel region of the readout transistor RT1. The portion of the insulating layer 41 that is sandwiched between the semiconductor layer 31 and the conductive layer 51 functions as a gate insulating film of the readout transistor RT1. The conductive layer 51 functions as the gate electrode of the readout transistor RT1. Furthermore, the conductive layer 51 also functions as a storage node SN.

[0044] At each memory layer ML, the semiconductor layer 31, insulating layer 41, and conductive layer 52 disposed around the conductive member 22 constitute a disk-shaped transistor with a GAA structure. The semiconductor layer 31, insulating layer 41, and conductive layer 52 disposed around the conductive member 22 function as a readout transistor RT2. Specifically, the portion of the semiconductor layer 31 that faces the conductive layer 52 across the insulating layer 41 functions as a channel region of the readout transistor RT2. The portion of the insulating layer 41 that is sandwiched between the semiconductor layer 31 and the conductive layer 52 functions as a gate insulating film of the readout transistor RT2. The conductive layer 52 functions as the gate electrode of the readout transistor RT2. In this way, the readout transistors RT1 and RT2 can also be configured with the semiconductor layer 31 and the insulating layer 41 sharing a common ground.

[0045] At each memory layer ML, the configurations corresponding to the write transistor WT, the read transistor RT1, and the read transistor RT2 are arranged side by side in the X direction. Furthermore, at each memory layer ML, the group of write transistors WT and read transistors RT1 and RT2 arranged side by side in the X direction constitutes a memory cell MC.

[0046] The conductive layer 60 is disposed at each of the isolation layers SL and surrounds the conductive member 21 when viewed in plan view. In other words, the conductive layer 60 of each isolation layer SL has a disk-shaped structure through which the conductive member 21 passes. Specifically, the conductive layer 60 is disposed extending in the X direction and is in contact with the side of the semiconductor layer 31. The conductive layer 60 of each isolation layer SL is electrically connected to the conductive member 21 through the semiconductor layer 31. When viewed in plan view, the conductive layer 60 is disposed in a manner that overlaps with the conductive layer 51 (storage node SN). Ideally, the conductive layer 60 should completely overlap with the conductive layer 51 when viewed in plan view. The conductive layer 60 may be, for example, a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO).

[0047] An insulating layer 61 is disposed at each of the isolation layers SL. The insulating layer 61 of each isolation layer SL is disposed in such a way that it covers the portion of the conductive layer 60 except for the portion through which the conductive member 21 and the semiconductor layer 31 are penetrated. Specifically, at each isolation layer SL, the insulating layer 61 is disposed on the top, bottom, two sides in the Y direction, and two sides in the X direction of the conductive layer 60. At each isolation layer SL, the insulating layer 61 is in contact with the side of the first portion of the semiconductor layer 31. The conductive layer 60 is isolated and insulated from each of the "semiconductor layer 30", the "second portion of the semiconductor layer 31 of the two adjacent memory layers ML", the "third portion of the semiconductor layer 31", and the "conductive layers 50 and 51 of the two adjacent memory layers ML" through the insulating layer 61. Insulator layer 61 has a composition different from that of insulator layers 40 and 41. Insulator layer 61 may, for example, contain one of silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO2), and aluminum oxide (Al2O3).

[0048] Thus, the conductive layers 60 and 51, which are separated from each other in the Z direction by the insulating layer 61, are alternately arranged in the Z direction. In other words, at two adjacent memory cells MC in the Z direction, two adjacent conductive layers 51 (storage nodes SN) in the Z direction are adjacent to each other by the conductive layer 60. Furthermore, the conductive layer 60 is electrically connected to the conductive member 21. In this way, the conductive layer 60 can function as a shielding electrode SH. When viewed in a planar manner, it is ideal for the shielding electrode SH to be larger than the storage node SN (conductive layer 51) and to overlap with the entire storage node SN.

[0049] A conductive layer 70 is disposed at each of the memory layers ML. At each memory layer ML, the conductive layer 70 is disposed on one side in the X direction. A conductive layer 71 is disposed, for example, on the top, bottom, two sides in the Y direction, and the other side in the X direction of the conductive layer 70. At each memory layer ML, the other side in the X direction of the conductive layer 71 is connected to the conductive layer 50. Thus, the conductive layer 70 is electrically connected to the conductive layer 50 (the gate electrode of the write transistor WT) via the conductive layer 71. The group of conductive layers 70 and 71 functions as the write word line WWL. The conductive layer 70 is, for example, a conductor such as tungsten (W). The conductive layer 71 is, for example, a barrier conductive film such as titanium nitride (TiN).

[0050] Conductor layer 72 is disposed at each of the memory layers ML. At each memory layer ML, conductor layer 72 is disposed on the opposite side in the X direction. Conductor layer 73 is disposed, for example, on the top, bottom, both sides in the Y direction, and one side in the X direction of conductor layer 72. At each memory layer ML, one side in the X direction of conductor layer 73 is connected to conductor layer 52. Thus, conductor layer 72 is electrically connected to conductor layer 52 (gate electrode of read transistor RT2) via conductor layer 73. The combination of conductor layers 72 and 73 functions as read word line RWL. Conductor layer 72 is, for example, a conductor such as tungsten (W). Conductor layer 73 is, for example, a barrier conductive film such as titanium nitride (TiN).

[0051] As shown in FIG. 5, the memory cell array 110 includes a plurality of insulating members 11 at the memory layer ML. Each insulating member 11 is provided extending along the memory cell MC in the X direction. The plurality of insulating members 11 are arranged side by side in the Y direction. Although not shown in the figure, each insulating member 11 further extends in the Z direction and is provided to penetrate the memory layer ML and the isolation layer SL, which are alternately stacked in the Z direction. In this way, each insulating member 11 electrically disconnects the plurality of memory cells MC (not shown) arranged side by side in the Y direction. In this specification, the region extending in the X direction and including the memory cell MC is called the "memory area MA". The region extending in the X direction and including the insulating member 11 is called the "trench area TA". That is, the memory region MA and the trench region TA are arranged side by side in the Y direction.

[0052] In the XY cross-section, the conductor layers 70 and 71 corresponding to the write word line WWL have portions extending in the Y direction that cover "memory regions MA and trench regions TA arranged alternately in the Y direction". In the XY cross-section, the conductor layers 72 and 73 corresponding to the read word line RWL have portions extending in the Y direction that cover "memory regions MA and trench regions TA arranged alternately in the Y direction". One side of each insulating member 11 (the conductor layer 70 side) is connected to the write word line WWL (e.g., conductor layer 71). The other side of each insulating member 11 (the conductor layer 72 side) is connected to the read word line RWL (e.g., conductor layer 73).

[0053] In the XY cross-section, one side portion of the semiconductor layer 30 in the X direction is formed, for example, in a straight line along the conductor layer 70. In the XY cross-section, the other side portion of the semiconductor layer 30 in the X direction is formed in an arc shape along a circle centered on the center position of the conductive member 21 (via wiring). In the XY cross-section, the portion of the insulating layer 40 disposed near the boundary of the write transistor WT and the read transistor RT1 is connected to two adjacent insulating members 11 in the Y direction. In the XY cross-section, the conductor layer 50 is connected to two adjacent insulating members 11 in the Y direction.

[0054] In the XY cross-section, one side of the semiconductor layer 31 in the X direction is formed as an arc along a circle centered on the center of the conductive member 21 (via wiring). In the XY cross-section, the other side of the semiconductor layer 31 in the X direction is, for example, formed as a straight line along the conductive layer 72. In the XY cross-section, the portion of the insulating layer 41 disposed near the boundary of the readout transistors RT1 and RT2 is connected to two adjacent insulating members 11 in the Y direction. In the XY cross-section, the side portions of the conductive layer 51 in the Y direction are connected to two adjacent insulating members 11 in the Y direction. Furthermore, in the XY cross-section, one side of the conductive layer 51 in the X direction is formed as an arc along a circle centered on the center of the conductive member 21 (via wiring). In the XY cross-section, the side portions of the conductive layer 52 in the Y direction are connected to two adjacent insulating members 11 in the Y direction. Furthermore, in the XY cross-section, the other side portion of the conductive layer 52 in the X direction is formed in a straight line along the conductive layer 72.

[0055] Although the illustration is omitted, in the XY cross-section, the side portion of the conductor layer 50 in the X direction is formed as an arc along a circle centered on the center position of the conductive member 21 (through-hole wiring). Although the illustration is omitted, in the XY cross-section, the side portions of both sides of the conductor layer 51 in the X direction are formed as arcs along a circle centered on the center position of the conductive member 21 (through-hole wiring). Although the illustration is omitted, in the XY cross-section, the side portion of one side of the conductor layer 52 in the X direction is formed as an arc along a circle centered on the center position of the conductive member 21 (through-hole wiring).

[0056] As shown in FIG. 6, the memory cell array 110 includes a plurality of insulating members 11 at the isolation layer SL, similar to the memory layer ML. The insulating layer 10 is disposed at the isolation layer SL, overlapping with the write word line WWL, the read word line RWL, and the memory cell MC in the Z direction. Furthermore, the insulating layer 10 has a portion through which the conductive member 20, the semiconductor layer 30, and the insulating layer 40 are connected, and a portion through which the conductive member 22, the semiconductor layer 31, and the insulating layer 41 are connected. Moreover, the insulating layer 10 is divided into one side and the other side in the X direction, separated by the group of conductive layers 60 and insulating layers 61.

[0057] In the XY cross-section, the side portions of the conductive layer 60 in the Y direction are formed in a straight line along two adjacent insulating members 11 in the Y direction. Furthermore, in the XY cross-section, the "side portion of the conductive layer 60 in the X direction on one side" and the "side portion of the conductive layer 60 in the X direction on the other side" are each formed as an arc along a circle centered on the center position of the conductive member 21 (through-hole wiring). In the XY cross-section, the insulating layer 61 is provided to surround the outer periphery of the conductive layer 60. Specifically, in the XY cross-section, the insulating layer 61 has the following components: "the portion sandwiched between the insulating member 11 on one side of the Y direction and the conductive layer 60," "the portion sandwiched between the insulating member 11 on the other side of the Y direction and the conductive layer 60," and "the portion sandwiched between the insulating layer 10 and the conductive layer 60." The width in the Y direction between the two ends of the insulating layer 61 is approximately equal to the width in the Y direction of the memory region MA. The width in the X direction between the two ends of the insulating layer 61 is wider than the width in the Y direction of the memory region MA.

[0058] Furthermore, in this specification, "conductive oxide" is, for example, defined as containing indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other oxygen-containing conductive materials. At the memory cell array 110, the gate electrode of the write transistor WT and the write word line WWL can also be connected via a conductive oxide. Similarly, the gate electrode of the read transistor RT2 and the read word line RWL can also be connected via a conductive oxide.

[0059] <1-2> Manufacturing Method Next, as a manufacturing method for the memory device 100 of the first embodiment, the process of forming the memory cell array 110 will be described using Figures 7 to 24. Figures 7 to 24 are cross-sectional views showing one example of the structure of the memory device 100 of the first embodiment during the manufacturing process. Figures 7 to 24 show an area that is the same as one of the memory region MR shown in Figure 4, the memory layer ML shown in Figure 5, and the isolation layer SL shown in Figure 6. In addition, in this specification, the term "processing performed through a specific hole" corresponds to "processing performed while other holes are covered by a mask or a sacrificial member, etc." That is, when processing is performed through a specific hole, processing of the structure that is related to the other holes is set to not be performed or to be suppressed.

[0060] First, as shown in FIG. 7, the insulating layer 10 and the sacrificial member 12 are alternately laminated. In this project, the layer in which the insulating layer 10 is disposed corresponds to the isolation layer SL, and the layer in which the sacrificial member 12 is disposed corresponds to the memory layer ML. The insulating layer 10 is, for example, silicon oxide (SiO2). The sacrificial member 12 is, for example, silicon nitride (SiN).

[0061] Next, as shown in FIG8, insulating members 11, which are separated by the laminated insulating layer 10 and sacrificial member 12, are formed in the trench region TA. Specifically, firstly, the insulating layer 10 and sacrificial member 12, which are disposed in the region corresponding to the insulating member 11, are removed by anisotropic etching such as RIE (Reactive Ion Etching). Then, in the trench portion formed by the etching process, the insulator is filled by CVD (Chemical Vapor Deposition) or the like. In this way, insulating members 11 are formed in each trench region TA. The insulating member 11 is, for example, silicon oxide (SiO2).

[0062] Next, as shown in FIG9, (1) at least two slit SLTs are formed, (2) a recess is formed by selectively removing a portion of the sacrificial member 12 at the memory region MA, and (3) the sacrificial member 80 is filled in the formed recess. In this process, the two slit SLTs are formed, for example, by removing the alternatingly laminated insulating layer 10 and sacrificial member 12 at each of the regions corresponding to the write character line WWL and the read character line RWL, respectively, by anisotropic etching such as RIE. In this process, the recess is formed by separating the sacrificial member 12 of each memory layer ML at each of the multiple memory regions MA arranged side by side in the Y direction by wet etching such as wet etching. Figure 10 is a cross-section corresponding to line XX in Figure 9. As shown in Figure 10, the sacrificial members 80, which are provided on both sides in the X direction, are formed by burying the recesses within each memory layer ML. The sacrificial members 80 are, for example, amorphous silicon (aSi).

[0063] Next, as shown in FIG11, a hole HGND is formed at the memory region MA, in the portion corresponding to the ground line GND. FIG12 corresponds to a cross-section along line XII-XII of FIG11. As shown in FIG12, the hole HGND is formed by anisotropic etching such as RIE, extending in the Z direction and penetrating the laminated insulating layer 10 and the sacrificial member 12.

[0064] Next, as shown in FIG13, (1) a portion of the sacrificial member 12 of each memory layer ML is selectively removed via the hole HGND, and a recess is formed; (2) the sacrificial member 81 is buried in the formed recess. The recess formed in this process corresponds to the location where the read transistor RT1 is formed. The sacrificial member 81 covers the side of the insulating layer 10 within the hole HGND. In addition, in this process, the sacrificial member 81 can also be formed by burying the hole HGND. The sacrificial member 81 is, for example, amorphous silicon (aSi).

[0065] Next, as shown in FIG14, at the memory region MA, (1) a hole HWBL is formed at the portion corresponding to the write bit line WBL, and (2) a hole HRBL is formed at the portion corresponding to the read bit line RBL. FIG15 corresponds to a cross-section along the XV-XV line of FIG14. As shown in FIG15, each of the holes HWBL and HRBL is formed by anisotropic etching such as RIE, in a manner that extends in the Z direction and penetrates the laminated insulating layer 10 and sacrificial member 12.

[0066] Next, as shown in FIG16, (1) sacrificial members 12 of each memory layer ML are selectively removed by means of holes HWBL and HRBL, and recesses are formed; (2) conductive films 82 and sacrificial members 83 are formed sequentially by filling the recesses to be formed. In this process, wet etching is used, for example, in the formation of the recesses. The recesses formed corresponding to holes HWBL correspond to the location where the write transistor WT is formed. In this process, the recesses formed corresponding to holes HRBL correspond to the location where the read transistor RT2 is formed. The conductive films 82 of each of holes HWBL and HRBL are in contact with each of the sacrificial members 80 and 81 at the memory layer ML. Furthermore, the conductive films 82 cover the top, bottom, two sides in the X direction, and two sides in the Y direction of the insulating layer 10 at each of holes HWBL and HRBL. In this project, the sacrificial member 83 can also be formed by filling the holes HWBL and HRBL. Both the conductive film 82 and the sacrificial member 83 are formed, for example, by CVD. The conductive film 82 is, for example, titanium nitride (TiN). The sacrificial member 83 is, for example, amorphous silicon (aSi).

[0067] Next, as shown in FIG17, (1) the sacrificial member 81, which is disposed corresponding to the hole HGND, is selectively removed, and (2) the sacrificial member 84 is formed in such a way that the recesses in contact with the hole HGND are filled at each memory layer ML. In this process, the removal of the sacrificial member 81 is performed, for example, by wet etching. The sacrificial member 84 is in contact with each of the conductive films 82 disposed in the recesses in contact with the hole HWBL and the conductive films 82 disposed in the recesses in contact with the hole HRBL at each memory layer ML. The sacrificial member 84 is, for example, silicon nitride (SiN). In this process, the sacrificial member 84 can also be formed in such a way that the hole HGND is filled.

[0068] Next, as shown in FIG18, (1) by removing a portion of the sacrificial member 84 provided at the hole HGND, the insulating layer 10 is exposed on the side of the hole HGND; (2) a portion of the insulating layer 10 of each isolation layer SL is selectively removed through the hole HGND. In this process, wet etching is used, for example, in the removal of the sacrificial member 84. In this process, the recess formed in the isolation layer SL in contact with the hole HGND corresponds to the location where the shielding electrode SH is formed.

[0069] Next, as shown in FIG19, (1) the insulating film corresponding to the insulating layer 61 and the conductive film corresponding to the conductive layer 60 are formed, and (2) the insulating film and the conductive film disposed on the side portion of the hole HGND are removed. Thus, the structure corresponding to the shielding electrode SH is formed. Furthermore, through this process, the side surfaces of the sacrificial members 84 of each memory layer ML are exposed within the hole HGND. In this process, for example, CVD is used in the formation of the insulating film and the conductive film.

[0070] Next, as shown in FIG20, the sacrificial members 84 of each memory layer ML are selectively removed via the hole HGND. Conductor layers 50, 51, and 52 are formed at each memory layer ML, an insulating layer 40 is formed, and sacrificial members 85 and 86 are formed. The structure shown in FIG20 can be formed by utilizing the holes HGND, HWBL, and HRBL and performing appropriate etching and film-forming processes. The conductor layer 51 is, for example, a conductive oxide such as indium tin oxide (ITO). The conductor layers 50 and 52 of each memory layer ML are formed by processing the conductive film 82. The sacrificial member 85 is provided such that it covers the insulating layer 40 at least within the hole HWBL. The sacrificial member 86 is disposed at each memory layer ML by filling the space enclosed by the disk-shaped conductive layer 51, the space enclosed by the disk-shaped conductive layer 52, and the space between the conductive layers 51 and 52. The sacrificial members 85 and 86 are, for example, amorphous silicon (aSi).

[0071] Next, as shown in FIG21, (1) a portion of the conductive layer 51 disposed at the memory layer ML is removed via the hole HGND; (2) the sacrificial members 86 of each memory layer ML are selectively removed; and (3) the insulating layer 41 is formed via the hole HGND and HRBL. The conductive layer 51 processed in this process corresponds to the shape of the conductive layer 51 (storage node SN) shown in FIG4. The removal of the conductive layer 51 is, for example, performed using a wet etching process. The insulating layer 41 is, for example, formed by CVD or the like.

[0072] Next, as shown in FIG. 22, the sacrificial member 87 is embedded in the space sandwiched in the Z direction by the insulating layer 41 at each memory layer ML. The sacrificial member 87 is formed, for example, by CVD or the like. In this process, the sacrificial member 87 formed at the side portions of the holes HGND and HRBL is removed by etch-back processing. The sacrificial member 87 is, for example, amorphous silicon (aSi).

[0073] Next, as shown in FIG23, the insulating layer 41 formed on the side portion of the hole HGND at each isolation layer SL is selectively removed via the hole HGND. As a result, a portion of the conductive layer 60 is exposed in the portion of the hole HGND corresponding to each isolation layer SL. The removal of the insulating layer 41 is, for example, performed using a wet etching process.

[0074] Next, as shown in FIG24, (1) sacrificial members 85 and 87 are selectively removed, (2) semiconductor layers 30 and 31 are formed, and (3) conductive members 20, 21, and 22 are respectively filled in the holes HWBL, HGND, and HRBL. After that, sacrificial member 80 is removed, and the structure corresponding to the write word line WWL and read word line RWL is formed. As a result, the structure of the memory cell array 110 shown in FIG4 to FIG6 is completed.

[0075] <1-3> Effects of the First Embodiment Based on the memory device 100 of the first embodiment, a low-cost 3D stacked memory can be provided. Hereinafter, the effects of the memory device 100 of the first embodiment will be explained in detail using comparative examples.

[0076] As a memory cell structured as a gain cell, the memory cell MC composed of 3T0C (3 transistors, 0 capacitors) is well known. Compared with the memory cell composed of 1T1C, the memory cell composed of 3T0C can be expected to have (1) improved tWT (write time), (2) lower power consumption, and (3) improved cell size scalability for multilayer stacking by eliminating the capacitor.

[0077] Figure 25 is a circuit diagram showing one example of the circuit configuration of the memory cell MCz provided in the memory device 100 of the comparative example. As shown in Figure 25, the memory cell MCz has a configuration in which the shielding electrode SH is omitted from the circuit configuration of the memory cell MC shown in Figure 3. Figure 26 is a cross-sectional view showing one example of the structure of the memory cell array 110 provided in the memory device 100 of the comparative example. As shown in Figure 26, in the memory device 100 of the comparative example, the shielding electrode SH is not disposed at the isolation layer SL. That is, two adjacent memory cells MCz in the Z direction are adjacent to each other through the insulating layer 10.

[0078] In the comparative example memory cell MCz, if the signal ("0" or "1") of the upper and lower memory cells MCz changes due to a write operation, the potential of the storage node SN will be affected by the coupling. Therefore, in the comparative example memory cell MCz, the potential of the storage node SN will interfere with the two adjacent memory cells MCz in the Z direction. When performing high-level stacking on such memory cells MCz, it is necessary to increase the stacking spacing of the memory cells MCz to suppress the interference effect. However, increasing the stacking spacing of the memory cells MCz may become an important factor leading to an increase in the size and cost of the memory cell array.

[0079] In contrast, the memory device 100 of the first embodiment has a configuration in which "a shielding electrode SH is formed at each of the two isolation layers SL adjacent to the storage node SN in the Z direction, and the shielding electrode SH is electrically connected to the ground wire GND". The shielding electrode SH is capable of suppressing the effects caused by "the change in the potential of the storage node SN due to the writing of the adjacent memory cell MC in the Z direction". That is, it is capable of suppressing interference between the two memory cells MC disposed above and below the shielding electrode SH.

[0080] As a result, the memory device 100 of the first embodiment can reduce the pitch of the memory cells MC arranged side by side in the Z direction, thereby providing a high-density and low-cost 3D stacked memory. Furthermore, since the shielding electrode SH can add capacitance (<1fF) between the storage node SN and the ground line GND, it can improve noise resistance. In addition, since the shielding electrode SH is formed in the area above and below the storage node SN, the parasitic capacitance of the write word line WWL and the read word line RWL will not increase. That is, the characteristic degradation of the memory cell MC caused by the addition of the shielding electrode SH can be suppressed.

[0081] <2> Second Embodiment In the memory device 100 of the second embodiment, when viewed in a plane, the two sides of the shielding electrode SH in the X direction are set as concave lenses (arc shapes). Hereinafter, the details of the memory device 100 of the second embodiment will be explained, mainly focusing on the differences from the first embodiment.

[0082] <2-1> Configuration First, the configuration of the memory device 100 in the second embodiment will be described using Figures 27 to 29. Figures 27 to 29 are cross-sectional views showing one example of the configuration of the memory cell array 110 provided in the memory device 100 of the second embodiment. Figure 27 is an XZ cross-section corresponding to the memory cell array 110 disposed at the memory region MR in the second embodiment, and the region containing two adjacent memory cells MC in the Z direction is shown. Figure 28 is a cross-section corresponding to the line XXVIII-XXVIII in Figure 27. Figure 29 is a cross-section corresponding to the line XXIX-XXIX in Figure 27.

[0083] The memory device 100 of the second embodiment has the same configuration as the memory device 100 of the first embodiment. On the other hand, the memory device 100 of the second embodiment differs from the memory device 100 of the first embodiment mainly in the shape of the conductive layers 50, 51, and 60 and the insulating layer 61. Hereinafter, the conductive layers 50, 51, and 60 and the insulating layer 61 of the memory device 100 of the second embodiment will be referred to as conductive layers 50a, 51a, and 60a and insulating layer 61a, respectively.

[0084] As shown in FIG. 27, at each memory layer ML, conductor layers 50a and 52a have shapes extending beyond the isolation layer SL described in the first embodiment. Specifically, the width in the Z-direction between the upper and lower ends of conductor layer 50a is wider than the width in the Z-direction of the write word lines WWL (conductor layers 70 and 71). The width in the Z-direction between the upper and lower ends of conductor layer 52a is wider than the width in the Z-direction of the read word lines RWL (conductor layers 72 and 73). Furthermore, the width in the Z-direction between the upper and lower ends of conductor layer 50a and the width in the Z-direction between the upper and lower ends of conductor layer 52a are, for example, approximately equal.

[0085] Therefore, the thickness in the Z-direction of the portion of the insulating layer 10 "enclosed by two adjacent conductive layers 50a in the Z-direction" is thinner than the thickness in the Z-direction of the portion "enclosed by two adjacent write word lines WWL in the Z-direction". Similarly, the thickness in the Z-direction of the portion of the insulating layer 10 "enclosed by two adjacent conductive layers 52a in the Z-direction" is thinner than the thickness in the Z-direction of the portion "enclosed by two adjacent read word lines RWL in the Z-direction". Furthermore, the spacing between the upper and lower ends of the conductive layer 51a in the Z-direction is narrower than both the spacing between the upper and lower ends of the conductive layer 50a in the Z-direction and the spacing between the upper and lower ends of the conductive layer 52a in the Z-direction.

[0086] Furthermore, the insulating layer 61a is provided to be closed in both the portion "enclosed by two adjacent conductive layers 50a in the Z direction" and the portion "enclosed by two adjacent conductive layers 52a in the Z direction". Therefore, when viewed in plan view, the conductive layer 60a is arranged such that the insulating layer 61a is closed off from each of the conductive layers 50a and 52a. As a result, the conductive layer 60a is not included in either the portion "enclosed by two adjacent conductive layers 50a in the Z direction" or the portion "enclosed by two adjacent conductive layers 52a in the Z direction".

[0087] As shown in FIG. 28, in the XY cross-section, the side portion of the semiconductor layer 30 in the second embodiment on the other side in the X direction (conductor layer 72) is formed as an arc along a circle centered on the center position of the conductive member 20 (via wiring). Although not shown in the figure, in the XY cross-section, the side portion of the conductor layer 50a on the other side in the X direction is formed as an arc along a circle centered on the center position of the conductive member 20 (via wiring). In the XY cross-section, the side portion of one side (conductor layer 70 side) of the semiconductor layer 31 in the second embodiment in the X direction is formed as an arc along a circle centered on the center position of the conductive member 20 (via wiring). Although not shown in the diagram, in the XY cross-section, one side of the conductive layer 51a in the X direction is formed as an arc along a circle centered on the center of the conductive member 20 (via wiring). Although not shown in the diagram, the other end of the conductive layer 50a in the X direction and the end of one side of the conductive layer 51a in the X direction are positioned at a certain distance from each other. Although not shown in the diagram, in the XY cross-section, the other side of the conductive layer 51a in the X direction is formed as an arc along a circle centered on the center of the conductive member 22 (via wiring). Although not shown in the diagram, in the XY cross-section, one side of the conductive layer 52a in the X direction is formed as an arc along a circle centered on the center of the conductive member 22 (via wiring).

[0088] As shown in Figure 29, in the XY cross-section, one side of the conductive layer 60a in the X direction is formed as an arc along a circle centered on the center of the conductive member 20 (via wiring). In the XY cross-section, the other side of the conductive layer 60a in the X direction is formed as an arc along a circle centered on the center of the conductive member 22 (via wiring). In the XY cross-section, both the "one side of the insulating layer 61a in the X direction" and the "other side of the insulating layer 61a in the X direction" are formed as arcs along a circle centered on the center of the conductive member 21 (via wiring). Furthermore, in the XY cross-section, the shapes of both the "one side of the insulating layer 61a in the X direction" and the "other side of the insulating layer 61a in the X direction" are convex lens shapes. The width in the Y direction between the two ends of the insulating layer 61a is approximately equal to the width in the Y direction of the memory region MA. The width in the X direction between the two ends of the insulating layer 61a is wider than the width in the Y direction of the memory region MA. Furthermore, the width in the X direction of the portion of the insulating layer 61a "enclosed by the conductive layer 60a and the insulating layer 10" is narrower than the width in the X direction of the portion "enclosed by the conductive layer 60a and the insulating member 11".

[0089] The other components of the memory device 100 in the second embodiment are the same as those of the memory device 100 in the first embodiment.

[0090] <2-2> Manufacturing Method Next, as a manufacturing method for the memory device 100 of the second embodiment, the process of forming the memory cell array 110 will be described using Figures 30 to 41. Figures 30 to 41 are cross-sectional views showing one example of the structure of the memory device of the second embodiment during the manufacturing process. Figures 30 to 41 show a region that is the same as one of the memory region MR shown in Figure 27, the memory layer ML shown in Figure 28, and the isolation layer SL shown in Figure 29.

[0091] In the manufacturing method of the memory device 100 in the second embodiment, firstly, the processing system described in Figures 7 to 10 in the first embodiment is performed, and the structure system shown in Figure 10 is formed.

[0092] Next, as shown in FIG30, at the memory region MA, a hole HWBL is formed at the portion corresponding to the write bit line WBL, a hole HGND is formed at the portion corresponding to the ground line GND, and a hole HRBL is formed at the portion corresponding to the read bit line RBL. FIG31 corresponds to a cross-section along line XXXI-XXXI of FIG30. As shown in FIG31, each of the holes HWBL, HGND, and HRBL is formed by anisotropic etching such as RIE, extending in the Z direction and penetrating the laminated insulating layer 10 and the sacrificial member 12.

[0093] Next, as shown in FIG. 32, the sacrificial member 81a is embedded at the hole HGND. In this process, for example, CVD is used in the formation of the sacrificial member 81a. Furthermore, in this process, the sacrificial member 81a is formed only in a manner that at least covers the insulating layer 10 on the side of the hole HGND and the sacrificial member 12. The sacrificial member 81a is, for example, amorphous silicon (aSi).

[0094] Next, as shown in FIG33, the sacrificial members 12 of each memory layer ML are selectively removed via holes HWBL and HRBL, and recesses are formed. In this process, wet etching is used, for example, in forming the recesses. The recess formed corresponding to the hole HWBL corresponds to the location where the write transistor WT is formed. In this process, the recess formed corresponding to the hole HRBL corresponds to the location where the read transistor RT2 is formed. At the recesses of holes HWBL and HRBL, a portion of the sacrificial member 80 is exposed. FIG34 corresponds to a cross-section along line XXXIV-XXXIV of FIG33. As shown in Figure 34, through this process, the sacrificial member 12 of each memory region MA is machined in the XY section as an arc along a circle centered on the center position of the hole HWBL on one side of the X direction (hole HWBL side), and as an arc along a circle centered on the center position of the hole HRBL on the other side of the X direction (hole HRBL side).

[0095] Next, as shown in FIG. 35, isotropic etching is performed via holes HWBL and HRBL, and the insulating layer 10 of each isolation layer SL is recessed. Thereby, at each memory layer ML, the recesses of holes HWBL and HRBL are enlarged in the Z direction. In this process, the recesses enlarged in the Z direction at holes HWBL and HRBL are processed in a manner that they do not connect between two adjacent memory layers ML. In this process, for example, a wet etching process is used. FIG. 36 corresponds to a cross-section along line XXXVI-XXXVI of FIG. 35. As shown in FIG. 36, in this process, by making the insulating layer 10 recessed, the diameters of holes HWBL and HRBL can be enlarged.

[0096] Next, as shown in FIG. 37, the conductive film 82a and the sacrificial member 83a are formed sequentially by filling the recesses of holes HWBL and HRBL. The conductive film 82a of each hole HWBL and HRBL is located at the memory layer ML and is in contact with the sacrificial members 80 and 12. Furthermore, the conductive film 82a covers the top, bottom, two sides in the X direction, and two sides in the Y direction of the insulating layer 10 at each hole HWBL and HRBL. In this process, the sacrificial member 83a can also be formed by filling the holes HWBL and HRBL. The conductive film 82a and the sacrificial member 83a are formed, for example, by CVD or the like. The conductive film 82a is, for example, titanium nitride (TiN). The sacrificial member 83a is, for example, amorphous silicon (aSi).

[0097] Next, as shown in FIG. 38, a portion of the insulating layer 10 of each isolation layer SL is selectively removed via the hole HGND. In this process, for example, a wet etching process is used. FIG. 39 corresponds to a cross-section along line XXXIX-XXXIX of FIG. 38. As shown in FIG. 39, by means of this process, the portion of the insulating layer 10 of each isolation layer SL located on the hole HGND side is processed in the XY cross-section into an arc shape along a circle centered on the center position of the hole HGND.

[0098] Next, as shown in FIG40, (1) the insulating film corresponding to the insulating layer 61a and the conductive film corresponding to the conductive layer 60a are formed, and (2) the insulating film and the conductive film disposed at the side portion of the hole HGND are removed. In this process, the insulating film corresponding to the insulating layer 61a is formed by burying the portion sandwiched in the Z direction by the conductive film 82a. Thereby, the structure corresponding to the shielding electrode SH is formed. By this process, the side of the sacrificial member 12 of each memory layer ML is exposed in the hole HGND. In this process, for example, CVD is used in the formation of the insulating film and the conductive film. FIG41 is a cross-section corresponding to the XLI-XLI line in FIG40. As shown in Figure 41, the portion of the insulating layer 61a that is sandwiched in the Z direction by the conductive film 82a is formed into a convex lens shape in the XY cross section. Therefore, the conductive layer 60a is formed into a shape that tapers along the insulating layer 61a at the insulating layer SL.

[0099] Subsequently, the same processing system as that described in Figures 20-24 in the first embodiment is performed, and the configuration system corresponding to the write bit line WBL, ground line GND, read bit line RBL, write transistor WT, read transistor RT1, and RT2 is formed. Then, the sacrificial member 80 is removed, and the configuration system corresponding to the write word line WWL and read word line RWL is formed. As a result, the configuration system of the memory cell array 110 shown in Figures 27-29 is completed.

[0100] <2-3> Effects of the Second Embodiment In the memory device 100 of the second embodiment, the insulating layer 10 of the isolation layer SL is recessed by etching through holes HWBL and HRBL. Then, by utilizing the difference in hole thickness, the shielding electrode SH is formed through self-alignment. Specifically, the conductive layer 51a corresponding to the storage node SN and the conductive layer 60a corresponding to the shielding electrode SH are formed by self-alignment.

[0101] By forming the conductive layer 51a and conductive layer 60a using self-alignment, the shapes of the shielding electrode SH (conductive layer 60a) and the conductive layer 50a connected to the write word line WWL are matched. In other words, the manufacturing method of the memory device 100 in the second embodiment is able to form the shielding electrode SH and the write word line WWL in a manner that does not overlap with each other in the Z direction. As a result, the increase of parasitic capacitance between the shielding electrode SH and the write word line WWL can be suppressed.

[0102] Similarly, by forming the conductive layers 52a and 60a using self-alignment, the shapes of the shielding electrode SH (conductive layer 60a) and the conductive layer 52a connected to the read word line RWL are matched. That is, in the memory device 100 of the second embodiment, the shielding electrode SH and the read word line RWL can be formed in a manner that prevents them from overlapping in the Z direction. As a result, the increase in parasitic capacitance between the shielding electrode SH and the read word line RWL can be suppressed.

[0103] As explained above, the memory device 100 of the second embodiment suppresses the overlap between the shielding electrode SH and other electrodes, thereby suppressing the increase of parasitic capacitance. Furthermore, by forming the conductive layers 50a, 51a, 52a, and 60a using self-alignment, the area at the memory cell MC that does not function as a channel can be reduced. As a result, the gate electrode of the write transistor WT, the shielding electrode SH, and the storage node SN are efficiently configured, and the area of ​​the memory cell MC can be reduced. Therefore, the memory device 100 of the second embodiment can reduce the size of the memory cell array 110, thereby reducing the manufacturing cost of the memory device 100.

[0104] <3> Third Embodiment In the memory device 100 of the third embodiment, when viewed in a plane, one side of the shielding electrode SH in the X direction is configured as a concave lens (arc shape), and the other side of the shielding electrode SH in the X direction is configured as a convex lens (arc shape). Hereinafter, the details of the memory device 100 of the third embodiment will be explained, mainly focusing on the differences from the first and second embodiments.

[0105] <3-1> Configuration First, the configuration of the memory device 100 in the third embodiment will be described using Figures 42 to 44. Figures 42 to 44 are cross-sectional views showing one example of the configuration of the memory cell array 110 provided in the memory device 100 of the third embodiment. Figure 42 is an XZ cross-section corresponding to the memory cell array 110 disposed at the memory region MR in the third embodiment, and the region containing two adjacent memory cells MC in the Z direction is shown. Figure 43 is a cross-section corresponding to the line XLIII-XLIII in Figure 42. Figure 44 is a cross-section corresponding to the line XLIV-XLIV in Figure 42.

[0106] The memory device 100 of the third embodiment has the same configuration as the memory device 100 of the first embodiment. On the other hand, the memory device 100 of the third embodiment differs from the memory device 100 of the first embodiment mainly in the shape of the conductive layers 50, 51, and 60 and the insulating layer 61. Hereinafter, the conductive layers 50, 51, and 60 and the insulating layer 61 of the memory device 100 of the third embodiment will be referred to as conductive layers 50b, 51b, and 60b and insulating layer 61b, respectively.

[0107] As shown in FIG. 42, at each memory layer ML, conductor layers 50b and 52b have shapes that extend beyond the isolation layer SL described in the first embodiment. Specifically, the width in the Z direction between the upper and lower ends of conductor layer 50b is wider than the width in the Z direction of the write word lines WWL (conductor layers 70 and 71). The width in the Z direction between the upper and lower ends of conductor layer 52b is wider than the width in the Z direction of the read word lines RWL (conductor layers 72 and 73). Furthermore, the width in the Z direction between the upper and lower ends of conductor layer 50b and the width in the Z direction between the upper and lower ends of conductor layer 52b are, for example, approximately equal.

[0108] Therefore, the thickness in the Z direction of the portion of the insulating layer 10 "enclosed by two adjacent conductive layers 50b in the Z direction" is thinner than the thickness in the Z direction of the portion "enclosed by two adjacent write word lines WWL in the Z direction". Similarly, the thickness in the Z direction of the portion of the insulating layer 10 "enclosed by two adjacent conductive layers 52b in the Z direction" is thinner than the thickness in the Z direction of the portion "enclosed by two adjacent read word lines RWL in the Z direction". Furthermore, the spacing between the upper and lower ends of the conductive layer 51b in the Z direction is narrower than both the spacing between the upper and lower ends of the conductive layer 50b in the Z direction and the spacing between the upper and lower ends of the conductive layer 52b in the Z direction.

[0109] Furthermore, the insulating layer 61b is provided to be closed in both the portion "enclosed by two adjacent conductive layers 50b in the Z direction" and the portion "enclosed by two adjacent conductive layers 52b in the Z direction". Therefore, when viewed in plan view, the conductive layer 60b is arranged such that the insulating layer 61b is closed off from each of the conductive layers 50b and 52b. As a result, the conductive layer 60b is not included in either the portion "enclosed by two adjacent conductive layers 50b in the Z direction" or the portion "enclosed by two adjacent conductive layers 52b in the Z direction".

[0110] As shown in FIG. 43, in the XY cross-section, the side portion of the semiconductor layer 30 in the third embodiment on the other side in the X direction (conductor layer 72) is formed as an arc along a circle centered on the center position of the conductive member 20 (via wiring). Although not shown in the figure, in the XY cross-section, the side portion of the conductor layer 50b on the other side in the X direction is formed as an arc along a circle centered on the center position of the conductive member 20 (via wiring). In the XY cross-section, the side portion of one side of the semiconductor layer 31 in the X direction (conductor layer 70 side) in the third embodiment is formed as an arc along a circle centered on the center position of the conductive member 20 (via wiring). Although not shown in the diagram, in the XY cross-section, one side of the conductive layer 51b in the X direction is formed as an arc along a circle centered on the center of the conductive member 20 (via wiring). Although not shown in the diagram, in the XY cross-section, the other side of the conductive layer 51b in the X direction is formed as an arc along a circle centered on the center of the conductive member 21 (via wiring). Although not shown in the diagram, in the XY cross-section, one side of the conductive layer 52b in the X direction is formed as an arc along a circle centered on the center of the conductive member 21 (via wiring).

[0111] As shown in Figure 44, in the XY cross-section, one side of the conductive layer 60b in the X direction is formed as an arc along a circle centered on the center of the conductive member 20 (via wiring). In the XY cross-section, the other side of the conductive layer 60b in the X direction is formed as an arc along a circle centered on the center of the conductive member 21 (via wiring). In the XY cross-section, both the "one side of the insulating layer 61b in the X direction" and the "other side of the insulating layer 61b in the X direction" are formed as arcs along a circle centered on the center of the conductive member 21 (via wiring). Furthermore, in the XY cross-section, the shape of one side of the insulating layer 61b in the X direction is a convex lens shape. The width in the Y direction between the two ends of the insulating layer 61b is approximately equal to the width in the Y direction of the memory region MA. The width in the X direction between the two ends of the insulating layer 61b is wider than the width in the Y direction of the memory region MA. The width in the X direction of the portion of the insulating layer 61b "enclosed by the conductive layer 60b and the insulating layer 10" is narrower than the width in the X direction of the portion "enclosed by the conductive layer 60b and the insulating member 11".

[0112] The other components of the memory device 100 in the third embodiment are the same as those of the memory device 100 in the first embodiment.

[0113] <3-2> Manufacturing Method Next, as a manufacturing method for the memory device 100 of the third embodiment, the process of forming the memory cell array 110 will be described using Figures 45 to 62. Figures 45 to 62 are cross-sectional views showing one example of the structure of the memory device 100 of the third embodiment during the manufacturing process. Figures 45 to 62 show a region that is the same as one of the memory region MR shown in Figure 42, the memory layer ML shown in Figure 43, and the isolation layer SL shown in Figure 44. In the manufacturing method of the memory device 100 of the third embodiment, firstly, the process described in Figures 7 to 10 of the first embodiment is performed.

[0114] In the manufacturing method of the memory device 100 in the third embodiment, firstly, the processing system described in Figures 7 to 10 in the first embodiment is implemented, and the structural system shown in Figure 10 is formed. Then, the processing system described in Figures 30 and 31 in the second embodiment is implemented, and the structural system shown in Figures 30 and 31 is formed.

[0115] Next, as shown in FIG. 45, the sacrificial member 81b is filled at the holes HGND and HRBL. In this process, CVD is used, for example, in the formation of the sacrificial member 81b. Furthermore, in this process, the sacrificial member 81b is formed only in a manner that at least covers the insulating layer 10 and the sacrificial member 12 on the sides of the holes HGND and HRBL. The sacrificial member 81b is, for example, amorphous silicon (aSi).

[0116] Next, as shown in FIG46, a recess is formed by selectively removing the sacrificial member 12 of each memory layer ML through the hole HWBL. In this process, a wet etching process is used, for example, in forming the recess. The recess formed in the hole HWBL corresponds to the location where the write transistor WT is formed. At each recess of the hole HWBL, a portion of the sacrificial member 80 is exposed. FIG47 is a cross-sectional view along line XLVII-XLVII of FIG46. As shown in FIG47, in this process, the sacrificial member 12 of each memory region MA is processed in the XY cross-section, on one side in the X direction (hole HWBL side), into an arc shape along a circle centered on the center position of the hole HWBL.

[0117] Next, as shown in FIG. 48, isotropic etching is performed via the hole HWBL, and the insulating layer 10 of each isolation layer SL is recessed. Thereby, at each memory layer ML, the recessed portion of the hole HWBL is enlarged in the Z direction. In this process, the recessed portion enlarged in the Z direction at the hole HWBL is processed in a manner that it does not connect between two adjacent memory layers ML. In this process, for example, a wet etching process is used. FIG. 49 corresponds to a cross-section along line XLIX-XLIX of FIG. 48. As shown in FIG. 49, in this process, by making the insulating layer 10 recessed, the diameter of the hole HWBL can be enlarged.

[0118] Next, as shown in Figure 50, the sacrificial member 88 is filled at the hole HWBL. In this process, for example, CVD is used in the formation of the sacrificial member 88. Furthermore, in this process, the sacrificial member 88 is formed only in a manner that at least covers the insulating layer 10, the sacrificial member 12, and the sacrificial member 80 on the side of the hole HWBL. The material of the sacrificial member 88 is different from that of the sacrificial member 81b. The sacrificial member 88, for example, is amorphous carbon (aC).

[0119] Next, as shown in FIG. 51, (1) the sacrificial member 81b within the hole HGND is removed, and (2) a portion of the sacrificial member 12 of each memory layer ML is selectively removed through the hole HGND, thereby forming a recess. Thus, the side of the sacrificial member 88 is exposed at the portion within the hole HGND corresponding to each memory layer ML. FIG. 52 corresponds to a cross-section along line LII-LII of FIG. 50. As shown in FIG. 52, the sacrificial member 12 is almost completely removed at one side of the recess in the X direction within the hole HGND. On the other hand, at the other end of the recess in the X direction within the hole HGND, in the XY cross-section, the sacrificial member 12 is machined into an arc shape centered on the center position of the hole HGND.

[0120] Next, as shown in FIG53, (1) sacrificial member 89 is formed to fill the recessed portion of the hole HGND, and (2) the hole HGND is filled by sacrificial member 90. Both sacrificial members 89 and 90 are formed, for example, by CVD or the like. Sacrificial members 89 and 90 are made of different materials. Sacrificial member 89, for example, is amorphous silicon (aSi). Sacrificial member 90, for example, is amorphous carbon (aC).

[0121] Next, as shown in FIG54, (1) the sacrificial member 81b within the hole HRBL is removed, and (2) by selectively removing the sacrificial members 12 of each memory layer ML through the hole HRBL, a recess is formed. Thereby, the side surfaces of sacrificial members 80 and 89 are exposed at the portions within the hole HRBL corresponding to each memory layer ML. FIG55 corresponds to a cross-section along the LV-LV line of FIG54. As shown in FIG55, on one side of the recess in the X direction within the hole HRBL, in the XY cross-section, an arc-shaped sacrificial member 89 centered on the center position of the hole HGND is exposed. On the other hand, on the other side of the recess in the X direction within the hole HRBL, in the XY cross-section, a straight sacrificial member 80 is exposed.

[0122] Next, as shown in FIG. 56, isotropic etching is performed via the hole HRBL, and the insulating layer 10 of each isolation layer SL is recessed. Thereby, at each memory layer ML, the recessed portion of the hole HRBL is enlarged in the Z direction. In this process, the recessed portion enlarged in the Z direction at the hole HRBL is processed in a manner that it does not connect between two adjacent memory layers ML. In this process, for example, a wet etching process is used. FIG. 57 corresponds to a cross-section along line XVII-XVII of FIG. 56. As shown in FIG. 57, in this process, by making the insulating layer 10 recessed, the diameter of the hole HRBL can be enlarged.

[0123] Next, as shown in Figure 58, the sacrificial member 91 is filled at the hole HRBL. In this process, for example, CVD is used in the formation of the sacrificial member 91. Furthermore, in this process, the sacrificial member 91 is formed only in a manner that at least covers the insulating layer 10, sacrificial members 80 and 89 on the sides of the hole HRBL. The material of the sacrificial member 91 is different from that of the sacrificial members 80 and 89. The sacrificial member 91, for example, is amorphous carbon (aC).

[0124] Next, as shown in FIG59, (1) the sacrificial member 90 within the hole HGND is selectively removed, and (2) the sacrificial member 89 within the hole HGND is removed in a manner that leaves the sacrificial member 89 in the recess within the hole HGND. In this process, for example, a wet etching process is used. Thereby, the sacrificial member 89 formed in the recess within the hole HGND is separated between the memory layers ML. Furthermore, within the hole HGND, the side surfaces of the insulating layers 10 of each isolation layer SL are exposed.

[0125] Next, as shown in FIG. 60, a portion of the insulating layer 10 of each isolation layer SL is selectively removed via the hole HGND. In this process, for example, a wet etching process is used. By means of this process, the portion of the insulating layer 10 of each isolation layer SL located on the hole HGND side is processed in the XY section into an arc shape (not shown) along a circle centered on the center position of the hole HGND.

[0126] Next, as shown in FIG. 61, (1) the insulating film corresponding to the insulating layer 61b and the conductive film corresponding to the conductive layer 60b are formed, and (2) the insulating film and the conductive film disposed at the side portion of the hole HGND are removed. In this process, the insulating film corresponding to the insulating layer 61b is formed by burying the portion sandwiched in the Z direction by the sacrificial member 88 or 91. Thereby, the structure corresponding to the shielding electrode SH is formed. By this process, the side of the sacrificial member 89 of each memory layer ML is exposed in the hole HGND. In this process, for example, CVD is used in the formation of the insulating film and the conductive film. FIG. 62 is a cross-section corresponding to the LXII-LXII line in FIG. 61. As shown in Figure 62, the portion of the insulating layer 61b that is sandwiched in the Z direction by the sacrificial member 88 is formed into a convex lens shape in the XY cross section. Furthermore, the portion of the insulating layer 61b that is sandwiched in the Z direction by the sacrificial member 91 is formed into an arc shape in the XY cross section that is thicker than the insulating layer 61b formed in this project.

[0127] Next, although the illustration is omitted, the sacrificial member 88 is removed via the hole HWBL, and the sacrificial member 91 is removed via the hole HRBL. Then, as explained in FIG37 in the second embodiment, the conductive film 82a and the sacrificial member 83a are sequentially formed by filling the recesses of both holes HWBL and HRBL. Then, in the process explained in FIGS. 20-24 in the first embodiment, the same process as when the sacrificial member 84 is replaced with the sacrificial member 89 is performed, and the structure corresponding to the write bit line WBL, ground line GND, read bit line RBL, write transistor WT, read transistor RT1, and RT2 is formed. Then, the sacrificial member 80 is removed, and the structure corresponding to the write word line WWL and read word line RWL is formed. As a result, the structure of the memory cell array 110 shown in FIGS. 42-44 is completed.

[0128] <3-3> Effects of the Third Embodiment In the memory device 100 of the third embodiment, similar to the second embodiment, the insulating layer 10 of the isolation layer SL is recessed by etching through holes HWBL and HRBL. Then, utilizing the difference in hole thickness, the shielding electrode SH is formed by self-alignment. Specifically, the conductive layer 51b corresponding to the storage node SN and the conductive layer 60b corresponding to the shielding electrode SH are formed by self-alignment.

[0129] Thus, the memory device 100 of the third embodiment, like that of the second embodiment, suppresses the overlap between the shielding electrode SH and other electrodes, thereby suppressing the increase of parasitic capacitance. Furthermore, by forming the conductive layers 50b, 51b, 52b, and 60b using self-alignment, the area at the memory cell MC that does not function as a channel can be reduced. As a result, the gate electrode of the write transistor WT, the shielding electrode SH, and the storage node SN are efficiently configured, thereby reducing the area of ​​the memory cell MC. Therefore, the memory device 100 of the third embodiment can reduce the size of the memory cell array 110, thereby reducing the manufacturing cost of the memory device 100.

[0130] <3-4> Modification of the Third Embodiment In the memory device 100 of the third embodiment, the shape of the shielding electrode SH can also be a shape that has been reversed in the X direction. Hereinafter, a modification of the third embodiment will be described using FIG63 and FIG64. In addition, in the modification of the third embodiment, the shape of the XY cross-section at the memory region MR of the memory cell array 110 is set to be the same as that in FIG27.

[0131] Figures 63 and 64 are cross-sectional views showing one example of the structure of the memory cell array 110 provided in the memory device 100 of the third embodiment. Figure 63 shows a cross-section at the same position as the cross-section along line XXVIII-XXVIII of Figure 27. Figure 64 shows a cross-section at the same position as the cross-section along line XXIX-XXIX of Figure 27.

[0132] As shown in FIG. 63, in the XY cross-section, the side portion of the semiconductor layer 30 in the third embodiment, on the other side in the X direction (conductor layer 72), is formed as an arc along a circle centered on the center position of the conductive member 21 (via wiring). Although not shown in the figure, in the XY cross-section, the side portion of the semiconductor layer 50b on the other side in the X direction is formed as an arc along a circle centered on the center position of the conductive member 21 (via wiring). In the XY cross-section, the side portion of the semiconductor layer 31 in the third embodiment, on one side in the X direction (conductor layer 70 side), is formed as an arc along a circle centered on the center position of the conductive member 21 (via wiring). Although not shown in the diagram, in the XY cross-section, one side of the conductive layer 51b in the X direction is formed as an arc along a circle centered on the center of the conductive member 21 (via wiring). Although not shown in the diagram, in the XY cross-section, the other side of the conductive layer 51b in the X direction is formed as an arc along a circle centered on the center of the conductive member 22 (via wiring). Although not shown in the diagram, in the XY cross-section, one side of the conductive layer 52b in the X direction is formed as an arc along a circle centered on the center of the conductive member 22 (via wiring).

[0133] As shown in FIG. 64, in the XY cross-section, the side portion of the conductive layer 60b of the modified third embodiment in the X direction is formed as an arc along a circle centered on the center position of the conductive member 21 (via wiring). In the XY cross-section, the other side portion of the conductive layer 60b of the modified third embodiment in the X direction is formed as an arc along a circle centered on the center position of the conductive member 22 (via wiring). In the XY cross-section, the side portion of the insulating layer 61b of the modified third embodiment in the X direction is formed as an arc along a circle centered on the center position of the conductive member 21 (via wiring). In the XY cross-section, the other side portion of the insulating layer 61b of the modified third embodiment in the X direction is formed as an arc along a circle centered on the center position of the conductive member 21 (via wiring). Furthermore, in the XY section, the shape of the portion of the insulating layer 61b on the other side in the X direction of the modified example of the third embodiment is convex lens-shaped.

[0134] The other configurations of the memory device 100 in the modified example of the third embodiment are the same as those of the memory device 100 in the third embodiment. The memory device 100 in the modified example of the third embodiment can achieve the same effect as the third embodiment.

[0135] <4> Fourth Embodiment In the memory device 100A of the fourth embodiment, a shielding electrode SH, identical to that of the first embodiment, is assembled at the DRAM of the memory cell having a 2TOC (2 transistors and 0 capacitors) structure. Hereinafter, the details of the memory device 100A of the fourth embodiment will be explained, mainly focusing on the differences from the first to third embodiments.

[0136] <4-1>Structure First, the structure of the memory device 100A in the fourth embodiment will be explained using Figures 65 to 69.

[0137] <4-1-1> Figure 65, showing the structure of memory device 100A, is a perspective view illustrating one example of the structure of memory device 100A in the fourth embodiment. As shown in Figure 65, memory device 100A, compared to memory device 100 in the first embodiment, has a configuration in which memory cells MC are replaced with memory cells MCa and multiple ground lines GND are omitted. Specifically, the memory region MR in the fourth embodiment includes multiple memory cells MCa, multiple write word lines WWL, and multiple read word lines RWL. Furthermore, the memory region MR includes multiple memory layers ML arranged side by side in the Z direction.

[0138] Each memory layer ML of the fourth embodiment includes a pair of write word lines WWL and read word lines RWL arranged side by side in the X direction, and a plurality of memory cells MCa arranged side by side in the Y direction. In each memory layer ML of the fourth embodiment, each of the plurality of memory cells MCa is respectively disposed between the pair of write word lines WWL and read word lines RWL, and is electrically connected to each of the pair of write word lines WWL and read word lines RWL.

[0139] In the memory region MR of the fourth embodiment, a pair of write bit lines WBL and read bit lines RBL are arranged side by side in the X direction. In the memory region MR, a plurality of write bit lines WBL are arranged side by side in the Y direction. In the memory region MR, a plurality of read bit lines RBL are arranged side by side in the Y direction. A pair of write bit lines WBL and read bit lines RBL are electrically connected to a memory cell MCa at each memory layer ML.

[0140] Furthermore, the structure of the memory device 100A in the fourth embodiment is not limited to the structure shown in FIG65. In the memory region MR, the number of write word lines (WWL) arranged side-by-side in the Z direction and the number of read word lines (RWL) arranged side-by-side in the Z direction are each only two or more. Also, in the memory region MR, the number of write bit lines (WBL) arranged side-by-side in the Y direction and the number of read bit lines (RBL) arranged side-by-side in the Y direction are each only two or more.

[0141] <4-1-2> Circuit configuration diagram 66 is a circuit diagram illustrating one example of the circuit configuration of the memory cell MCa provided in the memory device 100A of the fourth embodiment. Figure 66 shows one memory cell MCa, a pair of write word lines WWL and read word lines RWL, and a pair of write bit lines WBL and read bit lines RBL. As shown in Figure 66, the memory cell MCa is constructed using a 2TOC structure. Specifically, the memory cell MCa, for example, includes a write transistor WT, a read transistor RT, and a storage node SN.

[0142] The structure of the write transistor WT of the memory cell MCa is the same as that of the write transistor WT of the memory cell MC described in the first embodiment.

[0143] The read transistor RT is, for example, a field-effect type NMOS transistor. The gate electrode of the read transistor RT is connected to the storage node SN. One electrode of the read transistor RT is connected to the read bit line RBL. The other electrode of the read transistor RT is connected to the read word line RWL. Each of the electrodes of the read transistor RT functions as a source electrode or a drain electrode depending on the voltage supplied to the read transistor RT.

[0144] The storage node SN of the memory cell MCa is the same as that of the memory cell MC in the first embodiment, and has a parasitic capacitance (<1 fF). The memory cell MCa is able to store data in response to the potential of the parasitic capacitance of the storage node SN, that is, in response to the amount of charge stored in the storage node SN. The leakage current from the storage node SN is regulated by the leakage current of the write transistor WT. Therefore, during the read operation, the memory device 100A can read the data of the memory cell MCa non-destructively by reading the current of the read transistor RT corresponding to the potential of the storage node SN.

[0145] In the memory device 100A of the fourth embodiment, a shielding electrode SH is provided near the memory cell MCa. The shielding electrode SH is electrically connected to the read bit line RBL. The shielding electrode SH is arranged opposite to the storage node SN and suppresses interference between two adjacent memory cells MCa in the Z direction. In FIG66, the parasitic capacitance between the storage node SN and the shielding electrode SH is shown as the parasitic capacitance SC. The detailed arrangement between the two adjacent memory cells MCa in the Z direction and the shielding electrode SH will be described later.

[0146] <4-1-3> The structures of the memory cell array 110 are shown in Figures 67 to 69, which are cross-sectional views illustrating one example of the structure of the memory cell array 110 provided in the memory device 100A of the fourth embodiment. Figure 67 is an XZ cross-section corresponding to the memory cell array 110 disposed at the memory region MR in the fourth embodiment, and the region containing two adjacent memory cells MCa in the Z direction is shown. Figure 68 is a cross-section corresponding to the line LXVIII-LXVIII in Figure 67. Figure 69 is a cross-section corresponding to the line LXIX-LXIX in Figure 67.

[0147] The memory device 100A of the fourth embodiment includes a configuration in which the configuration related to the read transistor RT2 is omitted from the configuration of the memory device 100 of the first embodiment. Furthermore, in the memory device 100A of the fourth embodiment, the configuration corresponding to the read transistor RT1 of the first embodiment is used at the read transistor RT. Hereinafter, the semiconductor layer 31 and the insulating layer 41 provided in the memory device 100A of the fourth embodiment will be referred to as semiconductor layer 31a and insulating layer 41a, respectively.

[0148] As shown in FIG. 67, the conductive member 21 of the fourth embodiment has the same structure as that of the first embodiment and functions as the read bit line RBL. The semiconductor layer 31a has a cylindrical first portion extending in the Z direction and disposed on the side of the conductive member 21, and a second portion extending in the X direction at the memory layer ML. The insulating layer 40a has a cylindrical first portion extending in the Z direction and disposed on the side of the first portion of the semiconductor layer 30a, and a second portion disposed at the memory layer ML on the top, bottom, both sides in the Y direction, and one side (conductor layer 70 side) of the second portion of the semiconductor layer 30a. The read word line RWL of the fourth embodiment further includes a conductive layer 74. The conductive layer 74, for example, is disposed on the top, bottom, both sides in the Y direction, and one side in the X direction of the conductive layer 73. At each memory layer ML, the second portion of semiconductor layer 31a is connected to a read word line RWL (e.g., conductor layer 74) disposed on the same layer. Furthermore, semiconductor layer 31a is electrically connected to conductor layer 72 via conductor layers 74 and 73.

[0149] As shown in FIG. 68, in the XY cross-section, one side portion of the semiconductor layer 31a in the X direction is formed as an arc along a circle centered on the center position of the conductive member 20 (via wiring). In the XY cross-section, the other side portion of the semiconductor layer 31a in the X direction is, for example, formed as a straight line along the conductive layer 72. In the XY cross-section, the portion of the insulating layer 41a disposed near the boundary of the readout transistor RT and the readout word line RWL is connected to two adjacent insulating members 11 in the Y direction. Although not shown in the figure, in the XY cross-section, the other side portion of the conductive layer 50 in the X direction is formed as an arc along a circle centered on the center position of the conductive member 20 (via wiring). Although the illustration is omitted, in the XY cross section, the side portion of one side of the conductive layer 51 in the X direction is formed as an arc along a circle centered on the center position of the conductive member 20 (through-hole wiring).

[0150] As shown in FIG. 69, in the XY cross-section, the side portions of the conductive layer 60 in the Y direction are formed in a straight line along two adjacent insulating members 11 in the Y direction. Furthermore, in the XY cross-section, the "side portion of the conductive layer 60 in the X direction on one side" and the "side portion of the conductive layer 60 in the X direction on the other side" are each formed as an arc along a circle centered on the center position of the conductive member 21 (through-hole wiring). In the XY cross-section, the insulating layer 61 is provided to surround the outer periphery of the conductive layer 60. Specifically, in the XY cross-section, the insulating layer 61 has a "partition sandwiched between the insulating member 11 on one side of the Y direction and the conductive layer 60" and a "partition sandwiched between the insulating member 11 on the other side of the Y direction and the conductive layer 60".

[0151] As described above, at two adjacent memory cells MCa in the Z direction, two adjacent conductor layers 51 (storage nodes SN) in the Z direction are adjacent to each other, separated by a conductor layer 60, just as in the first embodiment. The conductor layer 60, when viewed in planar view, is arranged such that it overlaps with the conductor layer 51 (storage node SN). Ideally, the conductor layer 60 should completely overlap with the conductor layer 51 when viewed in planar view. Furthermore, the conductor layer 60 is electrically connected to the conductive member 21. Therefore, the conductor layer 60 can function as a shielding electrode SH.

[0152] The other components of the memory device 100A in the fourth embodiment are the same as those of the memory device 100 in the first embodiment.

[0153] <4-2> Manufacturing Method Next, as a manufacturing method for the memory device 100A of the fourth embodiment, the process of forming the memory cell array 110 will be described using Figures 70 to 79. Figures 70 to 79 each show a region that is the same as one of the memory region MR shown in Figure 67, the memory layer ML shown in Figure 68, and the isolation layer SL shown in Figure 69. Figures 70 to 79 each are cross-sectional views showing one example of the structure of the memory device 100A of the fourth embodiment during the manufacturing process.

[0154] In the manufacturing method of the memory device 100A in the fourth embodiment, firstly, the same process as that described in Figures 7 to 10 in the first embodiment is performed. By performing the above process, the structure shown in Figure 70 is formed.

[0155] Next, as shown in FIG71, at the memory region MA, a hole HWBL is formed at the portion corresponding to the write bit line WBL, and a hole HRBL is formed at the portion corresponding to the read bit line RBL. Although the illustration is omitted, both the holes HWBL and HRBL are formed by anisotropic etching such as RIE, extending in the Z direction and penetrating the laminated insulating layer 10 and the sacrificial member 12.

[0156] Next, as shown in FIG72, (1) by selectively removing the sacrificial members 12 of each memory layer ML through the hole HWBL, a recess is formed; (2) by filling the recess to be formed, the conductive film 82 and the sacrificial member 83 are formed sequentially. In this process, a wet etching process is used, for example, in forming the recess. The recess formed corresponding to the hole HWBL corresponds to the location where the write transistor WT is formed. The conductive film 82 of each hole HWBL is at the memory layer ML and is in contact with each of the sacrificial members 12 and 80. Furthermore, the conductive film 82 is at the hole HWBL and covers the top, bottom, two sides in the X direction, and two sides in the Y direction of the insulating layer 10. In this process, the sacrificial member 83 can also be formed by filling the hole HGND. Both the conductive film 82 and the sacrificial member 83 are formed, for example, by CVD or the like. The conductive film 82 is, for example, titanium nitride (TiN). The sacrificial member 83 is, for example, amorphous silicon (aSi).

[0157] Next, as shown in FIG. 73, a portion of the insulating layer 10 is selectively removed via the hole HRBL. In this process, wet etching is used, for example, for the removal of the insulating layer 10. In this process, the recess formed in the insulating layer SL in conjunction with the hole HRBL corresponds to the location where the shielding electrode SH is formed.

[0158] Next, as shown in FIG. 74, (1) the insulating film corresponding to the insulating layer 61 and the conductive film corresponding to the conductive layer 60 are formed, and (2) the insulating film and the conductive film disposed on the side portion of the hole HRBL are removed. Thus, the structure corresponding to the shielding electrode SH is formed. Furthermore, through this process, the side surfaces of the sacrificial members 12 of each memory layer ML are exposed within the hole HRBL. In this process, for example, CVD is used in the formation of the insulating film and the conductive film.

[0159] Next, as shown in FIG. 75, the sacrificial members 12 of each memory layer ML are selectively removed via the hole HRBL. Conductor layers 50 and 51 are formed at each memory layer ML, an insulating layer 40 is formed, and sacrificial members 85 and 92 are formed. The structure shown in FIG. 75 can be formed by utilizing the slit SLT on the other side of the hole HWBL and HRBL in the X direction, and is suitable for etching and film formation processes. The conductive layer 50 of each memory layer ML is formed by processing the conductive film 82. The conductive layer 51 is, for example, a conductive oxide such as indium tin oxide (ITO). The sacrificial member 85 is provided such that it covers the insulating layer 40 at least within the hole HWBL. The sacrificial member 92 is installed at each memory layer ML by filling the space enclosed by the disk-shaped conductive layer 51 and the space formed by the read word line RWL. The sacrificial members 85 and 92 are, for example, amorphous silicon (aSi).

[0160] Next, as shown in FIG. 76, (1) a portion of the sacrificial member 92 disposed at the memory layer ML is selectively removed via the hole HRBL, and (2) the insulating layer 41a is formed via the hole HRBL. The conductive layer 51 processed in this process corresponds to the shape of the conductive layer 51 (storage node SN) shown in FIG. 67. The removal of the sacrificial member 92 is, for example, performed using a wet etching process. The insulating layer 41 is, for example, formed by CVD or the like.

[0161] Next, as shown in FIG. 77, the sacrificial member 87 is embedded in the space sandwiched in the Z direction by the insulating layer 41 at each memory layer ML. The sacrificial member 87 is formed, for example, by CVD or the like. In this process, the sacrificial member 87 formed at the side portion of the hole HRBL is removed by an etch-back process. The sacrificial member 87 is, for example, amorphous silicon (aSi).

[0162] Next, as shown in FIG. 78, the insulating layer 41a formed on the side portion of the hole HRBL at each isolation layer SL is selectively removed via the hole HRBL. As a result, a portion of the conductive layer 60 is exposed in the portion of the hole HRBL corresponding to each isolation layer SL. The removal of the insulating layer 41a is, for example, performed using a wet etching process.

[0163] Next, as shown in FIG. 79, (1) sacrificial members 85 and 87 are selectively removed, (2) semiconductor layers 30 and 31a are formed, and (3) conductive members 20 and 21 are respectively buried in holes HWBL and HRBL. Afterwards, a portion of the insulating layer 41a on the side of sacrificial member 80 and read bit line RBL is removed, and the structure corresponding to write word line WWL and read word line RWL is formed. As a result, the structure of memory cell array 110 shown in FIGS. 67 to 69 is completed.

[0164] <4-3> Effects of the Fourth Embodiment The memory device 100A of the fourth embodiment has a configuration in which a "memory cell MC composed of 2 TOCs (2 transistors and 0 capacitors)" and a "shielding electrode SH" as described in the first embodiment are combined. The shielding electrode SH of the fourth embodiment is capable of suppressing interference between the two memory cells MCa disposed above and below the shielding electrode SH.

[0165] As a result, the memory device 100A of the fourth embodiment, being the same as that of the first embodiment, can reduce the pitch of the memory cells MCa arranged side by side in the Z direction, thereby providing a high-density and low-cost 3D stacked memory. Furthermore, the shielding electrode SH of the fourth embodiment, being the same as that of the first embodiment, can improve noise resistance because a capacitor (<1 fF) can be added between the storage node SN and the conductive member 21.

[0166] <5> Other In the memory device 100 of the above embodiment, a configuration is formed in which "a memory cell MC formed by at least two transistors arranged side by side in the horizontal direction (X direction)" is stacked multiple times in the vertical direction (Z direction) of the semiconductor substrate SUA. The write transistor WT and the read transistor RT are each formed by a disk-shaped GAA structure. A shielding electrode SH is disposed between two adjacent storage nodes SN in the Z direction. The shielding electrode SH is connected to an electrode inside a vertical hole (hole HGND or HRBL).

[0167] In the above embodiment, the vertical wiring located at the center of the memory cell MC is referred to as "GND" in the same way as ground wire GND and hole HGND, but these wirings are not necessarily grounded. In the above embodiment, ground wire GND can also be referred to as "power line PL" or "center line". Similarly, hole HGND can also be referred to as "hole HPL" or "hole HCL".

[0168] Furthermore, in this specification, the direction intersecting a specific surface may be referred to as the "first direction," the direction intersecting the first direction along this specific surface may be referred to as the "second direction," and the direction intersecting the second direction along this specific surface may be referred to as the "third direction." Each of the first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to each other. The gate electrode may also be referred to as the "gate." One end electrode may also be referred to as "one end." The other end electrode may also be referred to as "the other end." The manufacturing method described in the above embodiments is only one example. Other manufacturing methods may also be used as long as the structure described in each embodiment can be formed.

[0169] In this specification, the term "connection" refers to being electrically connected, and does not exclude situations where other components are intervening. "Being electrically connected" can also include an insulator, as long as it allows for the same operation as the electrically connected component. Write character lines (WWL), read character lines (RWL), write bit lines (WBL), and read bit lines (RBL) can also be referred to as "wiring". "Conductive layer" can also be referred to as "conductive film". "Insulating layer" can also be referred to as "insulating film".

[0170] Although several embodiments of the present invention have been described, these embodiments are merely illustrative examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or their variations are also included in the scope or spirit of the invention, and are also included within the scope of the invention described in the claims and their equivalents. [Simplified Explanation of the Diagram]

[0004] [Figure 1] is a block diagram showing one example of the configuration of a memory system having the memory device of the first embodiment. [Figure 2] is a perspective view showing one example of the structure of the memory device of the first embodiment. [Figure 3] is a circuit diagram showing one example of the circuit configuration of the memory cells of the memory device of the first embodiment. [Figure 4] is a cross-sectional view showing one example of the structure of the memory cell array of the memory device of the first embodiment. [Figure 5] is a cross-sectional view along line VV of Figure 4 showing one example of the structure of the memory cell array of the memory device of the first embodiment. [Figure 6] is a cross-sectional view along line VI-VI of Figure 4 showing one example of the structure of the memory cell array of the memory device of the first embodiment. [Figure 7] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 8] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 9] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 10] is a cross-sectional view along line XX of Figure 9 showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 11] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 12] is a cross-sectional view along line XII-XII of Figure 11 showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 13] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 14] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 15] is a cross-sectional view along line XV-XV of Figure 14 showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 16] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 17] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 18] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 19] is a cross-sectional view showing one example of the structure of the memory device in the manufacturing process of the first embodiment. [Figure 20] is a cross-sectional view showing one example of the structure of the memory device in the manufacturing process of the first embodiment.[Figure 21] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 22] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 23] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 24] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the first embodiment. [Figure 25] is a circuit diagram showing one example of the circuit configuration of the memory cells in the memory device of the comparative example. [Figure 26] is a cross-sectional view showing one example of the structure of the memory cell array in the memory device of the comparative example. [Figure 27] is a cross-sectional view showing one example of the structure of the memory cell array in the memory device of the second embodiment. [Figure 28] is a cross-sectional view along line XXVIII-XXVIII of Figure 27, showing one example of the structure of the memory cell array in the memory device of the second embodiment. [Figure 29] is a cross-sectional view along line XXIX-XXIX of Figure 27, showing one example of the structure of the memory cell array in the memory device of the second embodiment. [Figure 30] is a cross-sectional view showing one example of the structure of the memory device of the second embodiment during the manufacturing process. [Figure 31] is a cross-sectional view along line XXXI-XXXI of Figure 30, showing one example of the structure of the memory device of the second embodiment during the manufacturing process. [Figure 32] is a cross-sectional view showing one example of the structure of the memory device of the second embodiment during the manufacturing process. [Figure 33] is a cross-sectional view showing one example of the structure of the memory device of the second embodiment during the manufacturing process. [Figure 34] is a cross-sectional view along line XXXIV-XXXIV of Figure 33, showing one example of the manufacturing process structure of the memory device of the second embodiment. [Figure 35] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the second embodiment. [Figure 36] is a cross-sectional view along line XXXVI-XXXVI of Figure 35, showing one example of the manufacturing process structure of the memory device of the second embodiment. [Figure 37] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the second embodiment. [Figure 38] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the second embodiment.[Figure 39] is a cross-sectional view along line XXXIX-XXXIX of Figure 38, showing one example of the structure of the memory device in the manufacturing process of the second embodiment. [Figure 40] is a cross-sectional view showing one example of the structure of the memory device in the manufacturing process of the second embodiment. [Figure 41] is a cross-sectional view along line XLI-XLI of Figure 40, showing one example of the structure of the memory device in the manufacturing process of the second embodiment. [Figure 42] is a cross-sectional view showing one example of the structure of the memory cell array in the memory device of the third embodiment. [Figure 43] is a cross-sectional view along line XLIII-XLIII of Figure 42, showing one example of the structure of the memory cell array in the memory device of the third embodiment. [Figure 44] is a cross-sectional view showing one example of the structure of the memory cell array in the memory device of the third embodiment, and is a cross-sectional view along line XLIV-XLIV of Figure 42. [Figure 45] is a cross-sectional view showing one example of the structure of the memory device of the third embodiment in the manufacturing process. [Figure 46] is a cross-sectional view showing one example of the structure of the memory device of the third embodiment in the manufacturing process. [Figure 47] is a cross-sectional view showing one example of the structure of the memory device of the third embodiment in the manufacturing process, along line XLVII-XLVII of Figure 46. [Figure 48] is a cross-sectional view showing one example of the structure of the memory device of the third embodiment in the manufacturing process. [Figure 49] is a cross-sectional view along line XLIX-XLIX of Figure 48, showing one example of the manufacturing process structure of the memory device of the third embodiment. [Figure 50] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the third embodiment. [Figure 51] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the third embodiment. [Figure 52] is a cross-sectional view along line LII-LII of Figure 50, showing one example of the manufacturing process structure of the memory device of the third embodiment. [Figure 53] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the third embodiment. [Figure 54] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the third embodiment. [Figure 55] is a cross-sectional view along the LV-LV line of Figure 54, showing one example of the structure of the memory device in the manufacturing process of the third embodiment. [Figure 56] is a cross-sectional view showing one example of the structure of the memory device in the manufacturing process of the third embodiment.[Figure 57] is a cross-sectional view along line XVII-XVII of Figure 56, showing one example of the manufacturing process structure of the memory device of the third embodiment. [Figure 58] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the third embodiment. [Figure 59] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the third embodiment. [Figure 60] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the third embodiment. [Figure 61] is a cross-sectional view showing one example of the manufacturing process structure of the memory device of the third embodiment. [Figure 62] is a cross-sectional view along line LXII-LXII of Figure 61, showing one example of the manufacturing process structure of the memory device of the third embodiment. [Figure 63] is a cross-sectional view showing one example of the structure of the memory cell array in the memory device of the third embodiment. [Figure 64] is a cross-sectional view showing one example of the structure of the memory cell array in the memory device of the third embodiment. [Figure 65] is a perspective view showing one example of the structure of the memory device of the fourth embodiment. [Figure 66] is a circuit diagram showing one example of the circuit configuration of the memory cells in the memory device of the fourth embodiment. [Figure 67] is a cross-sectional view showing one example of the structure of the memory cell array in the memory device of the fourth embodiment. [Figure 68] is a cross-sectional view along line LXVIII-LXVIII of Figure 67 showing one example of the structure of the memory cell array in the memory device of the fourth embodiment. [Figure 69] is a cross-sectional view along line LXIX-LXIX of Figure 67, showing one example of the structure of the memory cell array in the memory device of the fourth embodiment. [Figure 70] is a cross-sectional view showing one example of the structure of the memory device of the fourth embodiment during the manufacturing process. [Figure 71] is a cross-sectional view showing one example of the structure of the memory device of the fourth embodiment during the manufacturing process. [Figure 72] is a cross-sectional view showing one example of the structure of the memory device of the fourth embodiment during the manufacturing process. [Figure 73] is a cross-sectional view showing one example of the structure of the memory device of the fourth embodiment during the manufacturing process. [Figure 74] is a cross-sectional view showing one example of the structure of the memory device of the fourth embodiment during the manufacturing process. [Figure 75] is a cross-sectional view showing one example of the construction of the memory device in the manufacturing process of the fourth embodiment.[Figure 76] is a cross-sectional view showing one example of the structure of the memory device in the manufacturing process of the fourth embodiment. [Figure 77] is a cross-sectional view showing one example of the structure of the memory device in the manufacturing process of the fourth embodiment. [Figure 78] is a cross-sectional view showing one example of the structure of the memory device in the manufacturing process of the fourth embodiment. [Figure 79] is a cross-sectional view showing one example of the structure of the memory device in the manufacturing process of the fourth embodiment.

Claims

1. A memory device comprising: A substrate; and a first conductive member and a second conductive member, each provided extending in a first direction intersecting the surface of the substrate and arranged side by side in a second direction parallel to the surface of the substrate; and a plurality of memory cells arranged side by side in the first direction, each including a first transistor and a second transistor arranged side by side in the second direction, the first transistor having a gate electrode and a channel region electrically connected to the first conductive member, the second transistor having a channel region electrically connected to the second conductive member and a gate electrode electrically connected to the channel region of the first transistor; and a shielding electrode, located at each of two adjacent memory cells in the first direction, electrically connected to the second conductive member and arranged in a manner overlapping the gate electrode of the second transistor in the first direction.

2. The memory device as described in claim 1, wherein, The channel region of the first transistor covers the area around the first conductive member when viewed from the first direction. The channel region of the second transistor covers the area around the second conductive member when viewed from the first direction. The shielding electrode covers the area around the second conductive member when viewed from the first direction.

3. The memory device as described in claim 2, wherein, The aforementioned first transistor comprises a first semiconductor layer that functions as the aforementioned channel region, a first insulating layer that covers the top, bottom, and one side of the aforementioned second direction of the first semiconductor layer, and a first conductive layer that covers the top, bottom, and one side of the aforementioned second direction of the first insulating layer and functions as the aforementioned gate electrode. The aforementioned second transistor comprises a second semiconductor layer that functions as the aforementioned channel region, a second insulating layer that covers the top, bottom, and one side of the aforementioned second direction of the second semiconductor layer, and a second conductive layer that covers the top, bottom, and one side of the aforementioned second direction of the second insulating layer, is connected to the aforementioned first semiconductor layer, and functions as the aforementioned gate electrode.

4. The memory device as described in claim 3, wherein, The aforementioned second conductive layer is used as a storage node for the aforementioned memory cell.

5. The memory device as described in claim 3, wherein, The aforementioned shielding electrode, when viewed from the aforementioned first direction, is larger than the aforementioned second conductive layer and overlaps with the entirety of the aforementioned second conductive layer.

6. The memory device as described in claim 3, wherein, Furthermore, the system includes: an insulating film that isolates and insulates the aforementioned shielding electrode from the aforementioned second conductive layer, and has a composition different from that of the aforementioned first insulating layer and the aforementioned second insulating layer.

7. The memory device as described in claim 6, wherein, Each of the aforementioned first insulating layer and the aforementioned second insulating layer comprises silicon oxide, and the aforementioned insulating film comprises one of silicon nitride, silicon oxynitride, hafnium oxide, and aluminum oxide.

8. The memory device as described in claim 3, wherein, Each of the aforementioned first semiconductor layer and the aforementioned second semiconductor layer comprises an oxide semiconductor.

9. The memory device as described in claim 8, wherein, The aforementioned oxide semiconductor contains at least one of gallium and aluminum, as well as indium, zinc, and oxygen.

10. The memory device as described in claim 1, wherein, The aforementioned shielding electrode contains a conductive oxide.

11. The memory device as described in claim 10, wherein, The aforementioned conductive oxide includes indium tin oxide.

12. The memory device as described in claim 1, wherein, The system further includes: a third conductive member that extends in the first direction and is disposed on the other side of the second direction relative to the second conductive member; The first word line is disposed at each of the aforementioned plurality of memory cells and is electrically connected to the gate electrode of the aforementioned first transistor; and the second word line is disposed at each of the aforementioned plurality of memory cells. Each of the aforementioned plurality of memory cells further includes a third transistor disposed on the other side of the aforementioned second direction relative to the aforementioned second transistor. The aforementioned third transistor has a channel region electrically connected to the aforementioned third conductive member and electrically connected to the channel region of the aforementioned second transistor, and a gate electrode electrically connected to the aforementioned second word line.

13. The memory device as described in claim 2, wherein, The system further includes: a third conductive member that extends in the first direction and is disposed on the other side of the second direction relative to the second conductive member; The first word line is disposed at each of the aforementioned plurality of memory cells and is electrically connected to the gate electrode of the aforementioned first transistor; and the second word line is disposed at each of the aforementioned plurality of memory cells. Each of the aforementioned plurality of memory cells further includes a third transistor disposed on the other side of the aforementioned second direction relative to the aforementioned second transistor. The aforementioned third transistor has a channel region that, when viewed from the aforementioned first direction, covers the area surrounding the aforementioned third conductive member and is electrically connected to the aforementioned third conductive member and is electrically connected to the channel region of the aforementioned second transistor, and a gate electrode that is electrically connected to the aforementioned second word line.

14. The memory device as described in claim 13, wherein, The aforementioned first transistor comprises a first semiconductor layer that functions as a channel region, a first insulating layer covering the top, bottom, and one side of the aforementioned second direction of the first semiconductor layer, and a first conductive layer covering the top, bottom, and one side of the aforementioned second direction of the first insulating layer and functioning as the aforementioned gate electrode of the first transistor. The aforementioned second transistor comprises a second semiconductor layer that functions as a channel region, a second insulating layer covering the top, bottom, and one side of the aforementioned second direction of the second semiconductor layer, and a second conductive layer covering the top, bottom, and one side of the aforementioned second direction of the second insulating layer, connected to the aforementioned first semiconductor layer, and functioning as the gate electrode. The aforementioned third transistor comprises a third semiconductor layer that functions as a channel region, a third insulating layer that covers the top, bottom, and the other side of the aforementioned second direction of the aforementioned third semiconductor layer, and a third conductive layer that covers the top, bottom, and the other side of the aforementioned second direction of the aforementioned third insulating layer, is electrically connected to the aforementioned second character line, and functions as a gate electrode.

15. The memory device as described in claim 14, wherein, The end of the first conductor layer on the other side of the second direction and the end of the second conductor layer on one side of the second direction are kept at a certain distance from each other.

16. The memory device as described in claim 14, wherein, When viewed from the first direction, each of the aforementioned shielding electrode and the aforementioned second conductive layer has an arc-shaped portion on one side of the aforementioned second direction, which is configured to follow a circle centered on the center position of the aforementioned second conductive member, and an arc-shaped portion on the other side of the aforementioned second direction, which is configured to follow a circle centered on the center position of the aforementioned second conductive member.

17. The memory device as described in claim 14, wherein, When viewed from the first direction, each of the aforementioned shielding electrode and the aforementioned second conductive layer has an arc-shaped portion on one side of the aforementioned second direction, which is configured to follow a circle centered on the center position of the aforementioned first conductive member, and an arc-shaped portion on the other side of the aforementioned second direction, which is configured to follow a circle centered on the center position of the aforementioned third conductive member.

18. The memory device as described in claim 14, wherein, When viewed from the first direction, the aforementioned shielding electrode has an arc-shaped portion on one side of the second direction that is configured to run along a circle centered on the center of the first conductive member, or an arc-shaped portion on the other side of the second direction that is configured to run along a circle centered on the center of the third conductive member.

19. The memory device as described in claim 18, wherein, When viewed from the first direction, the aforementioned shielding electrode has a portion on one side of the second direction that is configured as an arc along a circle centered on the center of the first conductive member. Furthermore, when viewed from the first direction, the shielding electrode has a portion on the other side of the second direction that is configured as an arc along a circle centered on the center of the second conductive member. The aforementioned second conductive layer, when viewed from the first direction, has a portion on one side of the second direction that is configured as an arc along a circle centered on the center of the first conductive member, and a portion on the other side of the second direction that is configured as an arc along a circle centered on the center of the second conductive member. When viewed from the first direction, the aforementioned shielding electrode has a portion on the other side of the second direction that is configured as an arc along a circle centered on the center of the third conductive member. The aforementioned shielding electrode further includes, when viewed from the first direction, a portion that is configured as an arc along a circle centered on the center position of the aforementioned second conductive member on one side of the aforementioned second direction. The aforementioned second conductive layer, when viewed from the first direction, includes, a portion that is configured as an arc along a circle centered on the center position of the aforementioned third conductive member on the other side of the aforementioned second direction, and a portion that is configured as an arc along a circle centered on the center position of the aforementioned second conductive member on one side of the aforementioned second direction.

20. A memory device as described in any of claims 15, 17-19, wherein, The spacing between the upper and lower ends of the aforementioned second conductor layer in the first direction is narrower than both the spacing between the upper and lower ends of the aforementioned first conductor layer in the first direction and the spacing between the upper and lower ends of the aforementioned third conductor layer in the first direction.

21. The memory device as described in claim 14, wherein, Each of the aforementioned first conductive layer and the aforementioned third conductive layer does not have a portion that overlaps with the aforementioned shielding electrode in the aforementioned first direction.

22. The memory device as described in claim 1, wherein, The system further comprises: a first word line, which is disposed at each of the aforementioned plurality of memory cells and electrically connected to the gate electrode of the aforementioned first transistor; and a second word line, which is disposed at each of the aforementioned plurality of memory cells and electrically connected to the channel region of the aforementioned second transistor.

23. The memory device as described in claim 22, wherein, The channel region of the first transistor covers the area around the first conductive member when viewed from the first direction. The channel region of the second transistor covers the area around the second conductive member when viewed from the first direction. The shielding electrode covers the area around the second conductive member when viewed from the first direction.

24. The memory device as described in claim 23, wherein, The aforementioned first transistor comprises a first semiconductor layer that functions as the aforementioned channel region, a first insulating layer that covers the top, bottom, and one side of the aforementioned second direction of the first semiconductor layer, and a first conductive layer that covers the top, bottom, and one side of the aforementioned second direction of the first insulating layer and functions as the aforementioned gate electrode. The aforementioned second transistor comprises a second semiconductor layer that functions as the aforementioned channel region, a second insulating layer that covers the top, bottom, and one side of the aforementioned second direction of the second semiconductor layer, and a second conductive layer that covers the top, bottom, and one side of the aforementioned second direction of the second insulating layer, is connected to the aforementioned first semiconductor layer, and functions as the aforementioned gate electrode.

25. The memory device as described in claim 24, wherein, The aforementioned shielding electrode has an arc-shaped portion, when viewed from the first direction, positioned on one side and the other side of the aforementioned second direction, along a circle centered on the center position of the aforementioned second conductive member. The aforementioned first conductive layer, when viewed from the first direction, has an arc-shaped portion, when viewed from the other side of the aforementioned second direction, positioned along a circle centered on the center position of the aforementioned first conductive member.

Images