Manufacturing method of semiconductor structure
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- POWERCHIP SEMICON MFG CORP
- Filing Date
- 2025-03-12
- Publication Date
- 2026-08-01
Smart Images

Figure TWG2TB001903853_001 
Figure TWG2TB001903853_002 
Figure TWG2TB001903853_003
Abstract
Claims
1. A method for manufacturing a semiconductor structure, comprising: Provide wafer structure; A first wafer is bonded to the wafer structure, wherein the first wafer includes a first substrate and a first element layer located on the first substrate; After the first wafer is bonded to the wafer structure, a first opening is formed in the first substrate, wherein the first opening exposes the first element layer; a dielectric layer is formed on the first substrate and in the first opening; And forming a first substrate via through the first opening in the dielectric layer, wherein the first substrate via extends into the first element layer, and the method of forming the first substrate via includes: forming a second opening in the dielectric layer and the first element layer; And forming the first substrate perforation in the second opening.
2. The method of manufacturing a semiconductor structure as claimed in claim 1, wherein the minimum width of the first opening is greater than the maximum width of the first substrate via.
3. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the first substrate via directly contacts the dielectric layer.
4. A method of manufacturing a semiconductor structure as claimed in claim 1, wherein the first substrate via penetrates the first element layer.
5. A method of manufacturing a semiconductor structure as claimed in claim 1, wherein the first substrate via extends further into the wafer structure.
6. A method of manufacturing a semiconductor structure as claimed in claim 1, wherein the width of the portion of the first opening closest to the first element layer is smaller than the width of the portion of the first opening furthest from the first element layer.
7. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the method of bonding the first wafer to the wafer structure includes fusion bonding.
8. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the method of bonding the first wafer to the wafer structure includes a hybrid bonding method.
9. The method for manufacturing a semiconductor structure as described in claim 1, further comprising: Before forming the first opening, the first substrate is thinned.
10. A method of manufacturing a semiconductor structure as claimed in claim 1, wherein the wafer structure includes a second wafer, and the second wafer includes a second substrate and a second element layer located on the second substrate.
11. A method of manufacturing a semiconductor structure as claimed in claim 10, wherein the second substrate does not have an opening aligned with the first opening.
12. A method of manufacturing a semiconductor structure as claimed in claim 10, wherein the second substrate has a third opening aligned with the first opening.
13. A method of manufacturing a semiconductor structure as claimed in claim 1, wherein the wafer structure includes a barrier layer and the bottom of the first substrate through-hole directly contacts the barrier layer.
14. The method for manufacturing a semiconductor structure as described in claim 1, further comprising: A third opening is formed in the first substrate, wherein the third opening exposes the first element layer; The dielectric layer is formed in the third opening; And a second substrate via is formed in the dielectric layer through the third opening, wherein the second substrate via extends into the first element layer.
15. A method of manufacturing a semiconductor structure as claimed in claim 14, wherein the second substrate via directly contacts the dielectric layer.
16. A method of manufacturing a semiconductor structure as claimed in claim 14, wherein the first substrate via and the second substrate via have different depths in the wafer structure.
17. A method of manufacturing a semiconductor structure as claimed in claim 14, wherein the wafer structure includes a second wafer, and the second wafer includes a second substrate and a second element layer located on the second substrate.
18. A method of manufacturing a semiconductor structure as claimed in claim 17, wherein the second substrate has a fourth opening aligned with the first opening, and the second substrate does not have an opening aligned with the third opening.
19. A method of manufacturing a semiconductor structure as claimed in claim 17, wherein the second substrate has a fourth opening aligned with the first opening, and the second substrate has a fifth opening aligned with the third opening.