Substrate
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- VESTA MICROSYSTEM CO LTD
- Filing Date
- 2025-03-24
- Publication Date
- 2026-08-01
Smart Images

Figure 00000000_0000_ABST
Abstract
Claims
1. A substrate, comprising: A substrate layer, wherein the substrate layer is made of glass or ceramic; and a perforation, comprising: a first conductive element; a second conductive element, the second conductive element being a point structure in the form of a metal pillar; and an insulating element, spaced apart from the first conductive element and the second conductive element, such that the first conductive element and the second conductive element are electrically independent of each other within the perforation.
2. The substrate as claimed in claim 1, wherein the material of the insulating element is the same as or different from the material of the base layer.
3. The substrate as claimed in claim 1, wherein the first conductive element is in direct contact with the hole wall of the substrate layer, and the insulating element is disposed between the first conductive element and the second conductive element.
4. The substrate as claimed in claim 3, wherein the first conductive element is a closed-loop structure.
5. The substrate as claimed in claim 4 further includes a third conductive element in a closed-loop annular structure, wherein the third conductive element is disposed between the first conductive element and the second conductive element and is electrically independent of each other.
6. The substrate as claimed in claim 3, wherein the first conductive element is a non-closed annular structure having multiple arc-shaped segments, and the second conductive element is a point structure of the form of a single or multiple metal pillars.
7. The substrate of claim 6, wherein the contours of the plurality of top surfaces of the plurality of arcuate segments are offset from the contours of the plurality of bottom surfaces of the plurality of arcuate segments.
8. The substrate as claimed in claim 7, wherein a first notch is provided between two adjacent top surfaces, a second notch is provided between two adjacent bottom surfaces, and the first notch and the second notch do not overlap in the orthographic projection direction.
9. The substrate as claimed in claim 1, further comprising a circuit structure disposed on the substrate layer, wherein the first conductive element and the second conductive element are electrically connected outside the via to the same conductive trace in the circuit structure.
10. The substrate as claimed in claim 1, further comprising a circuit structure disposed on the substrate layer, wherein the first conductive element and the second conductive element are electrically connected to different conductive traces in the circuit structure outside the through-hole.