Method for analyzing SRAM voltage parameter and computer readable media

Abstract

A method for analyzing memory voltage parameters and a computer-readable medium are disclosed. The method includes setting an initial value, an ending value, and a step value from the initial value to the ending value for a test voltage. Multiple memory elements are then repeatedly tested from the initial value to the ending value to obtain the fail bit count (FBC) value under different test voltages. The difference between the current FBC value and the previous FBC value is used as the numerator, and the difference between the current test voltage and the previous test voltage is used as the denominator to obtain multiple FBC slopes under different test voltages. All test voltages with FBC slopes greater than a set value are recorded as VCCMIN. A VCCMIN relationship graph is plotted to confirm the performance of each memory element.

Claims

1. A method for analyzing memory voltage parameters, comprising: Set the initial value, the final value, and the step value from the initial value to the final value of the test voltage. Starting from the initial value and ending at the final value, multiple memory elements are repeatedly tested to obtain the fail bit count (FBC) value under different test voltages. Using the difference between the current FBC value and the previous FBC value as the numerator and the difference between the current test voltage and the previous test voltage as the denominator, multiple FBC slopes under different test voltages are obtained. All test voltages with slopes greater than a set value are recorded as VCCMIN. A VCCMIN relationship graph is then plotted to confirm the performance of each memory element. The horizontal axis of the VCCMIN relationship graph is VCCMIN, and the vertical axis is the accumulated value (ACC), where the accumulated value is the ratio of VCCMIN to the operating voltage, and this ratio ranges from 0% to 100%.

2. The memory voltage parameter analysis method as described in claim 1, wherein the initial value is the lower limit voltage of the test voltage and the termination value is the upper limit voltage of the test voltage.

3. The memory voltage parameter analysis method as described in claim 1, wherein the set value is greater than 0 and less than 100.

4. The memory voltage parameter analysis method as described in claim 1, wherein the memory element includes an SRAM element.

5. A method for analyzing memory voltage parameters, comprising: Set the initial value, the final value, and the step value from the initial value to the final value of the test voltage. Starting from the initial value and ending at the final value, multiple memory elements are repeatedly tested to obtain multiple fail bit count (FBC) curves under different test voltages; the multiple FBC curves are differentiated twice to obtain multiple FBC curvatures under different test voltages; all test voltages corresponding to the multiple FBC curvatures that are greater than a set value are recorded as VCCMIN, where the set value is greater than 0 and less than 100; and a VCCMIN relationship graph is plotted to confirm the performance of each memory element, where the horizontal axis of the VCCMIN relationship graph is VCCMIN and the vertical axis is the accumulated value (ACC), where the accumulated value represents how much it increases by up to 100% at each voltage.

6. The memory voltage parameter analysis method as described in claim 5, wherein the initial value is the lower limit voltage of the test voltage and the termination value is the upper limit voltage of the test voltage.

7. The memory voltage parameter analysis method as described in claim 5, wherein the memory element includes an SRAM element.

8. A method for analyzing memory voltage parameters, comprising: Set the initial value, the final value, and the step value from the initial value to the final value of the test voltage. The following steps are performed on multiple memory elements: a) Test one of the multiple memory elements with the initial value to obtain the first fail bit count (FBC) value; b) Continuously test the memory element for the Nth time to obtain the Nth FBC value, wherein the test voltage of the Nth test is the initial value plus (N-1) times the step value, where N is an integer greater than 1; c) Obtain the FBC slope, which is the difference between the current FBC value and the previous FBC value divided by the difference between the current test voltage and the previous test voltage. And d) Compare the FBC slope with a set value. If the FBC slope is equal to or less than the set value, return to step b to perform the test of the next interval of the test voltage; if the FBC slope is greater than the set value, record the test voltage as VCCMIN.

9. The memory voltage parameter analysis method as described in claim 8, wherein the initial value is the lower limit voltage of the test voltage and the termination value is the upper limit voltage of the test voltage.

10. The memory voltage parameter analysis method as described in claim 8, wherein the memory element includes an SRAM element.

11. The memory voltage parameter analysis method as described in claim 8, wherein the set value is greater than 0 and less than 100.

12. The memory voltage parameter analysis method as described in claim 8, wherein the test of a memory element is terminated after obtaining the VCCMIN.

13. A computer-readable medium containing a program, which, when loaded and executed by a computer, can perform a memory voltage parameter analysis method as described in any one of claims 1 to 12.

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