Method for analyzing SRAM voltage parameter and computer readable media
The method of analyzing memory voltage parameters through setting test voltage ranges and plotting VCCMIN graphs addresses the challenge of identifying abnormal products in early semiconductor development, enhancing product yield and quality.
TWI934522BActive Publication Date: 2026-08-01POWERCHIP SEMICON MFG CORP
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Patent Information
- Application Number
- TW114110964
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2025-03-24
- Publication Date
- 2026-08-01
- Estimated Expiration
- 2045-03-23
AI Technical Summary
Technical Problem
Existing semiconductor manufacturing processes face challenges in identifying abnormal products during early stages of development, making it difficult to determine performance and direction for improvement.
Method used
A method for analyzing memory voltage parameters by setting initial and ending values for test voltages, obtaining fail bit count (FBC) slopes, and plotting VCCMIN relationship graphs to confirm memory element performance, along with a computer-readable medium to execute this method.
Benefits of technology
Enables accurate identification of abnormal memory elements in the early stages of semiconductor development, providing a basis for improving product yield and quality.
✦ Generated by Eureka AI based on patent content.
Abstract
A method for analyzing memory voltage parameters and a computer-readable medium are disclosed. The method includes setting an initial value, an ending value, and a step value from the initial value to the ending value for a test voltage. Multiple memory elements are then repeatedly tested from the initial value to the ending value to obtain the fail bit count (FBC) value under different test voltages. The difference between the current FBC value and the previous FBC value is used as the numerator, and the difference between the current test voltage and the previous test voltage is used as the denominator to obtain multiple FBC slopes under different test voltages. All test voltages with FBC slopes greater than a set value are recorded as VCCMIN. A VCCMIN relationship graph is plotted to confirm the performance of each memory element.
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