Semiconductor device

Abstract

The disclosed semiconductor device includes: a first circuit block that operates according to a first clock signal, the first circuit block including a multi-bit synchronizer and a temporary storage controller, the temporary storage controller including a first storage unit; and a second circuit block including a clock gate unit and a data storage circuit, the data storage circuit being coupled to the multi-bit synchronizer; wherein, when the first power domain is powered off and then powered on again, the data storage circuit provides the state value of the output signal of the first storage unit before the power failure to the multi-bit synchronizer.

Claims

1. A semiconductor device (40), comprising: A first circuit block (41) receives power from a first power domain (VDD0) and operates according to a first clock signal (CLK_A). The first circuit block (41) includes a multi-bit synchronizer (412) and a temporary storage controller (411). The temporary storage controller (411) includes at least one first storage unit (411b). The temporary storage controller (411) outputs a write pulse signal (wrbusy) to the multi-bit synchronizer (412). A second circuit block (42) receives power from a second power domain (VDD1) and includes a clock gate unit (421) and a data storage circuit (422, 423). The clock gate unit (421) selectively outputs a second clock signal (CLK_B) according to a gate signal. The data storage circuit (422, 423) is coupled to the multi-bit synchronizer (412). When the semiconductor device (40) enters a power-saving mode, the first power domain (VDD0) is powered off, and the second circuit block (42) causes the clock gate unit (421) to output the second clock signal (CLK_B) according to a storage enable signal (save_en); and when the semiconductor device (40) leaves the power-saving mode, the first power domain (VDD0) is powered on again, and the second circuit block (42) controls the clock gate unit (421) to stop outputting the second clock signal (CLK_B) when the storage enable signal (save_en) is a second logic level; wherein, when the data storage circuit (422, 423) is powered on again after the first power domain (VDD0) is powered off, it provides the status value of the output signal (int_sel) of the first storage unit (411b) before the power failure to the multi-bit synchronizer (412).

2. The semiconductor device as claimed in claim 1, wherein the clock gate unit (1502) is an integrated clock gate unit, and the write pulse signal (wrbusy) and the delayed write pulse signal (wrbusy_d) are connected to the input of the integrated clock gate unit (1502) through an OR gate (1501).

3. The semiconductor device as claimed in claim 1, wherein the temporary storage controller (411) further includes a read / write controller (411a) for controlling the writing and reading of data in the first storage cell (411b), and when the read / write controller (411a) modifies at least one circuit control parameter (PAR1) in the first storage cells (411b), the write pulse signal (wrbusy) output by the read / write controller (411a) is switched to a first logic level.

4. The semiconductor device as claimed in claim 1, wherein the multi-bit synchronizer (412) includes a plurality of serially connected flip-flops for synchronizing the output signal (int_sel) of the first storage cell (411b) to the clock domain of the second clock signal (CLK_B) and generating a synchronization output signal (int_sel_sync).

5. The semiconductor device as claimed in claim 4, wherein the data storage circuit (422, 423) comprises: A second storage unit (422); and a multiplexer (423); wherein, before entering the power saving mode, the second circuit block (42) saves the value of the synchronized output signal (int_sel_sync) as the state value through the clock gate control unit (421) and the second storage unit (422).

6. The semiconductor device as claimed in claim 1, wherein the multi-bit synchronizer (412) comprises: A synchronization control circuit block (81) is used to determine whether the multi-bit synchronizer (412) is in a busy state based on the write pulse signal (wrbusy) received by the multi-bit synchronizer (412); a data storage unit block (82) is used to write the status value (data_in_ret) received by the multi-bit synchronizer (412) from the second storage unit (422) into an output terminal (data_out) of the multi-bit synchronizer (412) according to a restore enable signal (restore_en) after the first power domain (VDD0) is restored; and a status control circuit block (83) is used to output a clear busy signal (clr_busy).

7. The semiconductor device as claimed in claim 6, wherein the output of the data storage unit block (82) includes a flip-flop (DFFs1) having a setting terminal (D), and the data storage unit block (82) selectively controls the setting terminal (D) according to the restore enable signal (restore_en) to write the status value (data_in_ret) to the output terminal (Q) of the flip-flop.

8. The semiconductor device as claimed in claim 1, wherein the first circuit block (41) further includes a scheduler for storing a complex array of addresses and data to be written to the first storage cell (411b), and sequentially providing the complex array of addresses and data to the read / write controller (411a).

9. The semiconductor device as claimed in claim 8, wherein when the complex array addresses and data stored in the scheduler have been written into the first storage unit (411b) and the corresponding synchronization actions have been completed, the scheduler outputs a clear status signal.

10. The semiconductor device as claimed in claim 6, wherein the restore enable signal (restore_en) is a multi-bit signal, each bit of the multi-bit signal corresponding to an output bit (data_out) of the multi-bit synchronizer (412), and the state control circuit block determines whether to write the bit value of the corresponding data save signal (int_sel_ret) to the output bit (data_out) of the multi-bit synchronizer (412) based on the value of each bit of the restore enable signal (restore_en).

11. The semiconductor device as claimed in claim 1, wherein the semiconductor device determines whether the synchronization operation is completed by polling the state of the write pulse signal (wrbusy).

12. The semiconductor device as claimed in claim 5, wherein the first storage cell (411b) and the second storage cell (422) share the write pulse signal (wrbusy).

13. The semiconductor device as claimed in claim 6, wherein the data storage unit block comprises: A first multiplexer has a first input terminal, a second input terminal, a selection terminal, and an output terminal, the selection terminal being used to receive a selection signal (load_pls); a second multiplexer has a first input terminal for receiving first data (data_in_ret), a selection terminal for receiving a restore enable signal (restore_en), and an output terminal; a third multiplexer has a first input terminal coupled to the output terminal of the first multiplexer, a second input terminal coupled to the output terminal of the second multiplexer, a selection terminal, and an output terminal; And a first flip-flop, having an input coupled to the output of the third multiplexer, and an output for outputting an output signal (data_out).

14. The semiconductor device as claimed in claim 6, wherein the data storage unit block comprises: A first multiplexer has a first input terminal, a second input terminal, a selection terminal and an output terminal, the selection terminal being used to receive a selection signal (load_pls); And a first flip-flop, having a first input terminal coupled to the output terminal of the first multiplexer, a second input terminal for receiving a restore enable signal (restore_en), a third input terminal for receiving a data input signal (data_in_ret), and an output terminal for outputting an output signal (data_out).

15. The semiconductor device as claimed in claim 6, wherein the multi-bit synchronizer is disposed in a first power domain, and the data storage unit block (82) includes a plurality of data storage units disposed in the plurality of power domains; the restore_en signal is used to control whether the corresponding bit in the corresponding output signal (data_out) requires a data input signal (data_in_ret) from any of the plurality of power domains to restore it to its value before power failure.

16. The semiconductor device as claimed in claim 1, further comprising a receiving clock generator, the receiving clock generator including: A first OR gate has a first input terminal for receiving a synchronization completion pulse signal (sync_finish_pls), a second input terminal for receiving a write synchronization signal (wrbusy_sync) after the write pulse signal has been synchronized, a third input terminal for receiving a delayed write synchronization signal (wrbusy_sync_d) after the write pulse signal has been delayed, and an output terminal; a first flip-flop has an input terminal coupled to the output terminal (wrbusy) of the first OR gate, and an output terminal; A second OR gate has a first input terminal coupled to the output terminal of the first flip-flop, a second input terminal for receiving the restore enable signal (restore_en), and an output terminal; And a first integrated clock gate control unit, having a first input terminal coupled to the output terminal of the second OR gate, a second input terminal for receiving a receive clock signal (receive_clk), and an output terminal for outputting a gate control receive clock signal (receive_clk_g).

17. The semiconductor device as claimed in claim 1, further comprising a transmission clock generator, the transmission clock generator including: A first OR gate has a first input terminal for receiving the write pulse signal (wrbusy), a second input terminal for receiving a delayed write pulse signal (wrbusy_d) after the write pulse signal has been delayed, and an output terminal; And a first integrated clock gate control unit, having a first input terminal coupled to the output terminal of the first OR gate, a second input terminal for receiving a transmit clock signal (transmit_clk), and an output terminal for outputting a gate control transmit clock signal (transmit_clk_g).

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