Packaging structure, packaging devices

Abstract

A packaging structure and a packaged device. The packaging structure includes: a dielectric layer; a first multi-level wiring layer located within the dielectric layer; a second multi-level wiring layer located on the first multi-level wiring layer, the first multi-level wiring layer and the second multi-level wiring layer being electrically connected, the top of the second multi-level wiring layer protruding from the dielectric layer; a wafer located on the dielectric layer; and leads connecting the wafer and the second multi-level wiring layer. This packaging structure has a small thickness.

Description

[Technical Field]

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a packaging structure and a packaging device. [Previous Technology]

[0002] Recently, the demand for portable devices in the electronics market has increased rapidly, thus there is a growing demand for miniaturization and weight reduction of electronic components installed in electronic products. [Summary of the Invention]

[0003] According to a first aspect of the present disclosure, a packaging structure is provided, comprising: a dielectric layer; a first rewiring layer located in the dielectric layer; a second rewiring layer located on the first rewiring layer, the first rewiring layer being electrically connected to the second rewiring layer, the top of the second rewiring layer protruding from the dielectric layer; a wafer located on the dielectric layer; and leads connecting the wafer and the second rewiring layer.

[0004] In some embodiments, the second redistribution layer includes: a main body portion located in the dielectric layer; and an extension portion located on the main body portion and extending to the top surface of the dielectric layer.

[0005] In some embodiments, the thickness of the main body is greater than the thickness of the extension in the vertical direction.

[0006] In some embodiments, there is an angle between the top surface of the extension and the top surface of the dielectric layer in the horizontal direction.

[0007] In some embodiments, the second redistribution layer further includes: a metal layer conformally disposed on the extension; wherein the thickness of the metal layer is less than the thickness of the extension.

[0008] In some embodiments, the lead is connected to the metal layer, and the angle between the metal layer and the lead is greater than the angle between the top surface of the metal layer and the top surface of the dielectric layer.

[0009] In some embodiments, the first redistribution layer includes: a lower conductive pattern located at the bottom of the dielectric layer, the lower conductive pattern extending horizontally in the dielectric layer; an intermediate conductive pattern located in the middle of the dielectric layer and connected to the lower conductive pattern; and an upper conductive pattern located in the upper part of the dielectric layer and connected to the intermediate conductive pattern.

[0010] In some embodiments, the material of the main body is different from the material of the upper conductive pattern, and the hardness of the main body is greater than the hardness of the upper conductive pattern.

[0011] In some embodiments, the intermediate conductive pattern includes: a vertical portion connected to the lower conductive pattern; and a horizontal portion connected to the vertical portion, extending horizontally in the dielectric layer; wherein, in the vertical direction, the thickness of the vertical portion is greater than the thickness of the horizontal portion.

[0012] In some embodiments, the width of the vertical portion is smaller than the width of the main body portion in the horizontal direction.

[0013] In some embodiments, the sidewall of the vertical portion has a first slope, and the top surface of the extension portion has a second slope, wherein the absolute value of the first slope is greater than the absolute value of the second slope.

[0014] In some embodiments, the main body portion is connected to the upper conductive pattern, and the thickness of the main body portion is greater than the thickness of the horizontal portion.

[0015] In some embodiments, the second redistribution layer is located on both sides of the wafer, and the spacing between the second redistribution layer on both sides and the wafer is different. In some embodiments, the second redistribution layer further includes: a recess extending from the extension to the main body; a gold ball located in the recess, and the lead connected to the gold ball; wherein the height of the gold ball is greater than the depth of the recess.

[0016] According to a second aspect of the present disclosure, a packaging device is provided, comprising: a substrate; and a packaging structure disposed on the substrate.

[0017] In summary, the embodiments of this disclosure propose a packaging structure and a packaging device. A first and second wiring layer are formed in a dielectric layer, with the top of the second wiring layer protruding beyond the dielectric layer. A wafer is then placed on the dielectric layer, and the second wiring layer and the wafer are connected by leads. Because the overall thickness of the dielectric layer is relatively small, and the top of the second wiring layer is outside the dielectric layer, the leads can be directly connected to the second wiring layer, thereby achieving miniaturization of the packaging structure.

Implementation Method

[0019] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementations of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0020] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and the claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0021] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0022] In the embodiments of this disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0023] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0024] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0025] With the trend of miniaturization of packaged products, the thickness of the substrate has a significant impact on the size of the package structure. The substrate is usually formed by stacking multiple organic material layers. In order to ensure the strength of the substrate, more organic material layers need to be stacked, which leads to the thickness of the substrate and thus the thickness of the package structure, which is not conducive to achieving miniaturized products.

[0026] This disclosure provides a packaging structure that uses a redistribution substrate as a support substrate. Since the redistribution substrate is formed through multiple deposition processes, the thickness of each film layer can be precisely controlled, thereby controlling the thickness of the redistribution layer and reducing the thickness of the redistribution substrate.

[0027] As shown in FIG. 1, this embodiment of the present disclosure proposes a packaging structure 100, which may include a dielectric layer 110, a first redistribution layer 120, a second redistribution layer 130, a wafer 140, leads 150, a molding compound layer 160, and external terminals 170. The first redistribution layer 120 is located in the dielectric layer 110. The second redistribution layer 130 is located on the first redistribution layer 120, and the top of the second redistribution layer 130 protrudes from the dielectric layer 110. The dielectric layer 110, the first redistribution layer 120, and the second redistribution layer 130 may be redistribution substrates. The wafer 140 is located on the front side of the dielectric layer 110 and is connected to the second redistribution layer 130 via leads 150. The molding compound layer 160 covers the wafer 140 and the leads 150. The external terminals 170 are located on the back side of the dielectric layer 110 and are connected to the first redistribution layer 120, thereby realizing external signal transmission. In this embodiment, the lead 150 is directly soldered onto the second wiring layer 130, that is, the second wiring layer 130 is used as a pad. Therefore, there is no need to set up additional pads. Since the thickness of the first wiring layer 120 and the second wiring layer 130 is relatively small, the overall thickness of the dielectric layer 110 can be reduced, thereby reducing the size of the package structure 100.

[0028] As shown in FIG2, the dielectric layer 110 may include a first dielectric layer 111, a second dielectric layer 112, a third dielectric layer 113, and a fourth dielectric layer 114 stacked in the vertical direction. The first dielectric layer 111 is located on the fourth dielectric layer 114, the second dielectric layer 112 is located on the first dielectric layer 111, and the third dielectric layer 113 is located on the second dielectric layer 112. When forming the dielectric layer 110, the first dielectric layer 111, the second dielectric layer 112, and the third dielectric layer 113 may be formed on a temporary substrate first, and then the temporary substrate may be removed, thereby forming the fourth dielectric layer 114 on the first dielectric layer 111. In the embodiments of this disclosure, the materials of the first dielectric layer 111 to the fourth dielectric layer 114 may be the same. The material of the first dielectric layer 111 can be an insulating material, such as a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), or an insulating material in which these resins are impregnated in a core material (e.g., inorganic filler and / or glass fiber (glass fiber, glass cloth, glass fabric)). The first dielectric layer 111 may also include a photosensitive resin such as a photoimageable dielectric (PID) resin.

[0029] As shown in Figure 2, the thickness of the first dielectric layer 111 is basically the same as the thickness of the second dielectric layer 112, the thickness of the second dielectric layer 112 is basically the same as the thickness of the third dielectric layer 113, and the thickness of the first dielectric layer 111 is greater than the thickness of the fourth dielectric layer 114. Since redistribution layers need to be formed in the first dielectric layer 111, the second dielectric layer 112, and the third dielectric layer 113, but not in the fourth dielectric layer 114, the thickness of the first dielectric layer 111 to the third dielectric layer 113 is relatively large. Meanwhile, since the external terminal 170 is formed after the fourth dielectric layer 114, the thickness of the fourth dielectric layer 114 is smaller, which also reduces the etching time of the fourth dielectric layer 114. In this embodiment of the present disclosure, the thickness of the fourth dielectric layer 114 can be reduced, thereby reducing the overall thickness of the dielectric layer 110, reducing the size of the external terminal 170, and thus improving the thickness of the package structure 100. The thickness of the first dielectric layer 111 can be 9-10 μm, and the thickness of the fourth dielectric layer 114 can be 4-5 μm. The thickness of the fourth dielectric layer 114 can be half the thickness of the first dielectric layer 111. If the thickness of the fourth dielectric layer 114 is close to the thickness of the first dielectric layer 111, the size of the external terminal 170 will also increase accordingly, thus increasing the overall thickness of the dielectric layer 110. If the thickness of the fourth dielectric layer 114 is too small, for example, 1-2 μm, the fourth dielectric layer 114 cannot protect the first redistribution layer 120, and it is also not conducive to the placement of the external terminal 170.

[0030] As shown in Figures 2-3, a first redistribution layer 120 is present in the dielectric layer 110. The first redistribution layer 120 may include a lower conductive pattern 121, an intermediate conductive pattern 122, and an upper conductive pattern 123. The lower conductive pattern 121 is located on the fourth dielectric layer 114. When forming the lower conductive pattern 121, the lower conductive pattern 121 is first formed on a temporary substrate, and then the first dielectric layer 111 is formed, thereby covering the lower conductive pattern 121. The lower conductive pattern 121 may extend horizontally on the fourth dielectric layer 114. An intermediate conductive pattern 122 is present on the lower conductive pattern 121, and the intermediate conductive pattern 122 may include a vertical portion 1221 and a horizontal portion 1222. The vertical portion 1221 may be located in the first dielectric layer 111, thereby being electrically connected to the lower conductive pattern 121. The horizontal portion 1222 is located on the first dielectric layer 111 and extends horizontally on the first dielectric layer 111. Meanwhile, in the vertical direction (Y direction), the thickness of the vertical portion 1221 is greater than the thickness of the horizontal portion 1222. In this embodiment, an intermediate conductive pattern 122 is formed after the first dielectric layer 111, thereby allowing the vertical portion 1221 to be formed in the first dielectric layer 111 and the horizontal portion 1222 to be formed on the first dielectric layer 111. In this embodiment, the sidewalls of the vertical portion 1221 are inclined. By increasing the thickness of the vertical portion 1221, the upper width of the vertical portion 1221 can be increased, which is beneficial for metal filling and thus increases the contact area with the horizontal portion 1222, improving signal transmission performance. In some embodiments, the first redistribution layer 120 may include ground patterns, power patterns, signal patterns, etc. The signal patterns may include various signals (such as data signals) other than ground patterns and power patterns related to power supply.

[0031] As shown in Figure 2, after forming the intermediate conductive pattern 122, a second dielectric layer 112 is first formed on the first dielectric layer 111, and then an upper conductive pattern 123 is formed in the second dielectric layer 112. The upper conductive pattern 123 is electrically connected to the intermediate conductive pattern 122. The structure of the upper conductive pattern 123 can be the same as the structure of the intermediate conductive pattern 122. Part of the upper conductive pattern 123 is located in the second dielectric layer 112, and part of the upper conductive pattern 123 is located on the second dielectric layer 112. After forming the upper conductive pattern 123, a third dielectric layer 113 is formed on the second dielectric layer 122. The third dielectric layer 113 can cover the horizontal portion of the upper conductive pattern 123. It should be noted that a seed barrier layer is also formed between the lower conductive pattern 121, the intermediate conductive pattern 122, and the upper conductive pattern 123 and the dielectric layer 110. The seed barrier layer can be titanium or tantalum.

[0032] As shown in Figures 2 and 4, after forming the third dielectric layer 113, a second redistribution layer 130 can also be formed in the third dielectric layer 113. The top of the second redistribution layer 130 protrudes beyond the top surface of the third dielectric layer 113, that is, in the vertical direction, the top of the second redistribution layer 130 is located outside the third dielectric layer 113. Since the top of the second redistribution layer 130 is located outside the third dielectric layer 113, that is, outside the dielectric layer 110, the second redistribution layer 130 can be used as a pad, and it is not necessary to form additional pads on the third dielectric layer 113.

[0033] As shown in Figures 2 and 4, the second redistribution layer 130 may include a main body 131 and an extension 132. The main body 131 may be located in the third dielectric layer 113, and the extension 132 may be located on the main body 131 and extend into the third dielectric layer 113, that is, the extension 132 is located on the third dielectric layer 113. The extension 132 may be the top of the second redistribution layer 130. In the vertical direction, the thickness of the extension 132 is less than the thickness of the main body 131. Since wiring is required on the second redistribution layer 130, the top of the second redistribution layer 130 needs to be lower than the wafer 140, thus forming a thinner extension 132. Of course, the second redistribution layer 130 may also include a metal layer 133, which is located on the extension 132 and conformally on the extension 132. Conformal growth can be understood as the metal layer 133 continuing the growth of the top surface of the extension 132. For example, if the top surface of the extension 132 is horizontal, then the top surface of the metal layer 133 is also horizontal; conversely, if the top surface of the extension 132 is inclined, then the top surface of the metal layer 133 is also inclined. A lead 140 can be connected to the metal layer 133. It should be noted that there is a seed barrier layer between the main body 131 and the dielectric layer 110, and similarly, there is a seed barrier layer between the extension 132 and the dielectric layer 110.

[0034] As shown in Figures 2 and 4, the metal layer 133 is located only on the top surface of the extension 132, that is, the metal layer 133 is not on the sidewall of the extension 132. Since there are a large number of second wiring layers 130 on the dielectric layer 110, and these second wiring layers 130 are arranged regularly, and since the metal layer 133 is located only on the top surface of the extension 132, the spacing between adjacent second wiring layers 130 can be appropriately reduced, thereby increasing the number of second wiring layers 130, and thus providing better signal transmission for the chip.

[0035] As shown in Figures 2 and 4, the main body 131 and the extension 132 are made of the same material, while the extension 132 and the metal layer 133 are made of different materials. Since the lead 150 is connected to the metal layer 133, the metal layer 133 and the lead 150 are made of the same material. Simultaneously, the main body 131 is electrically connected to the upper conductive pattern 123, but the main body 131 and the upper conductive pattern 123 are made of different materials. The hardness of both the main body 131 and the extension 132 can be greater than the hardness of the upper conductive pattern 123. After connecting the lead 150 to the metal layer 133, the endpoint of the lead 150 needs to be cut off with a chopping tool. The chopping tool will apply force to the main body 131; therefore, the main body 131 and the extension 132 need higher hardness to prevent deformation of the main body 131. In this embodiment, the material of the main body 131 can be nickel or titanium, the material of the upper conductive pattern 123 can be copper or aluminum, and the material of the metal layer 133 can be gold.

[0036] As shown in Figures 1 and 5, a chip 140 is disposed on the front side of the dielectric layer 110, and the chip 140 is connected to the second redistribution layer 130 via leads 150. The number of chips 140 can be multiple, for example, two, four, eight, or more. The chip 140 can be a logic chip or a memory chip. Logic chips can include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), a digital signal processor (DSP), a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc. Memory chips can include, for example, volatile memory devices (such as dynamic random access memory (DRAM) or static RAM (SRAM)) or non-volatile memory devices (such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or flash memory). In this embodiment, four chips 140 are disposed, namely, the first chip 141 to the fourth chip 144. The first chip 141 to the fourth chip 144 are stacked sequentially. A first wafer 141 is located on a third dielectric layer 113. A second wafer 142 is offset and disposed on the first wafer 142, a third wafer 143 is offset and disposed on the second wafer 142, and a fourth wafer 144 is offset and disposed on the third wafer 143. The offset directions of the second wafer 142 and the third wafer 143 are the same, for example, offset to the right in Figure 5. The offset direction of the fourth wafer 141 is opposite to the offset direction of the third wafer 143, for example, offset to the left in Figure 5. The first wafer 141 and the second wafer 142 are connected by a lead 150. The first wafer 141 is connected to a second redistribution layer 130 by a lead 150. The fourth wafer 144 is connected to the third wafer 143 by a lead 150. The third wafer 143 is connected to the second redistribution layer 130 by a lead 150. Since the first wafer 141 to the fourth wafer 144 are wafers of the same specification, such as DRAM wafers of the same model, the length of the lead 150 from the second wafer 142 to the first wafer 141 is the same as the length of the lead 150 from the fourth wafer 144 to the third wafer 143. The distance from the first wafer 141 to the third dielectric layer 113 can be the thickness of the first wafer 141, and the distance from the third wafer 143 to the third dielectric layer 113 can be the sum of the thicknesses of the first wafer 141 to the third wafer 143. Therefore, the first wafer 141 is lower than the third wafer 143, and thus the length of the lead 150 from the first wafer 141 to the second redistribution layer 130 is less than the length of the lead 150 from the third wafer 143 to the second redistribution layer 130. As a result, there will be a time difference in signal transmission on the first wafer 141 and the third wafer 143, leading to inconsistent signal transmission.In this embodiment, the first distance d1 from the second redistribution layer 130 on the left to the first wafer 141 is greater than the second distance d2 from the second redistribution layer 130 on the right to the third wafer 143, thereby reducing the length difference of the leads 150 on the left and right sides, and thus reducing the signal transmission time difference. In this embodiment, the second distance d2 from the second redistribution layer 130 on the right to the third wafer 143 can be 240-250 μm, and the first distance d1 from the second redistribution layer 130 on the left to the first wafer 141 can be 300-350 μm. That is, the difference between the first distance d1 and the second distance d2 is essentially equal to the sum of the thicknesses of the second wafer 142 and the third wafer 143.

[0037] As shown in FIG. 5, after the lead 150 is completed, a molding compound 160 may be formed on the third dielectric layer 113. The molding compound 160 covers the first wafer 141 to the fourth wafer 144 and also covers the lead 150. The molding compound 160 can protect the wafer 140. The molding compound 160 may include an insulating material. Examples of insulating materials may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or prepregs including inorganic fillers and / or glass fibers, Ajinomoto composite film (ABF), FR-4, bismaleimide triazine (BT), epoxy molding compound (EMC), etc.

[0038] As shown in Figures 2 and 5, after forming the molding compound 160, a temporary substrate is provided on the surface of the molding compound 160. The temporary substrate is then flipped, allowing a fourth dielectric layer 114 to be formed on the first dielectric layer 111. A portion of the fourth dielectric layer 114 is then etched, thereby forming an external terminal 170 within the fourth dielectric layer 114. The external terminal 170 can be electrically connected to the lower conductive pattern 121, thereby enabling signal transmission. The external terminal 170 can be a solder ball or a bump.

[0039] As shown in Figure 1, in this embodiment of the present disclosure, when forming the second wiring layer 130, the wafer 140 and the second wiring layer 130 are connected by leads 150, instead of using solder balls to fix the wafer 140 onto the second wiring layer 130. When using solder balls to fix the wafer 140, during molding, the molding material needs to enter between the wafer 140 and the dielectric layer 110. As the density of solder balls increases and the size of solder balls decreases, it becomes difficult for the molding material to enter between the wafer 140 and the dielectric layer 110, and gaps are easily formed in the molding layer 160, leading to a decrease in the performance of the molding layer 160. At the same time, solder balls have a certain height, and using solder balls to fix the wafer 140 increases the overall height of the package structure 100. In this embodiment, the wafer 140 is bonded to the dielectric layer 110, and then the wafer and the second wiring layer 130 are connected by leads 150. The molding layer 160 can completely cover the wafer 140, and at the same time, the overall height of the package structure 100 can be reduced. At the same time, the overall thickness of the dielectric layer 110 is reduced, thereby reducing the overall thickness of the packaging structure.

[0040] As shown in Figure 1, in this embodiment of the present disclosure, the top of the second wiring layer 130 is outside the dielectric layer 110, and the lead 150 can be directly connected to the second wiring layer 130. If the top of the second wiring layer 130 is inside the dielectric layer 110, that is, the second wiring layer 130 is lower than the dielectric layer 110, the portion of the dielectric layer 110 protruding from the second wiring layer 130 may affect the bonding process of the lead 150. Simultaneously, when the lead 150 is wired onto the second wiring layer 130, the length of the lead 150 will also be extended. During the subsequent molding process, the molding compound needs to be filled into the dielectric layer 110, which will cause the lead 150 to wobble, reducing the stability of the lead 150. In this embodiment of the present disclosure, the top of the second wiring layer 130 is outside the dielectric layer 110, and the second wiring layer 130 will not obstruct the wire bonding process. Since the present embodiment can also reduce the length of the lead 150, the second rewiring layer 130 will also slow down the flow rate of the molding compound, reduce the impact on the lead 150, and improve the stability of the lead 150.

[0041] As shown in Figure 2, in this embodiment of the present disclosure, a first dielectric layer 111, a second dielectric layer 112, and a third dielectric layer 113 are formed through multiple deposition processes. The deposition process can improve the precision of the first dielectric layer 111 to the third dielectric layer 113, reduce the thickness of the first dielectric layer 111 to the third dielectric layer 113, and thus reduce the thickness of the dielectric layer 110, thereby reducing the thickness of the encapsulation structure 100. This embodiment of the present disclosure does not use an organic substrate. An organic substrate requires multiple organic sub-substrates to be stacked, and then conductive lines are formed by drilling. Therefore, the thickness of the organic substrate is relatively large, which is not conducive to reducing the thickness of the encapsulation structure 100.

[0042] As shown in FIG6, this embodiment of the present disclosure proposes another packaging structure 100. The difference between this packaging structure 100 and FIG1 is that the structure of the second redistribution layer 130 in FIG6 is different from the structure of the second redistribution layer 130 in FIG1. ​​The structures of the dielectric layer 110, the first redistribution layer 120, the wafer 140, the lead 150, the molding layer 160, and the external terminal 170 in FIG6 can be referred to the above description. Here, the structure of the second redistribution layer 130 is described in detail.

[0043] As shown in Figures 7 and 8, the second redistribution layer 130 includes a main body 131, an extension 132, and a metal layer 133. The main body 131 is located in the third dielectric layer 113, and the extension 132 is located on the main body 131 and extends onto the third dielectric layer 113. The top surface of the extension 132 is inclined, and the metal layer 133 is conformally formed on the extension 132, so that the top surface of the metal layer 133 is also inclined. As can be seen from Figure 8, in the vertical direction, the end of the extension 132 near the wafer 140 has a larger thickness, and the end of the extension 132 away from the wafer 140 has a smaller thickness. The maximum thickness of the extension 132 is less than the thickness of the main body 131. The maximum thickness of the extension 132 is much smaller than the thickness of the wafer 140. In this embodiment, the maximum thickness of the extension 132 is approximately 1 / 10 of the thickness of the wafer 140. If the maximum thickness of the extension 132 is too large, it will be detrimental to the wire bonding process of the lead 150. As can be seen from Figure 8, the top surface 1331 of the metal layer 133 is inclined, that is, the top surface 1331 is inclined relative to the surface of the third dielectric layer 113. Therefore, the angle between the top surface 1331 and the third dielectric layer 113 can be angle b. The end of the lead 150 is on the top surface 1331, so there is an angle between the lead 150 and the top surface 1331, that is, angle α. The angle between the lead 150 and the top surface 1331 can be understood as the angle between the tangent of the lead 150 and the top surface 1331. In this embodiment, angle α can be greater than angle b, that is, the top surface 1331 is relatively flat, that is, the top surface of the extension 132 is relatively flat. Therefore, the thickness of the end of the extension 132 near the wafer 140 is smaller, which is beneficial for wire bonding. During wire bonding, to ensure the lead wire 150 has a good curvature and good stability, the angle α should be relatively large, thus angle α can be greater than angle β. Simultaneously, when the end of the lead wire 150 is led onto the metal layer 133, a wedge is used to press the lead wire 150 together. Since the bottom of the wedge is curved, by setting a gentle top surface 1331, the cut surface of the bottom of the wedge is basically parallel to the top surface 1331. When the wedge presses and cuts, it can ensure that the lead wire 150 is under overall pressure, improving the uniformity and stability of the lead wire pressing and forming, thereby improving the stability of the lead wire 150. In this embodiment, the angle β can be between 8-10°, for example, 9°, and the angle α can be between 15-20°, for example, 16° or 17°.

[0044] As shown in Figures 7-8, in this embodiment of the present disclosure, the thickness of the end of the extension 132 near the wafer 140 is greater than the thickness of the end of the extension 132 away from the wafer 140, which is beneficial to the bonding process of the lead 150. If the thickness of the end of the extension 132 near the wafer 140 is less than the thickness of the end of the extension 132 away from the wafer 140, the angle α between the lead 150 and the top surface 1331 becomes larger, and the bottom surface of the cleaver cannot be well matched to the lead 150, which is not conducive to the bonding process of the lead 150 and not conducive to the formation of a stable lead 150.

[0045] As shown in Figures 7-8, in this embodiment of the present disclosure, by forming an inclined extension 132 and then forming an inclined metal layer 133, the stability of the lead 150 can be improved during the pressing process of the lead 150.

[0046] As shown in Figure 9, (a) is a simplified schematic diagram of the extension 132, and (b) is a simplified schematic diagram of the vertical portion 1221. The top surface 1321 of the extension 132 is inclined, and the sidewall 1221a of the vertical portion 1221 is also inclined. The top surface 1321 of the extension 132 can facilitate the stability of the lead wire 150, and the sidewall 1221a of the vertical portion 1221 can facilitate metal filling. At the same time, the sidewall 1221a of the extension 132 has a first slope, and the top surface 1321 of the extension 132 has a second slope, the absolute value of the first slope being greater than the absolute value of the second slope. The angle of the first slope is less than 90°. If the absolute value of the first slope is less than the absolute value of the second slope, that is, the angle of the second slope is larger, then the top surface 1321 becomes steep, which is detrimental to the formation process of the lead wire 150.

[0047] As shown in FIG. 10, this embodiment of the present disclosure also proposes another second redistribution layer 130, in which no metal layer is shown. The second redistribution layer 130 includes a main body portion 131 and an extension portion 132. The extension portion 132 is located on the main body portion 131. The extension portion 132 has an inclined slope. In the vertical direction, the end of the extension portion 132 near the wafer 140 has a larger thickness, and the end of the extension portion 132 away from the wafer 140 has a smaller thickness. The center line S2 of the extension portion 132 deviates from the center line S1 of the main body portion 131, and the center line S2 of the extension portion 132 is closer to the wafer 140, that is, the center line S2 of the extension portion 132 is offset towards the wafer 140. As can be seen from FIG. 10, the distance from the right end of the extension portion 132 to the main body portion 131 is greater than the distance from the left end of the extension portion 132 to the main body portion 131. Since the thicker end of the extension 132 is closer to the wafer 140, it is beneficial to the wire bonding process of the wafer 140, and improves the stability and uniformity of the wires.

[0048] As shown in FIG11, this embodiment of the present disclosure also proposes another second redistribution layer 130. The second redistribution layer 130 may include a main body portion 131, an extension portion 132, and a recessed portion 134. Since an opening is formed in the third dielectric layer 113, during the electroplating process, metal material is grown simultaneously on the inner wall of the opening and the top surface of the third dielectric layer 113, and since the opening has a certain depth, during the electroplating process, the electroplating solution inside the opening is not updated in time, and metal ions cannot be deposited inside the opening in time. Therefore, the growth rate of the metal layer inside the opening is slow, so a recessed portion 134 is formed in the extension portion 132 and the main body portion 131, that is, the recessed portion 134 is located in the extension portion 132 and the main body portion 131, that is, it extends from the extension portion 132 to the main body portion 131. The main body portion 131 is still located in the third dielectric layer 113, and the extension portion 132 is located on the top surface of the third dielectric layer 113, that is, the extension portion 132 protrudes from the third dielectric layer 113. The presence of the recess 134 hinders the wiring process. Therefore, in this embodiment, a gold ball 135 is formed within the recess 134, allowing the gold ball 135 to be considered part of the second redistribution layer 130, meaning the second redistribution layer 130 includes the gold ball 135. The gold ball 135 can contact the sidewalls and bottom surface of the recess 134. The gold ball 135 is located within the recess 134, with a gap between it and the sidewalls. In some embodiments, the bottom of the gold ball 135 can deform, eliminating the gap between it and the sidewalls, thus increasing the contact area. Simultaneously, the top surface of the gold ball 135 is higher than the top surface of the extension 132, meaning the height of the gold ball 135 is greater than the depth of the recess 134. Because the gold ball 135 is taller, the lead wire 150 can be directly pressed onto the gold ball 135. Since both are made of the same material, the bonding strength is high, which is beneficial for the wire bonding process. Simultaneously, pressing the lead wire 150 onto the gold ball 135 also increases the bonding strength between the gold ball 135 and the recess 134. In some embodiments, the height of the gold ball 135 can be 2µm greater than the depth of the recess 134. For example, the height of the gold ball 135 is 8-10µm, and the depth of the recess 134 is 6-8µm.

[0049] As shown in FIG12, this disclosure provides an encapsulation device 10, which may include a substrate 200 and an encapsulation structure 100. The substrate 200 is, for example, a PCB, a flexible substrate, or a strip substrate, and the encapsulation structure 100 may refer to the above-described structure. The encapsulation structure 100 can be applied to electronic devices. The electronic devices may include one or more of the following: for example, smartphones, tablet PCs, mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable multimedia players (PMPs), MPEG-1 audio layer 3 (MP3) players, mobile medical devices, cameras, home appliances, medical devices, Internet of Things (IoT) devices, and wearable devices. Wearable devices may be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices may be, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted devices (HMDs).

[0050] In summary, the embodiments of this disclosure provide a packaging structure and packaging device that supports the wafer by using a thinner redistribution substrate, thereby reducing the thickness of the packaging structure. Simultaneously, since the top of the second redistribution layer protrudes from the dielectric layer, it facilitates direct connection of leads to the second redistribution layer, which is beneficial for the lead formation process.

[0051] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of protection of the claims. [Simplified Explanation of the Diagram]

[0018] FIG1 is a schematic diagram of a packaging structure according to an exemplary embodiment; FIG2 is a schematic diagram of a dielectric layer according to an exemplary embodiment; FIG3 is a schematic diagram of an intermediate conductive pattern according to an exemplary embodiment; FIG4 is a schematic diagram of a second redistribution layer according to an exemplary embodiment; FIG5 is a schematic diagram of a wafer stack according to an exemplary embodiment; FIG6 is a schematic diagram of another packaging structure according to an exemplary embodiment; FIG7 is another schematic diagram of a second redistribution layer according to an exemplary embodiment; FIG8 is an enlarged view of the dashed frame in FIG7 according to an exemplary embodiment; FIG9 is a schematic diagram of an extension and a vertical portion according to an exemplary embodiment; FIG10 is another schematic diagram of a second redistribution layer according to an exemplary embodiment; FIG11 is another schematic diagram of a second redistribution layer according to an exemplary embodiment; FIG12 is a schematic diagram of a packaging device according to an exemplary embodiment.

Claims

1. A packaging structure, comprising: Dielectric layer; The first wiring layer is located in the dielectric layer; A second wiring layer is located on top of the first wiring layer, and the first wiring layer and the second wiring layer are electrically connected. The top of the second wiring layer protrudes from the dielectric layer. A wafer is located on the dielectric layer. A lead is provided to connect the wafer and the second redistribution layer. The second redistribution layer includes: a main body located in the dielectric layer; an extension located on the main body and extending to the top surface of the dielectric layer; the thickness of the extension near the wafer is greater than the thickness of the extension away from the wafer; wherein, in the vertical direction, the thickness of the main body is greater than the thickness of the extension; wherein, in the horizontal direction, there is an angle between the top surface of the extension and the top surface of the dielectric layer.

2. The encapsulation structure as described in claim 1, wherein, The centerline of the extension is offset from the centerline of the main body, and the centerline of the extension is shifted toward the wafer.

3. The encapsulation structure as described in claim 1 or 2, wherein, The second redistribution layer further includes: a metal layer conformally disposed on the extension; wherein the thickness of the metal layer is less than the thickness of the extension; wherein the lead is connected to the metal layer, and the angle between the metal layer and the lead is greater than the angle between the top surface of the metal layer and the top surface of the dielectric layer.

4. The encapsulation structure as described in claim 1, wherein, The first redistribution layer includes: a lower conductive pattern located at the bottom of the dielectric layer, the lower conductive pattern extending horizontally in the dielectric layer; a middle conductive pattern located in the middle of the dielectric layer and connected to the lower conductive pattern; and an upper conductive pattern located in the upper part of the dielectric layer and connected to the middle conductive pattern; wherein the material of the main body is different from the material of the upper conductive pattern, and the hardness of the main body is greater than the hardness of the upper conductive pattern.

5. The encapsulation structure as described in claim 4, wherein, The intermediate conductive pattern includes: a vertical portion connected to the lower conductive pattern; and a horizontal portion connected to the vertical portion, extending horizontally in the dielectric layer; wherein, in the vertical direction, the thickness of the vertical portion is greater than the thickness of the horizontal portion; and wherein, in the horizontal direction, the width of the vertical portion is less than the width of the main body portion.

6. The encapsulation structure as described in claim 5, wherein, The sidewall of the vertical portion has a first slope, and the top surface of the extension portion has a second slope. The absolute value of the first slope is greater than the absolute value of the second slope. The main body portion is connected to the upper conductive pattern, and the thickness of the main body portion is greater than the thickness of the horizontal portion.

7. The encapsulation structure as described in any one of claims 1 to 2, wherein, The second redistribution layer is located on both sides of the wafer, and the spacing between the second redistribution layer on both sides and the wafer is different.

8. The encapsulation structure as described in claim 1, wherein, The second redistribution layer further includes: a recess extending from the extension to the main body; a gold ball located in the recess, with the lead wire connected to the gold ball; wherein the height of the gold ball is greater than the depth of the recess.

9. A packaged device, comprising: substrate; The packaging structure as described in any one of claims 1 to 8 is disposed on the substrate.

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