Multistable Display

Abstract

This invention is a multistable display, comprising a timing control circuit unit, a driving circuit unit, and a panel unit. The timing control circuit unit generates timing control signals. The driving circuit unit stores a voltage configuration truth table. The first data signal of the timing control signal sequentially includes header setting data and voltage waveform data. The driving circuit unit sets the voltage configuration truth table according to the header setting data. Furthermore, the driving circuit unit determines the driving voltage waveform output to the panel unit based on the voltage waveform data and the voltage configuration truth table. Since the voltage waveform data only needs to transmit 1 bit of data, only a smaller number of bits are needed to achieve the same amount of data transmission. Therefore, under the condition of transmitting the same total amount of data in the same amount of time, a lower clock frequency can be used, thereby reducing power consumption.

Claims

1. A multistable display, comprising: a timing control circuit unit for generating a timing control signal; a driving circuit unit for storing a voltage configuration truth table, connected to the timing control circuit unit, and receiving the timing control signal; and a panel unit connected to the driving circuit unit; wherein, The timing control signal includes a first data signal, and the first data signal sequentially includes at least one header setting data and at least one voltage waveform data; wherein, when the drive circuit unit receives the header setting data, the drive circuit unit sets the voltage configuration truth table according to the header setting data; wherein, when the drive circuit unit receives the voltage waveform data, the drive circuit unit determines a drive voltage waveform to be output to the panel unit according to the voltage waveform data and the voltage configuration truth table; wherein, the at least one header setting data includes a white-brush header setting data and a content header setting data, and the at least one voltage waveform data includes a white-brush voltage waveform data and a content voltage waveform data; wherein, the first data signal is composed of the white-brush header setting data, the white-brush voltage waveform data, the content header setting data, and the content voltage waveform data arranged sequentially.

2. The multistable display as described in claim 1, wherein, The first data signal also includes a duration data in sequence, and the duration data is between the brush voltage waveform data and the content header setting data.

3. The multistable display as described in claim 1, wherein, The timing control circuit unit includes: a header setting control terminal, connected to the drive circuit unit, which outputs a header setting signal to the drive circuit unit; a voltage positive / negative control terminal, connected to the drive circuit unit, which outputs a positive / negative signal to the drive circuit unit; and a first data output terminal, connected to the drive circuit unit, which outputs the first data signal to the drive circuit unit; wherein, when the first data signal output by the first data output terminal is the white header setting data, the header setting signal output by the header setting control terminal is a high voltage level.

4. The multistable display as described in claim 3, wherein, The brush white voltage waveform data sequentially includes a positive brush white voltage waveform data and a negative brush white voltage waveform data; wherein, when the first data signal output by the first data output terminal is the positive brush white voltage waveform data, the header setting signal output by the header setting control terminal is a low voltage level, and the positive and negative signals output by the voltage positive and negative control terminal are the high voltage level.

5. The multistable display as described in claim 4, wherein, When the first data signal output by the first data output terminal is the negative brush white voltage waveform data, the header setting signal output by the header setting control terminal is the low voltage level, and the positive and negative signals output by the voltage positive and negative control terminal are the low voltage level.

6. The multistable display as described in claim 3, wherein, When the first data signal output by the first data output terminal is the content header setting data, the header setting signal output by the header setting control terminal is the high voltage level.

7. The multistable display as described in claim 6, wherein, The content voltage waveform data sequentially includes a positive content voltage waveform data and a negative content voltage waveform data; wherein, when the first data signal output by the first data output terminal is the positive content voltage waveform data, the header setting signal output by the header setting control terminal is a low voltage level, and the positive and negative signals output by the voltage positive and negative control terminal are the high voltage level.

8. The multistable display as described in claim 7, wherein, When the first data signal output by the first data output terminal is the negative content voltage waveform data, the header setting signal output by the header setting control terminal is the low voltage level, and the positive and negative signals output by the voltage positive and negative control terminal are the low voltage level.

9. The multistable display as claimed in claim 3, wherein, The voltage configuration truth table takes the first data signal output from the first data output terminal and the positive and negative signals output from the voltage positive and negative control terminal as inputs; wherein, when the drive circuit unit sets the voltage configuration truth table according to the header setting data, the header setting data is set as the output of the voltage configuration truth table.

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