Diode formation with backside power delivery network

Abstract

The present invention provides a semiconductor device including a diode, the diode including: a first front contact located above a first source / drain region; a first back contact; and a first reserved position connected to a bottom surface of one of the first source / drain regions.

Description

Technical Field

[0001] This disclosure is generally related to transistors, and more particularly to diode devices having back contact elements integrated with the transistor and methods for manufacturing the same. Prior Technology

[0002] In integrated circuits (ICs) incorporating transistors and electrostatic discharge (ESD) diodes, transistors are used to perform active functions such as signal amplification and logic operations. ESD diodes are protective devices used in semiconductor and electronic circuits to expel harmful electrostatic discharge from sensitive components. ESD diodes provide a low-resistance path from circuit nodes to ground or power rails to safely dissipate static charge and prevent voltage surges from reaching critical components. ESD diodes are designed to switch on and conduct extremely quickly during rapid voltage surges, clamping the voltage to a safe level before damage occurs. Summary of the Invention

[0003] According to one embodiment, a semiconductor device includes a diode, the diode comprising: a first front contact located above a first source / drain region; a first back contact; and a first reserved location connected to a bottom surface of one of the first source / drain regions.

[0004] In some embodiments that can be combined with previous embodiments, the semiconductor device includes a transistor comprising: a second front contact located above a second source / drain region; a second back contact; and a second reserved location connected to a bottom surface of one of the second source / drain regions.

[0005] In some embodiments that can be combined with one or more prior embodiments, the diode is an electrostatic discharge (ESD) diode.

[0006] In some embodiments that can be combined with one or more prior embodiments, the transistor includes a plurality of nanoplate gates.

[0007] In some embodiments that can be combined with one or more prior embodiments, the diode further includes: a third source / drain region; and alternating layers of silicon and silicon-germanium extending horizontally between the first source / drain region and the third source / drain region.

[0008] In some embodiments that can be combined with one or more prior embodiments, the first source / drain region is an N-type source-drain region and the third source / drain region is a P-type source / drain region, or the first source / drain region is a P-type source-drain region and the third source / drain region is an N-type source / drain region.

[0009] In some embodiments that can be combined with one or more prior embodiments, the diode includes: shallow trench isolation (STI); one or more additional reserved locations; and a protective liner located above the STI, the one or more additional reserved locations, and portions of the diode that do not directly contact the first source / drain region and the third source / drain region.

[0010] In some embodiments that can be combined with one or more prior embodiments, the protective liner is made of silicon nitride.

[0011] In some embodiments that can be combined with one or more prior embodiments, the diode is adjacent to the transistor, and the diode and the transistor are separated by an internal spacer via a dummy gate.

[0012] According to one embodiment, a semiconductor device includes: a diode including a first front contact located above a first source / drain region and a first reserved position connected to a bottom surface of the first source / drain region; and a logic device including a logic back contact and a logic front contact.

[0013] In some embodiments that can be combined with previous embodiments, the diode is an electrostatic discharge (ESD) diode, and the logic device is a nanosheet transistor.

[0014] In some embodiments that can be combined with one or more prior embodiments, the diode includes: a second source / drain region; and alternating layers of silicon and silicon-germanium extending horizontally between the first source / drain region and the second source / drain region.

[0015] In some embodiments that can be combined with one or more prior embodiments, the first source / drain region is an N-type source-drain region and the second source / drain region is a P-type source / drain region, or the first source / drain region is a P-type source-drain region and the second source / drain region is an N-type source / drain region.

[0016] In some embodiments that can be combined with one or more prior embodiments, the diode includes: shallow trench isolation (STI); one or more additional reserved locations; and a protective liner located above the STI, the one or more additional reserved locations, and portions of the diode that do not directly contact the first source / drain region and the second source / drain region.

[0017] In some embodiments that can be combined with one or more prior embodiments, the diode is adjacent to the logic device, and the diode and the logic device are separated by an internal spacer via a dummy gate.

[0018] According to one embodiment, a method for forming a semiconductor device includes forming a diode, comprising: forming a first source / drain region; forming a first front contact over the first source / drain region; forming a first back contact; and forming a reserved position at a bottom surface of one of the first source / drain regions.

[0019] In some embodiments that can be combined with previous embodiments, the method includes forming a transistor, which includes: forming a second source / drain region; forming a second front contact over the second source / drain region; forming a second back contact; and forming a second reserved position at one bottom surface of the second source / drain region.

[0020] In some embodiments that can be combined with one or more prior embodiments, the method includes forming a plurality of nanosheet gates extending horizontally along a gate channel.

[0021] In some embodiments that can be combined with one or more prior embodiments, the method includes: forming a third source / drain region; and forming alternating layers of silicon and silicon-germanium extending horizontally between the first source / drain region and the third source / drain region.

[0022] In some embodiments that can be combined with one or more prior embodiments, the method includes: forming a shallow trench isolation (STI); forming one or more additional reserved locations; and forming a protective liner over the STI, the one or more additional reserved locations, and portions of the diode that are not in direct contact with the first source / drain region and the third source / drain region.

[0023] In some embodiments that can be combined with one or more prior embodiments, the method includes using an internal spacer to isolate the diode and the transistor by means of a dummy gate.

[0024] According to one embodiment, a method for forming a semiconductor device includes: forming a diode, which includes forming a first source / drain region, forming a first front contact above the first source / drain region, and forming a first reserved position connected to a bottom surface of the first source / drain region; and forming a logic device, which includes forming a logic back contact and forming a logic front contact.

[0025] In some embodiments that can be combined with previous embodiments, the method includes: forming a second source / drain region; and forming an alternating layer of silicon and silicon-germanium extending horizontally between the first source / drain region and the second source / drain region.

[0026] In some embodiments that can be combined with one or more prior embodiments, the method includes: forming a shallow trench isolation (STI); forming one or more additional reserved locations; and forming a protective liner over the STI, the one or more additional reserved locations, and portions of the diode that are not in direct contact with the first source / drain region and the second source / drain region.

[0027] In some embodiments that can be combined with one or more prior embodiments, the method includes using an internal spacer to isolate the diode and the logic device by means of a dummy gate.

[0028] These and other features will become apparent from the following illustrative embodiments, which will be read in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0029] The drawings are illustrative embodiments. They do not depict all embodiments. Other embodiments may be used alternatively or as alternatives. Details that may be obvious or unnecessary may be omitted to save space or for more efficient illustration. Some embodiments may be practiced with additional components or steps and / or without all the components or steps shown. When the same numbers appear in different drawings, they refer to the same or similar components or steps.

[0030] Figures 1A to 1D illustrate semiconductor devices according to some embodiments.

[0031] Figure 1E shows a top view depicting the cross-section of the semiconductor shown in each figure.

[0032] Figures 2A to 2D illustrate side views of a semiconductor device after patterning of a nanosheet according to some embodiments.

[0033] Figures 3A to 3D illustrate side views of a semiconductor device after a nanosheet is recessed, according to some embodiments.

[0034] Figures 4A to 4D illustrate side views of a semiconductor device after the silicon-germanium layer has been pressed in, according to some embodiments.

[0035] Figures 5A to 5D illustrate side views of a semiconductor device after the formation of internal spacers according to some embodiments.

[0036] Figures 6A to 6D illustrate side views of a semiconductor device after the formation of a reserved position according to some embodiments.

[0037] Figures 7A to 7D illustrate side views of a semiconductor device after the formation of the source / drain regions according to some embodiments.

[0038] Figures 8A to 8D illustrate side views of a semiconductor device after the formation of an interlayer dielectric, according to some embodiments.

[0039] Figures 9A to 9D illustrate side views of a semiconductor device after the removal of a dummy gate, according to some embodiments.

[0040] Figures 10A to 10D illustrate side views of a semiconductor device after the removal of the silicon-germanium layer according to some embodiments.

[0041] Figures 11A to 11D illustrate side views of a semiconductor device after metallization of the gate channel according to some embodiments.

[0042] Figures 12A to 12D illustrate side views of a semiconductor device after the substrate has been removed, according to some embodiments.

[0043] Figures 13A to 13D illustrate side views of a semiconductor device after the removal of the silicon-germanium layer according to some embodiments.

[0044] Figures 14A to 14D illustrate side views of a semiconductor device after the formation of an interlayer dielectric on the back side, according to some embodiments.

[0045] Figures 15A to 15D illustrate side views of a semiconductor device after patterning of the back contact according to some embodiments.

[0046] Figures 16A to 16D illustrate side views of a semiconductor device after metallization of the back contact according to some embodiments.

[0047] Figures 17A to 17D illustrate side views of a semiconductor device after the formation of the back metal contacts according to some embodiments.

[0048] Figure 18 illustrates a block diagram of a method for forming a semiconductor device according to some embodiments. Implementation

[0049] Overview In the following embodiments, numerous specific details are illustrated with examples to provide a thorough understanding of the relevant teachings. However, it will be apparent that the teachings of the invention can be practiced without such details. In other instances, well-known methods, procedures, components, and / or circuit systems have been described at a relatively high level without detail to avoid unnecessarily obscuring the nature of the teachings of the invention.

[0050] In one embodiment, spatially relative terms such as "front," "rear," "top," "bottom," "below," "under," "lower," "above," "upper," "side," "left," "right," and the like are used with reference to the orientation of the described diagrams. Because the components of the embodiments disclosed herein can be positioned in multiple different orientations, the directional terms are used for illustrative purposes and are by no means limiting. Therefore, it will be understood that, in addition to the orientations depicted in the diagrams, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the diagrams is flipped, an element described as "below" or "under" other elements or features will then be oriented "above" other elements or features. Thus, for example, the term "below" can cover both above and below orientations. The device can be oriented in other ways (rotated 90 degrees or viewed or referenced in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0051] As used herein, the terms "lateral" and "horizontal" describe orientation parallel to the first surface of the wafer.

[0052] As used herein, the term "vertical" describes an orientation that is perpendicular to the first surface configuration of a wafer, wafer carrier, or semiconductor body.

[0053] As used herein, the terms “coupled” and / or “electrically coupled” do not imply that elements must be directly coupled together—an intervention element may be provided between “coupled” or “electrically coupled” elements. In contrast, if an element is described as “directly connected” or “directly coupled” to another element, then there is no intervention element. The term “electrically connected” refers to a low-ohmic electrical connection between elements that are electrically connected together.

[0054] Although the terms first, second, etc., may be used herein to describe various elements, such elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0055] This document describes exemplary embodiments with reference to cross-sectional views as schematic illustrations of idealized or simplified embodiments (and intermediate structures). Therefore, variations from the illustrated shapes are expected due to, for example, manufacturing techniques and / or tolerances. Consequently, the areas depicted in the figures are schematic in nature, and their shapes do not necessarily represent the actual shapes of areas of the device and are not limiting.

[0056] It should be understood that other embodiments may be used, and structural or logical changes may be made, without departing from the spirit and scope defined by the claims. The description of the embodiments is not restrictive. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0057] According to one embodiment, a semiconductor device includes a diode comprising: a first front contact located above a first source / drain region; a first back contact; and a first reserved location connected to the bottom surface of the first source / drain region. The diode eliminates the need for any remaining substrate for integration with the back contact of a logic device.

[0058] In some embodiments that can be combined with previous embodiments, the semiconductor device includes a transistor comprising: a second front contact located above the second source / drain region; a second back contact; and a second reserved location connected to the bottom surface of the second source / drain region. Therefore, the semiconductor device may include a diode and a transistor integrated on the same wafer.

[0059] In some embodiments that can be combined with one or more prior embodiments, the diode is an electrostatic discharge (ESD) diode. Therefore, a semiconductor device may include an ESD diode and a transistor integrated on the same wafer.

[0060] In some embodiments that can be combined with one or more prior embodiments, the transistor includes a plurality of nanoplate gates. Therefore, the semiconductor device is suitable for nanoplate transistors integrated with diodes on the same wafer.

[0061] In some embodiments that can be combined with one or more prior embodiments, the diode further includes: a third source / drain region; and alternating layers of silicon and silicon-germanium extending horizontally between the first source / drain region and the third source / drain region. The presence of the alternating layers of silicon and silicon-germanium can increase the effective channel area.

[0062] In some embodiments that can be combined with one or more prior embodiments, the first source / drain region is an N-type source-drain region and the third source / drain region is a P-type source / drain region, or the first source / drain region is a P-type source-drain region and the third source / drain region is an N-type source / drain region. Therefore, the diode includes opposing doped sides that facilitate diode operation.

[0063] In some embodiments that can be combined with one or more prior embodiments, the diode includes: shallow trench isolation (STI); one or more additional reserved locations; and a protective liner located above the STI, the one or more additional reserved locations, and portions of the diode that do not directly contact the first source / drain region and the third source / drain region. The protective liner covers opposite sides of the diode, except for the locations of the first source / drain region and the third source / drain region.

[0064] In some embodiments, which can be combined with one or more prior embodiments, the protective liner is made of silicon nitride. Silicon nitride protects the underlying layer from damage during the manufacturing process.

[0065] In some embodiments that can be combined with one or more prior embodiments, the diode is adjacent to the transistor, and the diode and the transistor are separated by an internal spacer via a dummy gate. The dummy gate and the internal spacer ensure that short circuits between the diode and the transistor are avoided.

[0066] According to one embodiment, a semiconductor device includes: a diode including a first front contact located above a first source / drain region and a first reserved position connected to the bottom surface of the first source / drain region; and a logic device including a logic back contact and a logic front contact. The diode does not require any substrate for integration with the back contact of the logic device.

[0067] In some embodiments that can be combined with previous embodiments, the diode is an electrostatic discharge (ESD) diode, and the logic device is a nanoplate transistor. Therefore, a semiconductor device may include an ESD diode and a transistor integrated on the same wafer.

[0068] In some embodiments that can be combined with one or more prior embodiments, the diode includes: a second source / drain region; and alternating layers of silicon and silicon-germanium extending horizontally between the first source / drain region and the second source / drain region. The presence of the alternating layers of silicon and silicon-germanium can increase the effective channel area.

[0069] In some embodiments that can be combined with one or more prior embodiments, the first source / drain region is an N-type source-drain region and the second source / drain region is a P-type source / drain region, or the first source / drain region is a P-type source-drain region and the second source / drain region is an N-type source / drain region. Therefore, the diode includes opposing doped sides to facilitate diode operation.

[0070] In some embodiments that can be combined with one or more prior embodiments, the diode includes: shallow trench isolation (STI); one or more additional reserved locations; and a protective liner located above the STI, the one or more additional reserved locations, and portions of the diode that do not directly contact the first source / drain region and the second source / drain region. The protective liner covers opposite sides of the diode, except for the locations of the first source / drain region and the third source / drain region.

[0071] In some embodiments that can be combined with one or more prior embodiments, the diode is located adjacent to the logic device, and the diode and the logic device are separated by an internal spacer via a dummy gate. The dummy gate and the internal spacer ensure that short circuits between the diode and the transistor are avoided.

[0072] According to one embodiment, a method for forming a semiconductor device includes forming a diode, comprising: forming a first source / drain region; forming a first front contact over the first source / drain region; forming a first back contact; and forming a reserved position on the bottom surface of the first source / drain region. The diode does not require any remaining substrate for integration with the back contact of a logic device.

[0073] In some embodiments that can be combined with previous embodiments, the method includes forming a transistor, which includes: forming a second source / drain region; forming a second front contact over the second source / drain region; forming a second back contact; and forming a second reserved position at the bottom surface of the second source / drain region. Therefore, a semiconductor device may include a diode and a transistor integrated on the same wafer.

[0074] In some embodiments that can be combined with one or more prior embodiments, the method includes forming a plurality of nanoplate gates extending horizontally along a gate channel. Therefore, a semiconductor device may include diodes and nanoplate transistors integrated on the same wafer.

[0075] In some embodiments that can be combined with one or more prior embodiments, the method includes: forming a third source / drain region; and forming alternating layers of silicon and silicon-germanium extending horizontally between the first source / drain region and the third source / drain region. The presence of the alternating layers of silicon and silicon-germanium can increase the effective channel area.

[0076] In some embodiments that can be combined with one or more prior embodiments, the method includes: forming a shallow trench isolation (STI); forming one or more additional reserved locations; and forming a protective liner over the STI, the one or more additional reserved locations, and portions of the diode that are not in direct contact with the first source / drain region and the third source / drain region. The protective liner covers opposite sides of the diode, except for the locations of the first source / drain region and the third source / drain region.

[0077] In some embodiments that can be combined with one or more prior embodiments, the method includes isolating the diode and the transistor using an internal spacer via a dummy gate. The dummy gate and internal spacer ensure that short circuits between the diode and the transistor are avoided.

[0078] According to one embodiment, a method for forming a semiconductor device includes: forming a diode, which includes forming a first source / drain region, forming a first front contact over the first source / drain region, and forming a first reserved position connected to a bottom surface of the first source / drain region; and forming a logic device, which includes forming a logic back contact and forming a logic front contact. The diode does not require any remaining substrate for integration with the back contact of the logic device.

[0079] In some embodiments that can be combined with previous embodiments, the method includes: forming a second source / drain region; and forming alternating layers of silicon and silicon-germanium extending horizontally between the first source / drain region and the second source / drain region. Therefore, the semiconductor device may include diodes and transistors integrated on the same wafer.

[0080] In some embodiments that can be combined with one or more prior embodiments, the method includes: forming a shallow trench isolation (STI); forming one or more additional reserved locations; and forming a protective liner over the STI, the one or more additional reserved locations, and the portions of the diode that are not in direct contact with the first source / drain region and the second source / drain region. The protective liner covers opposite sides of the diode, except for the locations of the first source / drain region and the third source / drain region.

[0081] In some embodiments that can be combined with one or more prior embodiments, the method includes isolating the diode and the logic device using an internal spacer via a dummy gate. The dummy gate and internal spacer ensure that short circuits between the diode and the transistor are avoided.

[0082] The concepts discussed in this article pertain to electrostatic discharge (ESD) diodes, protective devices used in semiconductor and electronic circuits to expel harmful electrostatic discharge from sensitive components. ESD diodes provide a low-resistance path from circuit nodes to ground or power rails to safely dissipate static charge and prevent voltage surges from reaching critical components. Typically, ESD diodes are designed to switch on and conduct extremely quickly in the event of a rapid voltage surge, clamping the voltage to a safe level before damage occurs. Common types of ESD diodes include silicon pn junction diodes, avalanche diodes, and Schottky diodes. These diodes feature fast response times in the nanosecond range.

[0083] ESD diodes are small in size but can conduct large currents for short periods, diverting current away from components that might otherwise be damaged by a discharge event. ESD diodes shunt ESD events to ground without typically interfering with circuit operation. When no ESD event occurs, the ESD diode presents a high-impedance path to ground. ESD diodes are typically placed on the I / O pads of integrated circuits and across the power supply terminals to protect sensitive internal circuitry from electrostatic discharge events.

[0084] A semiconductor device comprising a diode and a logic device is disclosed. The semiconductor device provides back contacts and front contacts in both the logic device and the diode without requiring any residual substrate. Therefore, the back contacts are integrated with the diode and directly contact the substrate silicon material rather than through the remaining substrate material. By fabricating the diode without any residual substrate, the disclosed semiconductor device simplifies the integration process by eliminating the need for etching through or otherwise penetrating the substrate to fabricate the back contacts. Achieving such back contact integration through complete substrate removal allows for tighter integration and reduces parasitic effects originating from substrate interactions.

[0085] Therefore, the teachings herein provide methods and systems for forming semiconductor devices having diodes and logic devices. The techniques described herein can be implemented in various ways. Examples of implementation are provided below with reference to the following figures.

[0086] Example semiconductor devices with co-integrated diode and logic device structures Referring now to Figures 1A through 1D, which are simplified cross-sectional views consistent with illustrative embodiments, the semiconductor device includes a logic device 100A and a diode 100B in various embodiments. Although the logic device 100A and diode 100B are depicted separately for simplicity, it should be noted that the logic device 100A and diode 100B may be integrated adjacent to each other on the same semiconductor device. Furthermore, and to avoid crowded diagrams, the logic device 100A is shown in Figures 1A through 1B, and the diode 100B is shown separately in Figures 1C through 1D. Figure 1E shows the logic device 100C and diode 100B. Figure 1E depicts a top view of the semiconductor device, showing the different cross-sections on which the semiconductor device is based as illustrated in Figures 1A through 1D.

[0087] Referring now to Figures 1A and 1B, logic device 100A may be a transistor. The transistor depicted in Figures 1A and 1B is a nanosheet transistor. However, those skilled in the art will understand that the transistor may be any other transistor. Logic device 100A may include a first source / drain region 114A, a second source / drain region 114B, source / drain contacts CA 116, a set of nanosheets NS 118, a first back contact BSCA 126A, and a first reserved position PH 128A. Logic device 100A further includes a gate region 122, a gate contact CB 124, a shallow trench isolation STI 126, a bottom dielectric layer BILD 138, an interlayer dielectric ILD 130, spacers 132, and internal spacers 134.

[0088] Generally, the first source / drain region 114A and the second source / drain region 114B are prominent components that play a relevant role in the operation of the logic device 100A. In various embodiments, the first source / drain region 114A and the second source / drain region 114B are semiconductor materials, such as regions within the logic device 100A, through which current flows into and out of the logic device 100A. The source region is the region through which most charge carriers (e.g., electrons or holes) enter the channel of the logic device 100A and is responsible for providing the current flowing through the logic device 100A. The source region is typically doped to have an excess of charge carriers, thereby creating a region with a high carrier concentration. This abundant carrier allows for the efficient injection of electrons or holes into the channel when a voltage is applied.

[0089] On the other hand, the drain region is where most of the charge carriers leave the channel. The drain region receives current from the channel and carries charge away from the transistor. Similar to the source, the drain region is also doped to have a high carrier concentration. The doping distribution in the drain region ensures that the carrier can easily flow out of the channel and into the drain region.

[0090] In some embodiments, a first source / drain region 114A is connected to the front side of the logic device 100A via CA 116. In some embodiments, a gate region 122 is connected to the front side of the logic device 100A via CB 124. In one embodiment, a second source / drain region 114B is connected to the back side of the logic device 100A via BSCA 126A.

[0091] The CA 116, located above the first source / drain region 114A, establishes a connection between the first source / drain region 114A and the BEOL 160. The CA 116 ensures effective electrical wiring and connectivity within the logic device 100A. The fabrication of the CA 116 may involve lithography and etching processes to define the contact area. The CA 116 can be made using conductive materials such as silicate liners (e.g., Ni, Ti, NiPt), bonding metal layers (e.g., TiN), and conductive metal fillers (e.g., tungsten (W), Co, or Ru).

[0092] BSCA 126A is an area on the back of logic device 100A where electrical connections are made. By establishing electrical contacts, BSCA 126A ensures the normal operation of logic device 100A and facilitates the transmission of electrical signals.

[0093] The BSCA 126A can serve as a thermal interface between the logic device 100A and a heatsink or other cooling mechanism. By establishing direct contact with the substrate, the BSCA 126A can conduct heat away from the logic device 100A and facilitate improved heat dissipation. In some embodiments, the BSCA 126A can help mitigate parasitic effects from the logic device 100A, such as substrate coupling or substrate noise. In further embodiments, the BSCA 126A can allow for increased integration density in the logic device 100A. In one embodiment, the BSCA 126A connects (e.g., wires) the first source / drain region 114A to the BSPDN 164.

[0094] In various embodiments, the gate region 122 acts as a control element regulating the current flow through the logic device 100A. The gate region 122 may be made of a conductive material. The gate region 122 controls the current flow between the source and drain regions. In some embodiments, by applying a voltage to the gate, the conductivity of the channel region is modulated, thereby allowing the logic device 100A to allow or block current flow, which in turn enables the logic device 100A to act as an electronic switch or amplifier. The gate voltage determines whether the logic device 100A is in an "on" or "off" state. When the gate voltage is below a certain threshold value, the logic device 100A is in an "off" state, and the current flow between the source and drain is effectively blocked. On the other hand, when the gate voltage exceeds the threshold value, the logic device 100A enters an "on" state, thereby allowing current to flow through the channel region. In addition to acting as a switch, modulating the gate voltage allows the gate region 122 to control the current flowing through the channel region, thereby generating an amplified output signal.

[0095] In one embodiment, gate region 122 can implement Boolean logic operations, such as AND, OR, and NOT, by controlling current flow based on the input voltage. Multiple semiconductor devices can be interconnected to form complex logic circuits, enabling the performance of various computational tasks in digital systems. In some embodiments, gate region 122, along with other semiconductor device components, facilitates the miniaturization and integration of electronic circuits. The ability to control the conductivity of the channel region via gate voltage allows for compact and efficient circuit designs.

[0096] NS 118 includes a 3D structure in which the channel region of logic device 100A is surrounded by multiple stacked nanosheets. NS 118 acts as a conductive channel within logic device 100A, and a gate structure controls the current flow through these sheets.

[0097] ILD 130 can serve as an insulating layer to electrically isolate different layers of conductive and active components and provide mechanical support therebetween. ILD 130 enables efficient signal transmission, reduces crosstalk, and ensures proper operation of logic device 100A. In one embodiment, ILD 130 can electrically isolate adjacent conductive layers or active components in logic device 100A. By providing insulation between different layers, ILD 130 can prevent electrical short circuits, reduce (e.g., minimize) leakage current, and ensure that signals are guided only along the desired path. In some embodiments, ILD 130 can help reduce parasitic capacitance between adjacent metal interconnects or active devices and provide mechanical support for the structure of logic device 100A.

[0098] BILD 138 can be an insulating material or layer used to isolate the active region of logic device 100A from BSCA 126A and provide electrical insulation therebetween, and to prevent unwanted electrical contact between the active region and the back contact, thereby ensuring the proper operation and integrity of logic device 100A. In various embodiments, BILD 138 can act as a protective layer, shielding the active region of logic device 100A from external contaminants, moisture, and mechanical stress. BILD 138 can further help prevent physical damage, such as scratches or particle contamination, which may adversely affect the performance of the semiconductor device. In addition, BILD 138 can act as a barrier against moisture ingress, which can lead to corrosion and degradation of the logic device 100A components.

[0099] Referring now to Figures 1C to 1D, a diode 100B of a semiconductor device according to some embodiments is illustrated. Diode 100B includes vertically stacked epitaxial layers of first material 140A and second material 140B, a protective liner 142, N-type doped sections 144A, P-type doped sections 144B, a second reserved location 128B, one or more additional reserved locations PH2 166, a contact 146, a second back contact BSCA 126B, and a set of gate regions 148. The diode further includes an ILD 150, an STI 152, a BILD 154, a spacer 156, and an internal spacer 158. The semiconductor device may further include a back-end process BEOL 160, a carrier wafer 162, and a back-side power delivery network BSPDN 164.

[0100] The vertically stacked epitaxial layer of the first material 140A and the second material 140B may include silicon as the first material 140A and silicon-germanium as the second material 140B. The presence of such a conductive stacked multilayer can enhance the effective area of ​​the channel region, which in turn can improve the overall efficiency of the diode 100B.

[0101] The protective liner 142 protects the underlying devices, such as the vertically stacked epitaxial layers of the first material 140A and the second material 140B, PH2 166, and STI 152, from potential damage during the manufacturing process. In other words, although as shown in FIG1C, in an X2 cut, the two opposite sides of the vertically stacked epitaxial layers of the first material 140A and the second material 140B are covered by N-type doped segments 144A and P-type doped segments 144B, respectively, as shown in FIG1D, in a Y2 cut, the other two opposite sides of the vertically stacked epitaxial layers of the first material 140A and the second material 140B are covered by the protective liner 142.

[0102] The N-type doped region 144A and the P-type doped region 144B form the pn junction of diode 100B. This junction allows current to flow in one direction (forward bias) but blocks current flow in the reverse direction up to a certain reverse breakdown voltage. The N-type doped region 144A comprises an N-type semiconductor region with a high concentration of electrons. In other words, the N-type doped region 144A comprises a region in which most of the charge carriers are electrons. In some embodiments, to increase the electron density, a large amount of donor impurity (e.g., phosphorus or arsenic) is added to this region, thus transforming it into an N+ region.

[0103] P-type doped region 144B includes a P-type semiconductor region with a high concentration of holes. In some embodiments, to generate P-type doped region 144B, a high concentration of acceptor impurities (e.g., boron or aluminum) is introduced into the semiconductor material.

[0104] In some embodiments, the N-type doped segment 144A is connected to the front side of the diode 100B via contact 146. In some embodiments, the set of gate regions 148 is connected to the front side of the diode 100B via contact 146. In one embodiment, the P-type doped segment 144B is connected to the back side of the diode 100B via BSCA 126B.

[0105] A contact 146 located above the N-type doped region 144A establishes a connection between the N-type doped region 144A and the BEOL 160. Contact 146 ensures effective wiring and connectivity within the diode 100B. The fabrication of contact 146 may involve lithography and etching processes to define the contact area. Contact 146 can be made of conductive materials such as silicate liners (e.g., Ni, Ti, NiPt), bonding metal layers (e.g., TiN), and conductive metal fillers (e.g., tungsten (W), Co, or Ru).

[0106] The BSCA 126B is the area on the back of diode 100B where electrical connections are made. By establishing electrical contacts, the BSCA 126B ensures the normal operation of diode 100B and facilitates the transmission of electrical signals.

[0107] The BSCA 126B can serve as a thermal interface between the diode 100B and a heatsink or other cooling mechanism. By establishing direct contact with the substrate, the BSCA 126B can conduct heat away from the diode 100B and facilitate improved heat dissipation. In some embodiments, the BSCA 126B can help mitigate parasitic effects from the diode 100B, such as substrate coupling or substrate noise. In further embodiments, the BSCA 126B can allow for increased integration density in the diode 100B. In one embodiment, the BSCA 126B connects (e.g., wires) the P-type doped segment 144B to the BSPDN 164.

[0108] In various embodiments, the set of gate regions 148 acts as a control element for regulating the current flow through diode 100B. The set of gate regions 148 may be made of a conductive material. The set of gate regions 148 controls the current flow between the P-type doped segment 144B and the N-type doped segment 144A. In some embodiments, by applying a voltage to the gate, the conductivity of the channel region is modulated, thereby allowing diode 100B to allow or block current flow, which in turn enables diode 100B to act as an electronic switch or amplifier. The gate voltage determines whether diode 100B is in an "on" or "off" state. When the gate voltage is below a certain threshold, diode 100B is in an "off" state, and the current flow between the N-type doped segment 144A and the P-type doped segment 144B is effectively blocked. On the other hand, when the gate voltage exceeds the threshold, diode 100B enters an "on" state, thereby allowing current to flow through the channel region. In addition to acting as a switch, modulating the gate voltage allows the gate region 122 to control the current flowing through the channel region, thereby generating an amplified output signal.

[0109] The ILD 150 serves as an insulating layer to electrically isolate different layers of conductive and active components and provides mechanical support therebetween. The ILD 150 enables efficient signal transmission, reduces crosstalk, and ensures proper operation of the diode 100B. In one embodiment, the ILD 150 electrically isolates adjacent conductive layers or active components within the diode 100B. By providing insulation between different layers, the ILD 150 prevents electrical short circuits, reduces (e.g., minimizes) leakage current, and ensures that signals are guided only along the desired path. In some embodiments, the ILD 150 can help reduce parasitic capacitance between adjacent metal interconnects or active devices and provide mechanical support for the diode 100B structure.

[0110] BILD 154 can be an insulating material or layer used to isolate the active region of diode 100B from BSCA 126B and provide electrical insulation therebetween, preventing unwanted electrical contact between the active region and the back contact, thereby ensuring the proper operation and integrity of diode 100B. In various embodiments, BILD 154 can act as a protective layer, shielding the active region of diode 100B from external contaminants, moisture, and mechanical stress. BILD 154 can further help prevent physical damage, such as scratches or particle contamination, which can adversely affect the performance of the semiconductor device. Additionally, BILD 154 can act as a barrier against moisture ingress, which can lead to corrosion and degradation of the diode 100B assembly.

[0111] BEOL 160 includes, for example, metal interconnects such as wires and metal wires, and an insulating layer, which connects various components of the logic device 100A and enables it to act as an adhesive unit.

[0112] In some embodiments, BSPDN 164 is formed and covers BSCA 126A and BILD 154. BSPDN 164 can connect logic device 100A to other devices. In some embodiments, the back side of diode 100B and the back side of logic device 100A are in direct contact with BSPDN 164 via BILD 138.

[0113] Example fabrication of a semiconductor device with integrated diodes and logic devices The preceding description of the example semiconductor device is helpful in illustrating the exemplary actions involved in its manufacture. To this end, Figures 2 through 17 depict various actions in the manufacture of a semiconductor device consistent with the illustrative embodiments. Referring to Figure 1E, the diagram represented by A depicts the X1 cross-section of the logic device, and the diagram represented by B depicts the Y1 cross-section of the logic device. Similarly, referring to Figure 1E, the diagram represented by C depicts the X2 cross-section of the diode, and the diagram represented by D depicts the Y2 cross-section of the diode. It is also worth mentioning that the semiconductor devices depicted in Figures 1A through 1D can be the same as those depicted in Figures 2 through 17. For ease of illustration, the manufacturing actions described herein will be described in the context of forming nanosheet transistors as logic devices, and it will be understood that other semiconductor structures are also supported by the teachings herein.

[0114] Referring now to Figures 2A to 2D, a semiconductor device is illustrated according to some embodiments after patterning of a nanosheet. In some embodiments, after patterning of the nanosheet NS 218, the logic device 200A and diode 200B include a first substrate 212A, a second substrate 212B, an etch-stop layer 210 between the first substrate 212A and the second substrate 212B, a vertically stacked epitaxial layer of silicon Si 214A and silicon germanium SiGe 214B, STI 216, a dummy gate 228, a hard mask HM 220, and a spacer 222.

[0115] In the illustrative examples depicted in Figures 2A to 2D, the semiconductor device is depicted as being located on silicon, which serves as the first substrate 212A and the second substrate 212B. However, it will be understood that other types of substrates may also be used, including but not limited to single-crystal Si, silicon-germanium (SiGe), III-V compound semiconductors, II-VI compound semiconductors, or semiconductor-on-insulator (SOI). III-V compound semiconductors include, for example, materials having at least one Group III element and at least one Group V element, such as one or more of the following: aluminum gallium arsenide (AlGaAs), aluminum gallium nitride (AlGaN), aluminum arsenide (AlAs), aluminum indium arsenide (AlIAs), aluminum nitride (AlN), gallium antimonide (GaSb), gallium aluminum antimonide (GaAlSb), gallium arsenide (GaAs), gallium arsenide (GaAsSb), gallium nitride (GaN), indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium gallium phosphide (InGaAsP), indium gallium nitride (InGaN), indium nitride (InN), indium phosphide (InP), and alloy combinations including at least one of the foregoing materials. Alloy combinations may include binary (two elements, e.g., gallium (III)(GaAs)), ternary (three elements, e.g., InGaAs), and quaternary (four elements, e.g., aluminum gallium indium phosphide (AlInGaP)) alloys.

[0116] In various embodiments, the first substrate 212A and the second substrate 212B may comprise any suitable material or combination of materials, such as doped or undoped silicon, glass, dielectrics, etc. For example, the substrate may comprise, for instance, a silicon-on-insulator (SOI) structure having an embedded insulating layer, or, for instance, a bulk material substrate having appropriately doped regions (commonly referred to as wells). In another embodiment, the substrate may be silicon with a silicon oxide, nitride, or any other insulating film on top.

[0117] In various embodiments, an etch stop layer 210 is formed over the first substrate 212A. The etch stop layer 210 may be a thin material layer incorporated into the structure of the semiconductor device to provide a selective barrier for the etching process, thereby preventing further removal of underlying material during manufacturing. The etch stop layer 210 enables precise control of the etching depth and helps define the desired device dimensions. The etch stop layer 210 may further provide an end point for the etching process, ensuring that a specific layer or area is not etched beyond a certain point, resulting in accurate patterning and control of critical features. The etch stop layer 210 can create distinct spacing between different layers or components within the device structure and prevent unintended etching of underlying layers or materials, thereby enabling the creation of complex multilayer structures with well-defined interfaces and boundaries. In some embodiments, the etch stop layer 210 acts as a protective barrier for sensitive or delicate materials, shielding them from corrosive etchants to prevent damage or degradation during subsequent manufacturing steps.

[0118] In some embodiments, a first substrate 212A is prepared by cleaning and removing any impurities or oxide layers before forming the etch stop layer 210. The etch stop layer 210 is deposited onto the first substrate 212A using techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In one embodiment, photoresist may be applied, exposed to a patterned mask, developed, and used as a protective layer to define the etch stop region. The etch stop layer 210 may then be selectively etched to terminate at a predetermined depth while protecting the underlying layer. After the etching process, any remaining photoresist may be removed by a stripping technique. While SiGe is used to form the etch stop layer 210 in some embodiments, silicon nitride (SiN), silicon oxide (SiO2), or silicon oxynitride (SiON) may be used as the etch stop layer 210 in other embodiments. In some embodiments, a second substrate 212B is epitaxially grown over the etch stop layer 210.

[0119] In various embodiments, the vertically stacked epitaxial layers of Si 214A and SiGe 214B in the Y1 and Y2 cross sections of the logic device 200A and diode 200B depicted in Figures 2B and 2D, respectively, extend horizontally above the second substrate 212B. In other words, the vertically stacked epitaxial layers of Si 214A and SiGe 214B do not cover STI 216.

[0120] Figures 3A to 3D illustrate a semiconductor device including a logic device 300A and a diode 300B after a recess in a nanosheet, according to some embodiments. In some embodiments, NS 218 may be recessed, thus exposing the surface of the second substrate 212B. It should be noted that the portion of the logic device 300A covered by HM 220 (i.e., the Y1 cross-section) remains intact, as shown in Figure 3B.

[0121] Figures 4A to 4D illustrate semiconductor devices including logic device 400A and diode 400B after the silicon-germanium layer is pressed in, according to some embodiments. In some embodiments, an organic planarization layer OPL 410 is formed over the vertically stacked epitaxial layers of Si 214A and SiGe 214B gates of diode 400B. OPL 410 protects the underlying device from the effects of the manufacturing process. Subsequently, the silicon-germanium layer of the vertically stacked epitaxial layers of Si 214A and SiGe 214B is pressed in using a suitable method, such as etching.

[0122] Figures 5A to 5D illustrate semiconductor devices including logic devices 500A and diodes 500B after the formation of internal spacers, according to some embodiments. In some embodiments, internal spacers 510 are formed between every two adjacent layers of Si 214A and SiGe 214B in the logic devices 500A and diodes 500B. In various embodiments, the OPL is removed.

[0123] Figures 6A to 6D illustrate a semiconductor device including a logic device 600A and a diode 600B after the formation of a reserved position, according to some embodiments. In some embodiments, a protective spacer 610 is formed above the sidewall of the cavity between the gate regions. Subsequently, a portion of the second substrate 212B is removed, and a reserved position 620 is formed in the recessed portion. The portion of the second substrate 212B can be removed by reactive ion etching (RIE) technology. Generally, RIE is a dry etching process used in semiconductor device manufacturing to selectively remove material from the surface of a substrate. In some embodiments, RIE may involve using reactive ions and plasma to react with and chemically remove a specific material. In one embodiment, the RIE process begins by placing the semiconductor device in a vacuum chamber. The chamber is then evacuated to create a low-pressure environment. A reactive gas, which may include a combination of chemically reacting gases and inert gases, is introduced into the chamber. Chemically reactive gases such as fluorine-based gases (e.g., CF4, SF6) or chlorine-based gases (e.g., Cl2) can react with the material to be etched (i.e., the second substrate Si), while inert gases such as argon can help control ion bombardment.

[0124] In some embodiments, radio frequency or microwave power is applied to generate plasma within a cavity. In these embodiments, the power excites gas molecules, ionizing them and forming a plasma of reactive ions and electrons. The plasma may include reactive ions that chemically react with silicon. The reactive ions bombard the substrate surface, breaking chemical bonds and removing silicon. In various embodiments, the RIE process may be selective, meaning it may primarily affect the target material, i.e., silicon, while other materials, such as masking layers or underlying layers, remain relatively unaffected.

[0125] In some embodiments, to achieve selective etching, an etching mask may be applied to the substrate surface prior to the RIE process. The etching mask protects certain areas from etching, allowing reactive ions to selectively remove exposed material. The etching process can be controlled to achieve specific etching profiles, such as vertical sidewalls or tapered structures. Parameters such as gas composition, pressure, power, and process duration are adjusted to achieve the desired etching characteristics. In some embodiments, endpoint detection techniques such as photoemission spectroscopy or laser interferometry can be used to determine when the etching process has reached the desired endpoint. This ensures accurate control of the etching depth and prevents over-etching. After the etching process is complete, the substrate can be cleaned to remove any residues or byproducts from the self-etching process. Cleaning may involve solvent rinsing or plasma cleaning to ensure the substrate surface is free of contaminants. Subsequently, the removed portion of the second substrate 212B may be filled with the reserved location 620. The reserved location 620 can be epitaxially grown.

[0126] Figures 7A to 7D illustrate a semiconductor device including a logic device 700A and a diode 700B after the formation of the source / drain regions, according to some embodiments. In some embodiments, the source / drain region 710 is formed above a reserved location 620 in the logic device 700A. Similarly, N-type doped regions 712A and P-type doped regions 712B are formed above the reserved location 620 in the diode 700B. Before forming the source / drain regions 710, the N-type doped region 712A, and the P-type doped region 712B, and to maintain the vertically stacked epitaxial layers of Si 214A and SiGe 214B that do not contact the N-type doped region 712A and the P-type doped region 712B in the diode 700B, a protective liner 720, for example, of silicon nitride, covers the vertically stacked epitaxial layers of Si 214A and SiGe 214B in the diode 700B that do not contact the N-type doped region 712A and the P-type doped region 712B in the diode 700B. The protective liner 720 may cover STI 216 and additional reserved positions 740 that do not contact the N-type doped region 712A and the P-type doped region 712B in the diode 700B.

[0127] Figures 8A to 8D illustrate a semiconductor device including a logic device 800A and a diode 800B after the formation of an interlayer dielectric according to some embodiments. In some embodiments, an interlayer dielectric ILD 810 is formed over the source / drain region 710 in the logic device 800A, and over the N-type doped region 712A and the P-type doped region 712B and the protective liner 720 in the diode 800B.

[0128] Figures 9A to 9D illustrate a semiconductor device including logic device 900A and diode 900B after the removal of a dummy gate, according to some embodiments. In some embodiments, the dummy gate is removed.

[0129] Figures 10A to 10D illustrate semiconductor devices including logic device 1000A and diode 1000B after the removal of the silicon-germanium layer according to some embodiments. In some embodiments, the SiGe layer is removed from the vertically stacked epitaxial layers of Si 214A and SiGe 214B in logic device 1000A and diode 1000B. However, the protective liner 720 and the N-type doped sections 712A and P-type doped sections 712B prevent the SiGe layer of the vertically stacked epitaxial layers of Si 214A and SiGe 214B from being removed in the Y1 and Y2 sections of diode 1000B shown in Figures 10C to 10D.

[0130] Figures 11A to 11D illustrate semiconductor devices including logic devices 1100A and diodes 1100B after the formation of a replacement metal gate HKMG 1110, according to some embodiments. In some embodiments, a metal gate material is formed that is suitable for the desired threshold voltage and electronic behavior of the semiconductor device. The replacement metal gate (RMG) process can be used to fabricate metal gate electrodes, forming source / drain contacts, gate contacts, and metal gate regions in N-type doped segments 712A and P-type doped segments 712B. In some embodiments, the RMG may involve replacing SiGe with a metal material, which can provide improved electrical performance and scalability. The metal gate can provide electrostatic control of the channel region, reduce leakage current, and improve the performance of the semiconductor device. In some embodiments, the metal gate can further provide improved control of the work function, achieve threshold voltage matching, and reduce the variability of the semiconductor device.

[0131] Figures 12A to 12D illustrate a semiconductor device including logic device 1200A and diode 1200B after mid-process formation according to some embodiments. In some embodiments, a mid-process (MOL) is performed. The formation of the MOL involves the formation of metal layers and interconnects connecting various components and transistors on the semiconductor device. In several embodiments, multiple metal layers are deposited and patterned on the semiconductor device during the MOL process. These metal layers act as electrical connections, such as contacts CA 1210 and gate contacts CB 1220, which allow signals to be transmitted between different parts of the integrated circuit. In addition to the metal layers, insulating layers (typically made of a low-k dielectric material such as ILD) may be deposited between the metal layers to isolate them from each other and prevent electrical interference. In some embodiments, advanced lithography and patterning techniques are used to define intricate patterns of metal lines and vias (vertical connections between metal layers) during the MOL process. Chemical mechanical polishing (CMP) can be performed to ensure a flat and smooth surface for subsequent metal layers. This CMP involves planarizing the surface of the semiconductor device after each metal layer deposition. In one embodiment, barrier and liner layers are deposited before the metal layers to enhance adhesion, prevent metal diffusion, and improve overall performance.

[0132] In some embodiments, a back-end process BEOL 1240 is formed over the MOL, followed by the formation of a carrier wafer 1250. BEOL 1240 may include metal interconnects such as wires and metal lines, as well as an insulating layer, which connects various components of the semiconductor device and enables it to act as an adhesive unit.

[0133] In various embodiments, carrier wafer bonding, also known as wafer-to-wafer bonding or chip-to-wafer bonding, is performed to join two semiconductor devices together by creating a permanent bond between them. In some embodiments, the two semiconductor devices may be in contact and bonded at the atomic or molecular level to create an interface. In one embodiment, the two semiconductor devices are brought into contact under controlled conditions, such as controlled pressure and temperature, to achieve atomic or molecular bonding at the interface. Such bonding may be performed at room temperature or at high temperatures. Alternatively, in some embodiments, bonding is created using an electric field and high temperature. One semiconductor device may be made of a semiconductor material, while the other semiconductor device may be a glass or silicon dioxide (SiO2) wafer. The electric field can cause ions in the glass or SiO2 to migrate and chemically bond with the semiconductor material in the other semiconductor device. In additional embodiments, a thin metal layer or metal alloy may be used as an intermediate bonding layer between the semiconductor devices. The metal layer may be deposited or transferred onto the surfaces of one or both semiconductor devices, and these semiconductor devices may then be in contact and subjected to temperature and pressure to create a metallic bond.

[0134] Figures 13A to 13D illustrate a semiconductor device including logic device 1300A and diode 1300B after the removal of a first substrate, according to some embodiments. In some embodiments, the wafer is flipped and the first substrate is removed. It should be noted that, for simplicity, the semiconductor device is not shown flipped.

[0135] Figures 14A to 14D illustrate a semiconductor device including logic device 1400A and diode 1400B after removal of an etch stop layer, according to some embodiments. In some embodiments, the etch stop layer and the second substrate are removed.

[0136] Figures 15A to 15D illustrate semiconductor devices including logic devices 1500A and diodes 1500B after the formation of a back-side interlayer dielectric according to some embodiments. In some embodiments, a back-side dielectric BILD 1510 is formed beneath vertically stacked epitaxial layers of Si 214A and SiGe 214B, and surrounds reserved locations 620 and STI 216. BILD 1510 may be an insulating material or layer that isolates the semiconductor device from the reserved location 620 in the active region and provides electrical insulation therebetween. In various embodiments, BILD 1510 may act as a protective layer, thereby shielding the active region of the semiconductor device from external contaminants, moisture, and mechanical stress. BILD 1510 may further help prevent physical damage, such as scratches or particle contamination, which may adversely affect the performance of the semiconductor device. Additionally, BILD 1510 may act as a barrier against moisture ingress, which can lead to corrosion and degradation of components of the semiconductor device. The first and second substrates can be removed by the RIE process.

[0137] Figures 16A to 16D illustrate a semiconductor device including a logic device 1600A and a diode 1600B after patterning of the back contact according to some embodiments. In some embodiments, sacrificial reserved positions are removed, thereby forming a recess 1610 that exposes the bottom of the source / drain regions and the N-type doped segment 712A or the P-type doped segment 712B.

[0138] Figures 17A to 17D illustrate a semiconductor device including logic device 1700A and diode 1700B after the formation of the back contact, according to some embodiments. In some embodiments, the back contact BSCA 1710 is formed in a recess by filling a recess with a metal contact. BSCA 1710 is surrounded by BILD 1510. A back interconnect 1720 is formed to cover BSCA 1710 and BILD 1510. The back interconnect 1720 can be used to connect the semiconductor device to other devices.

[0139] Figure 18 illustrates a block diagram of a method 1800 for forming a semiconductor device according to some embodiments. As shown by block 1810, a diode is formed.

[0140] As shown in block 1820, as part of forming the diode, a first source / drain region and a first front contact above the first source / drain region are formed.

[0141] As shown in block 1830, a first back contact and a reserved position are formed as part of forming the diode.

[0142] As shown in square 1840, a transistor is formed.

[0143] As shown in block 1850, as part of forming the transistor, a second source / drain region and a second front contact above the second source / drain region are formed.

[0144] As shown in block 1860, as part of forming the transistor, a second back contact and a second reserved position are formed on the bottom surface of the second source / drain region.

[0145] In one embodiment, the methods and structures described above can be used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by a fabricator in the form of raw wafers (i.e., as a single wafer having multiple unpackaged chips), as bare dies, or in a packaged form. In the latter case, the chips can be mounted in a single-chip package (such as a plastic carrier having wires attached to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier having either surface-mount interconnects or embedded interconnects, or both). In any case, the chips can then be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product encompassing integrated circuit chips ranging from low-end applications (such as toys) to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0146] in conclusion Various embodiments of the invention have been described for illustrative purposes, but such descriptions are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles, practical applications, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0147] While the best-case scenario and / or other examples have been described above, it should be understood that various modifications may be made therein, and the subject matter disclosed herein can be implemented in various forms and instances, and the teachings can be applied to many applications, only some of which are described herein. The following claims are intended to assert any and all applications, modifications, and variations that fall within the true scope of the teachings of this invention.

[0148] The components, steps, features, objectives, benefits, and advantages discussed herein are illustrative only. None of these and related discussions are intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, quantities, sizes, and other specifications set forth in this specification (including in the following claims) are approximate and not precise. They are intended to have a reasonable scope, consistent with their associated functions and with convention in the art.

[0149] This also covers many other embodiments. These include embodiments with fewer, additional, and / or different components, steps, features, objectives, benefits, and advantages. These also include embodiments where components and / or steps are configured and / or ordered differently.

[0150] Although the foregoing description has been accompanied by exemplary embodiments, it should be understood that the term "exemplary" means only as an example, not the best or optimal. Apart from what has just been stated above, nothing stated or illustrated is intended or should be construed as making any component, step, feature, object, benefit, advantage, or equivalent public-private, whether or not it is described in the claims.

[0151] It will be understood that, except where otherwise set forth herein, the terms and expressions used herein have the same general meaning as given to their respective respective queries and fields of study. Relational terms such as "first," "second," and "like" are used only to distinguish one entity or action from another, and do not necessarily require or imply any actual relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of components includes not only those components but may also include other components not expressly listed or inherent to such process, method, article, or apparatus. Without further constraints, an element preceded by "a" or "an" does not exclude the presence of additional identical components in the process, method, article, or apparatus that includes that element.

[0152] This summary of disclosure is provided to allow the reader to quickly determine the nature of the disclosed technical content. It should be understood that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing embodiments, it is evident that various features are grouped together in different embodiments for the purpose of simplification. This method of disclosure should not be construed as reflecting an intention that the claimed embodiments have more features than explicitly described in the respective technical solutions. In fact, as reflected in the following claims, the subject matter of the invention lies in fewer than all the features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the embodiments, wherein each technical solution is, in itself, a separately claimed subject matter.

[0153] 100A: Logic Device 100B: Diode 100C: Diode 114A: First source / drain region 114B: Second source / drain region 116: Source / Drain Contact 118: Nanoparticles 122: Gate region 124: Gate contact 126: Shallow ditch isolation 126A: First back contact element 126B: Second back contact 128A: First reserved position 128B: Second reserved position 130: Interlayer dielectric 132: Spacer 134: Internal spacers 138: Bottom Dielectric Layer 140A: First Material 140B: Second Material 142: Protective Lining 144A: N-type doped region 144B: P-type doped region 146: Contact element 148: Gate Region 150:ILD 152:STI 154:BILD 156: Spacer 158: Internal spacers 160: Back-end process 162: Carrier wafer 164: Rear power transmission network 166: Additional reserved space 200A: Logic Device 200B: Diode 210: Etching stop layer 212A: First substrate 212B: Second substrate 214A: Silicon 214B: Silicon Germanium 216:STI 218: Nanoparticles 220: Hard Mask 222: Spacer 228: Dummy gate 300A: Logic Device 300B: Diode 400A: Logic Device 400B: Diode 410: Organic planarization layer 500A: Logic Device 500B: Diode 510: Internal spacers 600A: Logic Device 600B: Diode 610: Protective spacer 620: Reserved space 700A: Logic Device 700B: Diode 710: Source / Drain Region 712A: N-type doped region 712B: P-type doped region 720: Protective Lining 740: Additional reserved space 800A: Logic Device 800B: Diode 810: Interlayer Dielectric 900A: Logic Device 900B: Diode 1000A: Logic Device 1000B: Diode 1100A: Logic Device 1100B: Diode 1110: Replace the metal gate 1200A: Logic Device 1200B: Diode 1210: Contact element 1220: Gate contact 1240: Back-end process 1250: Carrier wafer 1300A: Logic Device 1300B: Diode 1400A: Logic Device 1400B: Diode 1500A: Logic Device 1500B: Diode 1510: Backside Dielectric 1600A: Logic Device 1600B: Diode 1610: Groove 1700A: Logic Device 1700B: Diode 1710: Back contact component 1720: Backside interconnect 1800: Method 1810: Square 1820: Square 1830: Square 1840: Square 1850: Square 1860: Square X1: Cross section X2: Cross section Y1: Cross section Y2: Cross section

Claims

1. A semiconductor device comprising: a diode including: a first front contact located above a first source / drain region; a first back contact; and a first reserved location connected to a bottom surface of one of the first source / drain regions.

2. The semiconductor device of claim 1, further comprising a transistor including: a second front contact located above a second source / drain region; a second back contact; and a second reserved location connected to a bottom surface of the second source / drain region.

3. The semiconductor device of claim 2, wherein the diode is an electrostatic discharge (ESD) diode.

4. The semiconductor device of claim 2, wherein the transistor comprises a plurality of nanoplate gates.

5. The semiconductor device of claim 1, wherein the diode further comprises: A third source / drain region; The alternating layers of silicon and silicon-germanium extend horizontally between the first source / drain region and the third source / drain region.

6. The semiconductor device of claim 5, wherein the first source / drain region is an N-type source-drain region and the third source / drain region is a P-type source / drain region, or the first source / drain region is a P-type source-drain region and the third source / drain region is an N-type source / drain region.

7. The semiconductor device of claim 5, wherein the diode further comprises: shallow trench isolation (STI); one or more additional reserved locations; and a protective liner located above the STI, the one or more additional reserved locations, and portions of the diode that are not in direct contact with the first source / drain region and the third source / drain region.

8. The semiconductor device of claim 7, wherein the protective liner is made of silicon nitride.

9. The semiconductor device as claimed in claim 2, wherein: The diode is adjacent to the transistor; and the diode and the transistor are separated by an internal spacer via a dummy gate.

10. A semiconductor device comprising: a diode including: a first front contact located above a first source / drain region; and a first reserved location connected to a bottom surface of the first source / drain region; and a logic device including a logic back contact and a logic front contact.

11. The semiconductor device as claimed in claim 10, wherein: The diode is an electrostatic discharge (ESD) diode; and the logic device is a nanoplate transistor.

12. The semiconductor device of claim 10, wherein the diode further comprises: a second source / drain region; and alternating layers of silicon and silicon-germanium extending horizontally between the first source / drain region and the second source / drain region.

13. The semiconductor device as claimed in claim 12, wherein: The first source / drain region is an N-type source-drain region, and the second source / drain region is a P-type source / drain region; or the first source / drain region is a P-type source-drain region, and the second source / drain region is an N-type source / drain region.

14. The semiconductor device of claim 12, wherein the diode further comprises: shallow trench isolation (STI); one or more additional reserved locations; and a protective liner located above the STI, the one or more additional reserved locations, and portions of the diode that are not in direct contact with the first source / drain region and the second source / drain region.

15. The semiconductor device of claim 10, wherein the diode is adjacent to the logic device, wherein the diode and the logic device are separated by an internal spacer via a dummy gate.

16. A method for forming a semiconductor device, the method comprising: forming a diode, the diode comprising: forming a first source / drain region; forming a first front contact over the first source / drain region; forming a first back contact; and forming a reserved position at a bottom surface of one of the first source / drain regions.

17. The method of claim 16, further comprising: forming a transistor, comprising: forming a second source / drain region; forming a second front contact above the second source / drain region; forming a second back contact; and forming a second reserved position at one bottom surface of the second source / drain region.

18. The method of claim 17, further comprising forming a plurality of nanosheet gates extending horizontally along the gate channel.

19. The method of claim 16, further comprising: forming a third source / drain region; and forming alternating layers of silicon and silicon-germanium extending horizontally between the first source / drain region and the third source / drain region.

20. The method of claim 19, further comprising: forming a shallow trench isolation (STI); forming one or more additional reserved locations; and forming a protective liner over the STI, the one or more additional reserved locations, and the portions of the diode that are not in direct contact with the first source / drain region and the third source / drain region.

21. The method of claim 17 further comprises isolating the diode and the transistor by means of a dummy gate via an internal spacer.

22. A method for forming a semiconductor device, the method comprising: forming a diode, comprising: forming a first source / drain region; forming a first front contact over the first source / drain region; and forming a first reserved location connected to a bottom surface of the first source / drain region; and forming a logic device, comprising: forming a logic back contact; and forming a logic front contact.

23. The method of claim 22, further comprising: forming a second source / drain region; and forming an alternating layer of silicon and silicon-germanium extending horizontally between the first source / drain region and the second source / drain region.

24. The method of claim 23 further comprises: forming a shallow trench isolation (STI); forming one or more additional reserved locations; and forming a protective liner over the STI, the one or more additional reserved locations, and the portions of the diode that are not in direct contact with the first source / drain region and the second source / drain region.

25. The method of claim 22 further comprises isolating the diode and the logic device by means of a dummy gate via an internal spacer.

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