Integrated circuit package and method of forming same

Abstract

In some embodiments, the apparatus includes a wafer on an interposer element on a first side of a package substrate, and a first annular structure on the first side of the package substrate. The first annular structure extends around the periphery of the wafer on the interposer element. A cap may be disposed on the first annular structure. The apparatus further includes an array of connectors on a second side of the package substrate, wherein the second side of the package substrate is relative to the first side of the package substrate. A second annular structure may be on the second side of the package substrate. The second annular structure is positioned around the periphery of the array of connectors.

Description

[Previous Technology]

[0001] Since the discovery of integrated circuits (ICs), the semiconductor industry has experienced rapid growth due to the continuous increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this improvement in integration density comes from the repeated reduction of the minimum feature size, which allows more components to be integrated into a given area.

[0002] To further improve circuit density, three-dimensional (3D) ICs have been investigated. In a typical 3D IC fabrication process, two dies are bonded together, and an electrical connection is formed between each die and a contact pad on the substrate. Interposer stacking is part of 3D IC technology, in which through-silicon vias (TSVs) embedded in the interposer are connected to the silicon device via microbumps.

Implementation Method

[0006] The following disclosure provides numerous different embodiments or examples for implementing various features of the present invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0008] According to various embodiments, the back-side annular structure is integrated onto the back side of the package substrate of the integrated circuit package. For example, for a ball grid array (BGA) package, the back-side annular structure can provide improved package warpage control and higher bonding yield. The integrated circuit package may have a capped package architecture, which can help with package warpage control. However, in some cases, the degree of warpage control provided by the package cap may be limited, or additional strength may be required in larger package designs to further control warpage. The back-side annular structure can provide additional package reinforcement beyond that provided by the cap to further alleviate stresses that may cause package warpage.

[0009] Figures 1 through 13 show views of intermediate stages in the fabrication of an integrated circuit package according to some embodiments. Figures 1, 2, 3, 4, 5, 6, 7, 8, 9B, and 10B are cross-sectional views. Figures 9A, 10A, 11, 12, and 13 are top views, in which some features are omitted for clarity. A chip-on-interposer component is formed by bonding integrated circuit devices to a redistribution layer (RDL) interposer. The chip-on-interposer component is then mounted onto a package substrate. Furthermore, a back-side annular structure is attached to the back side of the package substrate. The back-side annular structure can provide improved warpage control for the resulting integrated circuit package. It should be noted that this disclosure is not limited to the integrated circuit package provided only in the figures; embodiments of the integrated package may include other three-dimensional integrated circuit (3DIC) packages not specifically depicted herein.

[0010] In FIG. 1, a redistribution layer (RDL) interposer 109 is formed on a first carrier substrate 107. The redistribution layer (RDL) interposer 109 includes one or more metal interconnects 114 for electrically connecting subsequently bonded integrated circuit devices 120 (as shown in FIG. 2) to subsequently bonded package substrates 137 (as shown in FIG. 4) for signal and / or power routing. The redistribution layer (RDL) interposer 109 includes one or more metal interconnects 114 to provide electrical connections that allow bonding pads on subsequently formed integrated circuit devices to connect to wires or balls that connect the redistribution layer (RDL) interposer 109 to the package substrate 137. The bonding pads of the integrated circuit devices 120 can be bonded to the bonding pads of one or more metal interconnects 114.

[0011] The metal interconnect 114 may be formed in one or more layers of insulating material 115. In some embodiments, the one or more layers of insulating material 115 in the redistribution layer (RDL) interlayer 109 may have an organic composition. For example, the insulating material 115 in the redistribution layer (RDL) interlayer 109 may be a polymer composition. In some examples, the insulating material 115 in the redistribution layer (RDL) interlayer 109 may be a polymer material, such as epoxy resin. For example, the insulating material 115 of the redistribution layer (RDL) interlayer 109 may be epoxy resin to provide a matrix for a composite material, which further includes an amine compound curing agent, a filler including silicon dioxide and / or alumina, flexabilizers, and / or a curing agent. In other embodiments, the insulating material 115 of the redistribution layer (RDL) interlayer 109 may be a silicon-containing inorganic material. In some embodiments, the insulating material 115 in the redistribution layer (RDL) interlayer 109 may have a dielectric constant of less than 3.5. For example, the insulating material 115 in the redistribution layer (RDL) interlayer 109 may have a dielectric constant of about 3.3.

[0012] The redistribution layer (RDL) interposer 109 may be formed with an insulating material 115, such as a polymer insulating material, using deposition processes, spin coating processes, or the like. Lithography and etching processes may be used to form openings and trenches for metal lines and / or traces. Furthermore, deposition processes, such as sputtering, electroplating processes, or the like, may be used to form metallic materials, such as copper and / or aluminum, for the metal lines and / or traces. In some embodiments, planarization processes, such as chemical mechanical planarization (CMP), may be used to planarize the upper surface of the redistribution layer (RDL) interposer 109 (e.g., the upper layer of the insulating material).

[0013] In some embodiments, the redistribution layer (RDL) interlayer 109 may be formed on the supporting first carrier substrate 107 via a bonding layer 108. The first carrier substrate 107 may be formed of any rigid material, such as metal, glass, and / or semiconductor material (e.g., silicon (Si)). In some embodiments, the bonding layer 108 may be a release film, which may be a photothermal conversion (LTHC) layer.

[0014] In Figure 2, the die-on-intermediate (DIP) process is performed above the redistribution layer (RDL) interposer 109. The DIP architecture is not limited to those specifically depicted in the figure. For example, in some embodiments, the DIP architecture may also be provided by a System-on-Chip (SoC) architecture and / or a System-on-Integrated Circuit (SoIC) architecture.

[0015] In some embodiments, the integrated circuit device 120 is bonded to the upper surface of the redistribution layer (RDL) interposer 109. The integrated circuit device 120 may include logic elements 125 and / or memory elements 130. For example, the logic element 125 may include a device die, a package including the device die therein, a system-on-a-chip (SoC) or system-on-a-chip (SoIC) die that integrates multiple integrated circuits (or device dies) as a system, or the like. The device die in the logic element 125 may be or may include a processor die, a memory die, an input / output die, an integrated passive device (IPD), the like, or a combination thereof. For example, the processor die in the die on the interposer element may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller unit (MCU) die, a baseband (BB) die, an application processor (AP) die, or the like. The memory die in logic element 125 may include static random access memory (SRAM) die, dynamic random access memory (DRAM) die, or the like. The device die in logic element 125 may include a semiconductor substrate and interconnect structure.

[0016] In some embodiments, memory element 130 may include a memory stack, such as a high bandwidth memory (HBM) stack. In some other embodiments, memory element 130 may include memory dies forming a die stack and an encapsulation (e.g., a molding compound) encapsulating the memory dies.

[0017] In some embodiments, integrated circuit devices 120, such as logic elements 125 and memory elements 130, can be bonded to the underlying redistribution layer (RDL) interposer 109 via bonding members 150. For example, according to some embodiments, bonding members 150 are used via a chip-on-wafer (CoW) bonding process, wherein logic elements 125 and memory elements 130 (as separate wafers / packages) are bonded to the redistribution layer (RDL) interposer 109. Bonding members 150 can be solder bonds, direct bonding (e.g., metal-to-metal bonding), or the like.

[0018] Figure 2 illustrates the bonding of an integrated circuit device 120 (e.g., logic element 125 and memory element 130) to a redistribution layer (RDL) interposer 109. The integrated circuit device 120 can be bonded to contacts on the redistribution layer (RDL) interposer 109 using a solder bonding / flip die process. A bonding member 150 provides a connection between the contact pads of one or more metal interconnects 114 and the contact pads of the integrated circuit device 120. In some embodiments, the solder bonding method may include microbumps having a bump size of 25 microns or less. In some embodiments, the microbumps may also be formed from lead-free materials such as SnAg, SnCu, and SnAgCu. In some other cases, the microbumps may be formed from PbAg. The bonding member 150 can be formed using indirect bonding, mass reflow, thermoforming, direct bonding, copper-to-copper diffusion bonding, insert bump bonding, and combinations thereof. It should be noted that the microbump methods described above are for illustrative purposes only. Examples of other solder formation methods include solder paste printing, engraved mask stumps, photosensitive organic masks and squeegees, solder electroplating, vapor deposition, needle dispensing, solder paste printing, electroplated solder bumps, electroplated copper pillars with microbumps, and combinations thereof.

[0019] After solder is formed onto the contacts of the integrated circuit device 120, the solder can be brought into contact with the contacts on the contact pads of one or more metal interconnects 114 under elevated temperature and pressure to achieve bonding. After bonding, an underfill material 116 can be formed. The underfill material 116 can be a thermosetting epoxy resin or a polymer, formed on the joint 150 to protect them and enhance the strength of the solder joint.

[0020] In some embodiments, the underfill material 116 may be formed after the solder bumps have passed through a reflow oven and may be dispensed using an auto-injector. The underfill material 116 may then be formed, wherein the underfill material 116 flows under the integrated circuit device 120 (e.g., logic element 125 and memory element 130) by capillary action. In some embodiments, after formation, the underfill material 116 is cured by heating. In some embodiments, the structure including the integrated circuit device 120 and the redistribution layer (RDL) interposer 109 may be referred to as interposer-on-device 200 (as shown in FIG. 3). It should be noted that although a single logic element 125 and a single memory element 130 are depicted in the figure, the interposer-on-device 200 may include any number of integrated circuit devices 120. For example, the interposer-on-device 200 may include multiple logic elements 125 and multiple memory elements 130.

[0021] After the bottom filler 116 is formed, the structure can be encapsulated in a package 117, for example, by molding. For example, a structure including at least integrated circuit devices 120 (e.g., logic elements 125 and / or memory elements 130) bonded to a redistribution layer (RDL) interposer 109 can be placed in a mold, and molding material can be injected into the mold to encapsulate the integrated circuit devices 120 to the redistribution layer (RDL) interposer 109. The molding material of the package 117 can be an epoxy material. For example, the epoxy material of the package 117 can include epoxy resin, phenolic curing agent, fused silica filler, coupling agent, curing accelerator, and release agent for a compound structural matrix. In some embodiments, the above-described package materials can work together to protect the integrated circuit devices 120 (e.g., logic elements 125 and / or memory elements 130) from environmental factors such as moisture, heat, and physical stress, while also maintaining electrical insulation and structural integrity.

[0022] In FIG. 3, after the package 117 has hardened, the hardened structure can be planarized, for example, by using chemical mechanical planarization to planarize the package 117 to expose the upper surface of the integrated circuit device 120. The exposed planarized upper surface of the integrated circuit device 120 can then be attached to the tape structure 207. For example, the planarized upper surface of the integrated circuit device 120 can be attached to the tape structure 207, which also includes a ring structure 401. The ring structure 401 can be a metal ring to provide support and stability to the tape structure 207 during and after the peeling process. In some embodiments, the tape structure 207 can be ultraviolet tape; however, any other suitable adhesive or attachment may also be used. In some embodiments, after the tape structure 207 is attached to the integrated circuit device 120 (e.g., logic element 125 and memory element 130), the first carrier substrate 107 can be removed (as shown in FIG. 2). For example, the first carrier substrate 107 can be peeled off, for instance, by projecting a laser beam onto the release membrane to decompose the release membrane. After the first carrier substrate 107 is removed, the back surface of the redistribution layer (RDL) interlayer 109 is exposed.

[0023] FIG3 illustrates a solder bonding process embodiment formed on a wafer 200 on an interposer element. In some embodiments, solder bumps 129 are formed on the contacts of one or more metal interconnects 114 of a redistribution layer (RDL) interposer layer 109. In some embodiments, solder bumps 129 may be controlled collapse wafer connection (C4) bumps. Solder bumps 129 may be used to bond the wafer 200 on the interposer element to a package substrate 137 (as shown in FIG4).

[0024] As used herein, the term "solder" refers to any metal or metal compound or alloy that is melted and then cooled to join two or more metal surfaces together. Generally, solder has a melting point in the range of 150°C to 250°C. Solder bumps may be small ball-shaped solder (tin balls) bonded to contact areas, interconnects, or pads of a semiconductor device. In some embodiments, solder bumps may be made of lead-free solder mixtures or lead-tin solder.

[0025] In some embodiments, the solder bumping process forming the solder joint may include in-situ sputtering cleaning to remove oxides or photoresist before metal is deposited onto the contacts of one or more metal interconnects 114. Cleaning may also be used to roughen the surface of the contacts (also referred to as bonding pads) to promote better adhesion of the under-ball metallization (UBM). A metal mask may be used to pattern the UBM and bump deposition. In some embodiments, a chromium layer, a phase-change chromium / copper layer, a copper layer, and a gold layer are sequentially vapor-deposited to form a thin-film under-ball metallization (UBM) on the contacts of one or more metal interconnects 114. In one example, lead-tin solder is subsequently vapor-deposited over the UBM to form a thick solder layer. The height of the resulting solder bump is determined by the volume of the deposited vapor-deposited material. This also serves the purpose of the distance between the metal mask and the wafer, as well as the size of the mask opening. Due to the way the solder is formed in the solder mask opening, the deposited solder may be conical. The solder may be reflowed to form spheres.

[0026] In FIG. 4, the wafer 200 on the interposer element of FIG. 3 is bonded to a first side S1 of the package substrate 137. The bonding can be performed by flip chip bonding (FCB). The package substrate 137 can be a cored substrate or a coreless substrate. In some embodiments, the package substrate 137 can be a printed circuit board (PCB). A printed circuit board (PCB) is an electronic component that uses copper conductors to establish electrical connections between components. In some embodiments, the PCB for the package substrate 137 can be constructed by alternating layers of conductive copper and electrically insulating material. In some embodiments, the package substrate 137 can be a semiconductor material substrate, such as a group IV or group III-V semiconductor substrate. In one example, the package substrate 137 can be formed of a silicon-containing material, such as a silicon (Si) substrate, or a germanium-containing material, such as a silicon-germanium (SiGe) substrate.

[0027] After the solder bumps 129 are formed, the structure (e.g., die-on-intermediate 200) is flipped over, and the solder bumps 129 are aligned with the contact pads (also called bonding pads) of the metal interconnects on the package substrate 137. In some embodiments, the alignment accuracy may need to be on the order of several micrometers to ensure reliable functionality. Once the structure (e.g., die-on-intermediate 200) is flipped over and aligned on the package substrate 137, the solder bumps 129 are reflowed to allow the conductive material to spread uniformly on the bonding pads of the package substrate 137. This improves solder wettability and reduces the gap or spacing between the die-on-intermediate 200 and the package substrate 137.

[0028] Furthermore, an underfill material 135 may be formed between the die 200 on the interposer element and the package substrate 137. The underfill material 135 may also be referred to as a wafer-on-wafer (COW) molding. The underfill material 135 may be deposited on the edge of the die 200 on the interposer element, allowing it to flow through the gap between the die 200 on the interposer element and the package substrate 137 via capillary action, filling the space between the solder bumps 129. The underfill material 135 applied between the die 200 on the interposer element and the package substrate 137 depicted in FIG4 may be similar to the underfill material 116 formed between the integrated circuit device 120 and the redistribution layer (RDL) interposer 109 shown in FIG3. Therefore, the description of the underfill material 116 described above with reference to FIG3 is applicable to the description of the underfill material 135 existing between the die 200 on the interposer element and the package substrate 137.

[0029] In FIG. 5, the first annular structure 140 is attached to a first side S1 of the package substrate 137. When the first side S1 of the package substrate 137 is the front side of the package substrate 137, the first annular structure 140 may be referred to as a front annular structure. The first annular structure 140 may be a heat dissipation ring for providing heat dissipation for the device. The first annular structure 140 may be formed of a metal selected for heat dissipation performance, such as copper. However, any material capable of dissipating heat generated in the interposer element on the wafer 200 and the package substrate 137 may be used. The first annular structure 140 is located on the surface of the package substrate 137 where the interposer element on the wafer 200 is bonded. From a top view, the first annular structure 140 is configured to surround the periphery of the interposer element on the wafer 200.

[0030] In FIG. 6, the cap 375 is attached to the first annular structure 140 and the wafer 200 on the interposer element. In some embodiments, an adhesive material 373 is applied to the first annular structure 140. In some embodiments, the adhesive material 373 may include any material suitable for sealing the cap 375 to the first annular structure 140, such as epoxy resin, urethane, polyurethane, silicone elastomer, or the like. The adhesive material 373 may be applied wet-applied to the outer portion, periphery, or edge of the first annular structure 140 via an adhesive dispenser.

[0031] In addition, thermal interface material (TIM) 374 may be formed on the top of the wafer 200 (e.g., integrated circuit device 120) on the interposer element. The thermal interface material 374 may include, but is not limited to, thermal paste, phase change material, metal-filled polymer matrix, and solder (e.g., alloys of lead, tin, indium, silver, copper, bismuth, or the like). If the thermal interface material 374 is solid, it may be heated to a temperature at which a solid-to-liquid transition occurs and then formed in liquid form on the surface of the wafer 200 on the interposer element. In some embodiments, the thermal interface material 374 may be wet-applied to the top of the integrated circuit device 120 using a TIM dispenser with a stamp-type dispensing head. In some embodiments, the thermal interface material 374 may be formed to the top surface of the integrated circuit device 120 using stencil printing.

[0032] In some embodiments, after the thermal interface material 374 is formed onto the wafer 200 of the interposer element, the cap 375 may be bonded to at least one of the adhesive material 373 present on the first annular structure 140 and the thermal interface material 374 present on the integrated circuit device 120. In some embodiments, the cap 375 may be made of a thermally conductive material, such as copper, copper alloys, aluminum, aluminum alloys, cobalt, nickel, combinations thereof, and alloys thereof. However, the cap may be formed of any other material suitable for the application of this disclosure. For example, the material of the cap 375 may be selected based on its coefficient of thermal expansion (CTE). In some embodiments, the cap 375 may have a selective composition to have thermal expansion characteristics that can mitigate stresses that cause warping of the wafer 200 and / or the package substrate 137 of the interposer element. For example, the composition of the cap 375 material may be selected to have a coefficient of thermal expansion (CTE) in the range of 10 ppm / ˚C to 25 ppm / ˚C. In some embodiments, the cap 375 may have a selective composition for heat dissipation. For example, the composition of the cap 375 may have a high thermal conductivity (Tk), such as between about 200 W / m·K and about 400 W / m·K or higher, and may serve as a heat sink to dissipate the heat generated by the device in the package structure.

[0033] A cap 375 is positioned on the integrated circuit device 120 and the first annular structure 140. In some embodiments, the cap 375 may be positioned on the integrated circuit device 120 and the first annular structure 140 using a pick-and-place tool. In some embodiments, the cap 375 may be placed on top of the adhesive material 373 and the thermal interface material 374 to encapsulate and protect the integrated circuit device 120. It is understood that additional processes may be performed before, during, or after the adhesive and / or TIM application processes to complete the fabrication of the integrated circuit package, but for the sake of brevity, these additional processes are not discussed in detail here. For example, heat may be applied to the integrated circuit package to cure the structure by increasing the temperature of the thermal interface material 374 and the adhesive material 373.

[0034] In FIG. 7, an array of connectors 323 is formed on the side of a package substrate 137 (e.g., a printed circuit board) opposite to a first side S1 on which an interposer element-on-chip 200 is deposited. For example, the interposer element-on-chip 200 may be positioned on the first side S1 of the package substrate 137, while the array of connectors 323 may be positioned on a second side S2 of the package substrate 137, wherein the first side S1 and the second side S2 are opposite sides of the package substrate 137. In some embodiments, the first side S1 is the front side of the package substrate 137, and the second side S2 is the back side of the package substrate 137. In some embodiments, the array of connectors 323 may include a plurality of solder bumps. The array may be arranged in a set of multiple rows and columns of solder bumps. In some embodiments, the array of connectors 323 may be a ball grid array (BGA). In some embodiments, a ball grid array (BGA) may be formed by attaching solder balls to the bottom side of an integrated circuit package (e.g., the second side S2 of the package substrate 137). After reflow, the solder balls of the ball grid array (BGA) can form an electrical connection with the electrical connection of the package substrate 137. During the reflow process, the solder melts and self-aligns due to surface tension, forming a connection with the package substrate 137.

[0035] In some embodiments, the ball grid array forming the array of connectors 323 may include solder ball placement and a final reflow soldering step. Preparation of the package substrate 137 may include forming copper pads arranged in a grid pattern, where solder balls will be placed. This pattern may correspond to the required connection points on the electronic device to which the integrated circuit package will ultimately be connected. In some embodiments, solder ball placement may include forming solder balls on the pads on the package substrate 137, which may include the use of flux to ensure proper adhesion. The reflow process may include using a reflow oven, where the solder balls melt, allowing the array of connectors 323 of the ball grid array (BGA) to align and attach to a second side S2 of the package substrate 137, for example, due to surface tension.

[0036] In FIG. 8, the second annular structure 300 is attached to the second side S2 of the package substrate 137. When the second side S2 of the package substrate 137 is the back side of the package substrate 137, the second annular structure 300 may be referred to as a back-side annular structure. The second annular structure 300 extends around the periphery of the array of connectors 323. The second annular structure 300 may be formed of a material that provides improved warpage control of the integrated circuit package, such as warpage control of the wafer 200 on the package substrate 137 and / or interposer elements. The second annular structure 300 may facilitate higher bonding yields, such as higher bonding yields of ball grid arrays (BGAs) to subsequently connected electronic device substrates 450 (as shown in FIG. 14).

[0037] In some embodiments, the second annular structure 300 may have a polygonal geometry that, in top view, surrounds the periphery of the array of connectors 323. The polygonal geometry may include a polygonal shape, such as a square or rectangular configuration. In some aspects, each side of the second annular structure 300 may be a straight line in top view.

[0038] In some embodiments, the second annular structure 300 may be formed of a metal, such as copper, copper alloys, aluminum, aluminum alloys, nickel, cobalt, and combinations thereof and alloys thereof. However, the second annular structure 300 may be formed of any other suitable material that can counteract, mitigate, and / or reduce warpage in the wafer 200 on the package substrate 137 and / or interposer element by providing a coefficient of thermal expansion (CTE) that can counteract warpage stress in the package substrate 137 and / or wafer 200 on the interposer element. For example, the material composition of the second annular structure 300 may be selected to have a coefficient of thermal expansion (CTE) ranging from 10 ppm / ˚C to 25 ppm / ˚C. In some embodiments, the second annular structure 300 may be formed using stamping, cutting, grinding, or the like. The CTE of the second annular structure 300 may be lower than the CTE of the package substrate 137 and / or the CTE of the wafer 200 on the interposer element.

[0039] In some embodiments, the second annular structure 300 may be attached to a second side S2 of the package substrate 137 using an adhesive layer 299. In some embodiments, the adhesive layer 299 is disposed on the second annular structure 300 and / or the second side S2 of the package substrate 137. In some embodiments, the adhesive layer 299 may comprise any material suitable for attaching the second annular structure 300 to the second side S2 of the package substrate 137, such as epoxy resin, polyurethane, silicone rubber, or the like. It is understood that additional processes may be performed before, during, or after the adhesive application process to complete the fabrication of the integrated circuit package, but for the sake of brevity, these additional processes are not discussed in detail here. For example, heat may be applied to the integrated circuit package to cure the structure by increasing the temperature of the adhesive layer 299.

[0040] In some embodiments, the second annular structure 300 has a first height H1, which is smaller than the second height H2 of the array of connectors 323. The heights of the second annular structure 300 and the array of connectors 323 are measured from the second side S2 of the packaging substrate 137. For example, the second height H2 of the array of connectors 323 can range from 0.2 mm to 0.5 mm. The first height H1 may be selected to allow underfill material to be injected through an opening defined by the space between the second annular structure 300 and the subsequently connected electronic device substrate 450 (as shown in FIG. 14).

[0041] Figures 9A to 13 illustrate some geometric embodiments of the second annular structure 300. The geometry of the second annular structure 300 may be selected to facilitate the formation of underfill material into the array of connectors 323, and the underfill material may be positioned in a structural region including the package substrate 137 and the wafer 200 on the interposer element to alleviate stresses that may cause warping.

[0042] Figures 9A and 9B illustrate a multi-sided second annular structure 300, wherein the second annular structure 300 includes a groove 301 in each sidewall. In the embodiment depicted in Figure 9A, the multi-sided second annular structure 300 may have a quadrilateral geometry, such as a square perimeter geometry or a rectangular perimeter geometry. The perimeter geometry of the multi-sided second annular structure 300 may completely surround the array of connectors 323 in the integrated circuit package. Although the geometry depicted in Figures 9A and 9B includes four sides, the second annular structure 300 is not limited to this example. For example, the multi-sided second annular structure 300 may have more than four sides. For example, in a top view, the second annular structure 300 may have hexagonal, heptagonal, octagonal, nonagonal, decagonal geometry, as well as geometry with more or fewer sides.

[0043] Figure 9B shows a portion of the sidewall of the second annular structure 300 including a groove 301 with a third height H3, which is smaller than the first height H1 at the corner of the second annular structure 300. In the embodiment depicted in Figure 9B, only a single groove 301 exists between the corners of the second annular structure 300. In some embodiments, the groove 301 may provide an opening in the sidewall extending from the first corner C1 of the sidewall to the second corner C2 of the sidewall. The reduced height H3 of the sidewall including the groove 301 facilitates the formation of underfill material into the array of connectors 323 (as shown in Figure 9A). Furthermore, when the array of connectors 323 (e.g., a ball grid array) is engaging with the electronic device substrate 450 (as shown in Figure 14), the portion of the sidewall of the second annular structure 300 with the first height H1 can contact the electronic device substrate 450, wherein the groove 301 allows underfill material to be formed into the array of connectors 323 through the second annular structure 300. In this embodiment, the second annular structure 300 provides a bridge for direct contact with the electronic device substrate 450 and the package substrate 137, stabilizing the spacing between the substrates during solder reflow of the array of connectors 323.

[0044] Figures 10A and 10B illustrate another embodiment of the second annular structure 300. In the embodiment depicted in Figures 10A and 10B, the sidewalls of the second annular structure 300 include a plurality of grooves 301. Each groove 301 having a third height H3 exists in a portion of the sidewalls of the second annular structure 300, and each groove 301 is separated from adjacent grooves 301 by a portion of the sidewalls of the second annular structure 300 having a first height H1. Although the sidewalls of the second annular structure 300 depicted in Figure 10B have five grooves 301, the second annular structure 300 is not limited to this embodiment, as each sidewall of the second annular structure 300 may have any number of grooves 301.

[0045] Similar to the embodiment described with reference to FIG9B, when the array of connectors 323 (e.g., a ball grid array) is engaged with the electronic device substrate 450 (as shown in FIG14), the sidewall portion of the second annular structure 300 depicted in FIG10B having a first height H1 is accessible to the electronic device substrate 450, wherein a plurality of grooves 301 allow underfill material to be formed into the array of connectors 323 through the second annular structure 300. In this embodiment, the direct contact between the second annular structure 300 and the electronic device substrate 450 and the package substrate 137 provides a bridge to stabilize the spacing between the substrates during solder reflow of the array of connectors 323.

[0046] Figure 11 illustrates another embodiment of the second annular structure 300. For example, the height of the second annular structure 300 along its sidewalls is continuously equal to a first height H1 (as shown in Figure 8). In some embodiments, the sidewall width W1 (also referred to as the first width W1) of the second annular structure 300 shown in Figure 11 is uniform and continuous along the length of each sidewall. For example, for each side of the second annular structure 300, the sidewall width W1 is the same from the inner edge of the first corner C1 to the inner edge of the opposite second corner C2.

[0047] Figure 12 illustrates another embodiment of the second annular structure 300, wherein the width of the sidewall at corners C1 and C2 of the second annular structure 300 is greater than the width of the sidewall portion between corners C1 and C2. For example, the second annular structure 300 may include a second width W2 at corners C1 and C2, which is greater than the first width W1 of the sidewall portion between each sidewall corner C1 and C2 of the second annular structure 300. In one example, the corners C1 and C2 of the second annular structure 300 may have rectangular or square columnar structures on the inner surface of the second annular structure 300.

[0048] Figure 13 shows another embodiment of the second annular structure 300, wherein the corners C1 and C2 have triangular columnar structures on the inner surface of the second annular structure 300. Figure 13 shows another embodiment of the second annular structure 300, wherein the sidewall width at the corners C1 and C2 of the second annular structure 300 is greater than the width of the sidewall portion between the corners C1 and C2. In one embodiment, the second annular structure 300 includes a non-uniform width at each corner C1 and C2.

[0049] In the embodiments of Figures 11 to 13, the sidewalls of the second annular structure 300 have no grooves. Therefore, the sidewalls of the second annular structure 300 depicted in each of Figures 11 to 13 have no grooves. For example, the height of the second annular structure 300 along the sidewalls of the second annular structure 300 is continuously equal to the first height H1. In other embodiments, the sidewalls of the second annular structure 300 of Figures 11 to 13 also include one or more grooves 301.

[0050] Figure 14 illustrates the implementation of an integrated circuit package in an electronic device according to some embodiments. In particular, the package substrate 137 can be connected to an electronic device substrate 450, such as a circuit board (e.g., a motherboard). Figure 14 further illustrates the bonding of an array of connectors 323 to the electronic device substrate 450, and the formation of a bottom filler 435 to the array of connectors 323 through a groove 301 in the second annular structure 300.

[0051] In some embodiments, underfill 435 may be formed on the bottom of an array of connectors 323 (e.g., a ball grid array) to provide additional mechanical support and protect solder joints under stress. Underfill 435 may contact the inner edge of the second annular structure 300 and may flow capillarily through the gap between the package substrate 137 and the electronics substrate 450, filling the space between the connectors 323. The underfill 435 depicted in FIG. 14 may be similar to the underfill 116 shown in FIG. 3 located between the integrated circuit device 120 and the redistribution layer (RDL) interposer 109. Therefore, the underfill 116 described above with reference to FIG. 3 is applicable to describing the underfill 435 present between the package substrate 137 and the electronics substrate 450.

[0052] In some embodiments, the second annular structure 300 acts as a dam to receive underfill material 435 around the array of connectors 323 (e.g., a ball grid array). The groove 301 shown in Figures 9A to 10B provides additional passage for the underfill material 435 to be formed into the array of connectors 323. Although not shown separately in Figure 14, it should be understood that, for the embodiment of the second annular structure 300 described with reference to Figures 9A to 10B, when the array of connectors 323 (e.g., a ball grid array) is being engaged to the electronic device substrate 450, the sidewall portion of the second annular structure 300 having a first height H1 can contact the electronic device substrate 450, wherein the groove 301 (as shown in Figure 9B) or multiple grooves 301 (as shown in Figure 10B) allows underfill material to be formed into the array of connectors 323 through the second annular structure 300. In this embodiment, the second annular structure 300 provides a bridge to the direct contact between the electronic device substrate 450 and the package substrate 137 to stabilize the spacing between the substrates during solder reflow of the connector 323 array.

[0053] In some embodiments, the second annular structure 300 can provide better warpage control and higher bonding yield of the integrated circuit package, such as the high bonding yield of the array of connectors 323. The second annular structure 300 can also provide additional reinforcement for the cap 375 to further alleviate stresses that may cause warpage of the integrated circuit package.

[0054] According to one embodiment, a method includes bonding a die on an interposer element to a package substrate; bonding a first annular structure to a first side of the package substrate, wherein the first annular structure extends around the periphery of the die on the interposer element; bonding a cap to the first annular structure and the die on the interposer element; forming an array of connectors on a second side of the package substrate, wherein the second side of the package substrate is opposite to the first side of the package substrate; and bonding a second annular structure to the second side of the package substrate, wherein the second annular structure extends around the periphery of the array of connectors. In one embodiment, the die on the interposer element includes an integrated circuit die bonded to a redistribution layer interposer. In one embodiment, the array of connectors includes a ball grid array (BGA). In one embodiment, the coefficient of thermal expansion of the second annular structure is less than the coefficient of thermal expansion of the package substrate. In one embodiment, the second annular structure includes copper, aluminum, cobalt, or nickel, and wherein the cap includes copper, aluminum, cobalt, or nickel. In one embodiment, bonding the second annular structure to the second side of the package substrate includes attaching the second annular structure to the second side of the package substrate via an adhesive layer. In one embodiment, the second annular structure has a first height different from the second height of the connector array. In another embodiment, the method further includes bonding the connector array to an electronic device substrate; and forming a bottom filler into the connector array, wherein the second annular structure includes an opening through which the bottom filler is formed.

[0055] According to another embodiment, an apparatus includes a package substrate; an interposer element-on-a-die located on a first side of the package substrate; a ball grid array located on a second side of the package substrate, wherein the second side of the package substrate is relative to the first side of the package substrate; and an annular structure located on the second side of the package substrate, the annular structure extending around the periphery of the ball grid array, wherein the annular structure has a first height different from a second height of the ball grid array. In one embodiment, the interposer element-on-a-die includes a high-bandwidth memory (HBM) stack, a system-on-a-die (SoC) element, or a system-on-a-die (SoIC) element. In one embodiment, the coefficient of thermal expansion of the annular structure is different from the coefficient of thermal expansion of the package substrate. In one embodiment, the annular structure includes copper, aluminum, cobalt, or nickel. In one embodiment, the annular structure has a polygonal geometry in a top view, wherein the sidewalls of the polygonal geometry include an edge having a first height and at least one opening in the sidewall having a third height, wherein the third height is less than the first height. In one embodiment, the at least one opening in the sidewall is a single opening extending from a first corner of the sidewall to a second corner of the sidewall. In one embodiment, the annular structure has a first thickness at the first corner and the second corner, and a second thickness at the sidewall portion between the first corner and the second corner, wherein the first thickness is greater than the second thickness.

[0056] According to another embodiment, an apparatus includes a wafer-on-a-substrate structure located on a first side of a package substrate; a first annular structure located on the first side of the package substrate, wherein the first annular structure extends around the periphery of the wafer-on-a-substrate structure; a cap located on the first annular structure; an array of connectors located on a second side of the package substrate, wherein the second side of the package substrate is relative to the first side of the package substrate; and a second annular structure located on the second side of the package substrate, the second annular structure extending around the periphery of the array of connectors. In one embodiment, the array of connectors includes a ball grid array, and the second annular structure has a first height smaller than a second height of the ball grid array. In one embodiment, the second annular structure has a coefficient of thermal expansion ranging from 10 ppm / ˚C to 25 ppm / ˚C. In one embodiment, the second annular structure includes copper, aluminum, cobalt, or nickel. In one embodiment, the cap includes copper, aluminum, cobalt, or nickel.

[0057] The features of several embodiments have been summarized above to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0005] The various aspects of this disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figures 1 to 13 show views of intermediate stages in the manufacture of an integrated circuit package according to some embodiments. Figure 14 shows an embodiment of an integrated circuit package in an electronic device according to some embodiments.

Claims

1. A method for forming an integrated circuit package, comprising: Bonding the interposer element onto the package substrate; Join a first annular structure to a first side of the package substrate, wherein the first annular structure extends around the periphery of the wafer on the interposer element; Join a cap to the first annular structure and the wafer on the interposer element; An array of connectors is formed on a second side of the packaging substrate, wherein the second side of the packaging substrate is relative to the first side of the packaging substrate; and engaging a second annular structure to the second side of the encapsulation substrate, wherein the second annular structure extends around the periphery of the array of connectors, wherein the second annular structure has a coefficient of thermal expansion ranging from 10 ppm / ˚C to 25 ppm / ˚C.

2. The method of claim 1, wherein attaching the second annular structure to the second side of the packaging substrate comprises attaching the second annular structure to the second side of the packaging substrate via an adhesive layer.

3. An integrated circuit package, comprising: Packaging substrate; Intermediate layer element-on-wafer, on the first side of the package substrate; A ball grid array on a second side of the packaging substrate, wherein the second side of the packaging substrate is relative to the first side of the packaging substrate; And an annular structure, on the second side of the encapsulation substrate, the annular structure extending around the periphery of the ball grid array, wherein the annular structure has a first height different from the second height of the ball grid array, and wherein the annular structure has a coefficient of thermal expansion ranging from 10 ppm / ˚C to 25 ppm / ˚C.

4. The integrated circuit package as claimed in claim 3, wherein the coefficient of thermal expansion of the annular structure is different from the coefficient of thermal expansion of the package substrate.

5. The integrated circuit package as claimed in claim 3, wherein the annular structure comprises copper, aluminum, cobalt, or nickel.

6. The integrated circuit package as claimed in claim 3, wherein the annular structure has a polygonal geometry in a top view, wherein the sidewalls of the polygonal geometry include an edge having a first height and at least one opening having a third height in the sidewalls, wherein the third height is less than the first height.

7. The integrated circuit package as claimed in claim 6, wherein the at least one opening in the sidewall is a single opening extending from a first corner of the sidewall to a second corner of the sidewall.

8. The integrated circuit package as claimed in claim 7, wherein the annular structure has a first thickness at the first corner and the second corner, and a second thickness in the sidewall portion between the first corner and the second corner, and wherein the first thickness is greater than the second thickness.

9. An integrated circuit package, comprising: On-substrate wafer structure, on the first side of the packaging substrate; A first annular structure on the first side of the packaging substrate, wherein the first annular structure extends around the periphery of a wafer structure on the substrate; a cap on the first annular structure; and an array of connectors on the second side of the packaging substrate, wherein the second side of the packaging substrate is relative to the first side of the packaging substrate. And a second annular structure, on the second side of the encapsulation substrate, the second annular structure extending around the periphery of the array of connectors, wherein the second annular structure has a coefficient of thermal expansion ranging from 10 ppm / ˚C to 25 ppm / ˚C.

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