Level shifter circuit
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- RAYDIUM SEMICON
- Filing Date
- 2025-04-02
- Publication Date
- 2026-08-01
Smart Images
Figure TWG2TB001903894_001 
Figure TWG2TB001903894_002 
Figure TWG2TB001903894_003
Abstract
Claims
1. A level shifter circuit, comprising: a first transistor controlled by an input signal; an enabling transistor controlled by a control signal and coupled to the first transistor via a first node; a second transistor, the gate of which is coupled to the first node; a third transistor, the gate of which is coupled to the first node and the third transistor is coupled to the second transistor via a first output node; a fourth transistor, the gate of which is coupled to the first output node; a fifth transistor, the gate of which is coupled to the first output node and the fifth transistor is coupled to the fourth transistor via a second output node; and a feedback transistor controlled by the control signal and coupled between the first node and the second output node; wherein during a write phase, the control signal turns on the enabling transistor and turns off the feedback transistor.
2. The level shifter circuit as claimed in claim 1 further comprises: a sixth transistor controlled by a first bias voltage and coupled to the end of the enabling transistor that is not coupled to the first node.
3. The level shifter circuit as claimed in claim 2 further comprises: a seventh transistor controlled by a second bias voltage and coupled between the first node and the first transistor.
4. The level shifter circuit as described in claim 1, wherein the control signal has a first on-time and the input signal has a second on-time greater than the first on-time.
5. The level shifter circuit as described in claim 1, wherein a first on-time of the control signal does not lag behind a second on-time of the input signal.
6. The level shifter circuit as claimed in claim 1, wherein in an initial phase, the control signal turns off the enable transistor and turns on the feedback transistor.
7. The level shifter circuit as claimed in claim 1, wherein during a latching phase, the control signal turns off the enable transistor and turns on the feedback transistor.
8. A level shifter circuit, comprising: an input stage configured to receive an input signal and an operating voltage, and to provide the operating voltage to a first node according to the input signal and a control signal; a first inverter, a first input terminal of the first inverter being coupled to the first node; and a second inverter, a second input terminal of the second inverter being coupled to a first output terminal of the first inverter. A power-receiving crystal, controlled by the control signal, is coupled to the first node and a second output terminal of the second inverter; And a power transistor, controlled by the control signal and coupled between the operating voltage and the input stage, wherein during a write phase, the control signal turns on the power transistor and turns off the feedback transistor.
9. The level shifter circuit as claimed in claim 8, wherein the control signal has a first on-time and the input signal has a second on-time greater than the first on-time.
10. The level shifter circuit as described in claim 8, wherein a first on-time of the control signal does not lag behind a second on-time of the input signal.
11. The level shifter circuit as claimed in claim 8, wherein in an initial phase, the control signal turns off the enable transistor and turns on the feedback transistor.
12. The level shifter circuit as claimed in claim 8, wherein during a latching phase, the control signal turns off the enable transistor and turns on the feedback transistor.