Nitride semiconductor device and manufacturing method of nitride semiconductor device

Abstract

This application provides a nitride semiconductor device, including a substrate, a channel layer, a first polarization layer, a polarization control layer, and a second polarization layer. The channel layer is disposed on the substrate, the first polarization layer is disposed on the channel layer, the polarization control layer is disposed on the first polarization layer, and the second polarization layer is disposed on the polarization control layer. The lattice constants of the first polarization layer and the second polarization layer are smaller than the lattice constant of the polarization control layer. The two-dimensional electron gas of the channel layer is adjusted through the arrangement of the first polarization layer, the polarization control layer, and the second polarization layer.

Claims

1. A nitride semiconductor device, comprising: One substrate; A channel layer is disposed on the substrate; A first polarization layer is disposed on the channel layer; A first spacer layer is disposed between the first polarization layer and the channel layer; a polarization control layer is disposed on the first polarization layer; a second polarization layer is disposed on the polarization control layer; and a second spacer layer is disposed between the polarization control layer and the second polarization layer; wherein the lattice constants of the first polarization layer and the second polarization layer are smaller than the lattice constant of the polarization control layer.

2. The nitride semiconductor device as claimed in claim 1, wherein the material of the first polarization layer, the material of the polarization control layer, and the material of the second polarization layer are aluminum gallium nitride, and the aluminum ratio of the first polarization layer and the aluminum ratio of the second polarization layer are greater than the aluminum ratio of the polarization control layer.

3. The nitride semiconductor device as claimed in claim 1, further comprising: At least one buffer layer is disposed between the substrate and the channel layer; And a back barrier layer, disposed on at least one of the buffer layers.

4. The nitride semiconductor device as claimed in claim 1, further comprising: A cap layer is disposed on the second polarization layer.

5. The nitride semiconductor device as claimed in claim 4, wherein, The first spacer layer, the first polarization layer, the polarization control layer, the second spacer layer, the second polarization layer, and the cap layer form a platform structure, which exposes the channel layer. The nitride semiconductor device further includes: a first passivation layer disposed on the platform structure; a drain electrode disposed on one side of the platform structure and located on the first passivation layer, extending from the first passivation layer to the channel layer; and a source electrode disposed on the other side of the platform structure and located on the first passivation layer, extending from the first passivation layer to the channel layer.

6. The nitride semiconductor device as claimed in claim 5, wherein, The drain includes a first extension and a first electrode portion. The first extension extends from the first passivation layer to the channel layer. The first electrode portion is disposed on the first passivation layer and penetrates the first passivation layer to connect with the first extension. The source includes a second extension and a second electrode portion. The second extension extends from the first passivation layer to the channel layer. The second electrode portion is disposed on the first passivation layer and penetrates the first passivation layer to connect with the second extension. The materials of the first extension and the second extension include n-type gallium nitride, n-type gallium indium nitride, or a metal material.

7. The nitride semiconductor device as claimed in claim 5, further comprising: A second passivation layer is disposed on the first passivation layer and has an opening that extends to the second spacer layer; A gate insulating layer is disposed on the second passivation layer, and a portion of the gate insulating layer is disposed in the opening; and a gate is disposed in the opening and electrically insulated from the second spacer layer through the gate insulating layer.

8. The nitride semiconductor device as claimed in claim 7 further includes an oxide layer disposed at the bottom of the opening, and the gate insulating layer located on the oxide layer.

9. The nitride semiconductor device as claimed in claim 7, further comprising: An inter-dielectric layer is disposed on the gate and located on the gate insulating layer; A plurality of first metal pins are disposed on the interlayer dielectric layer and penetrate the interlayer dielectric layer, the gate insulating layer and the second passivation layer to connect the drain and the source.

10. The nitride semiconductor device as claimed in claim 9, further comprising: An inter-metal dielectric layer is disposed on the inter-metal dielectric layer; a plurality of second metal pins are disposed on the inter-metal dielectric layer and penetrate the inter-metal dielectric layer to connect the plurality of first metal pins; and a third passivation layer is disposed on the inter-metal dielectric layer and exposes the plurality of second metal pins.

11. The nitride semiconductor device as claimed in claim 4, wherein the thickness of the cap layer is less than the thickness of the second polarization layer.

12. The nitride semiconductor device as claimed in claim 11, wherein, The thickness of the channel layer is greater than the thickness of the polarization control layer, and the thickness of the polarization control layer is greater than the thickness of the first polarization layer.

13. The nitride semiconductor device as claimed in claim 1 or 12, wherein, The thickness of the first spacer layer is less than the thickness of the first polarization layer and the thickness of the channel layer, and the thickness of the second spacer layer is less than the thickness of the polarization control layer and the thickness of the second polarization layer.

14. The nitride semiconductor device as claimed in claim 4, further comprising: A passivation layer is disposed on the cap layer and has an opening that extends to the second spacer layer; A gate insulating layer is disposed on the passivation layer, and a portion of the gate insulating layer is disposed in the opening; and a gate is disposed in the opening and electrically insulated from the second spacer layer through the gate insulating layer.

15. The nitride semiconductor device of claim 14 further includes an oxide layer disposed at the bottom of the opening, and the gate insulating layer located on the oxide layer.

16. The nitride semiconductor device as claimed in claim 14, further comprising: An interlayer dielectric layer is disposed on the gate and located on the gate insulating layer; a plurality of first metal pins are disposed on the interlayer dielectric layer and penetrate the interlayer dielectric layer, the gate insulating layer and the passivation layer to connect the drain and the source respectively.

17. The nitride semiconductor device as claimed in claim 16, further comprising: An inter-metal dielectric layer is disposed on the inter-metal dielectric layer; a plurality of second metal pins are disposed on the inter-metal dielectric layer and penetrate the inter-metal dielectric layer to connect the plurality of first metal pins; and a third passivation layer is disposed on the inter-metal dielectric layer and exposes the plurality of second metal pins.

18. A method for manufacturing a nitride semiconductor device, comprising: A channel layer, a first spacer layer, a first polarization layer, a polarization control layer, a second spacer layer, a second polarization layer, and a cap layer are sequentially formed on a substrate; the channel layer, the first spacer layer, the first polarization layer, the polarization control layer, the second spacer layer, the second polarization layer, and the cap layer are partially etched to form a platform structure, wherein the platform structure exposes the channel layer; a first passivation layer, a drain, and a source are formed on the platform structure and on both sides of the platform structure, wherein the drain and the source are located on the first passivation layer and extend from the first passivation layer to the channel layer; a second passivation layer is formed on the first passivation layer, and the second passivation layer is partially etched to give the second passivation layer an opening, wherein the opening extends to the second spacer layer; a gate insulating layer is formed on the second passivation layer and in the opening; and a gate is formed on the gate insulating layer.

19. The method of manufacturing a nitride semiconductor device as claimed in claim 18, further comprising, prior to the step of forming the channel layer, the first spacer layer, the first polarization layer, the polarization control layer, the second spacer layer, the second polarization layer, and the cap layer on the substrate: At least one buffer layer and one back barrier layer are sequentially formed on the substrate.

20. A method for manufacturing a nitride semiconductor device as claimed in claim 18, comprising forming the first passivation layer, the drain, and the source on the platform structure and on both sides of the platform structure, comprising: A first extension and a second extension are formed on both sides of the platform structure; The first passivation layer is formed on the platform structure, the first extension, and the second extension; the first passivation layer is partially etched to expose the first extension and the second extension; a first electrode portion and a second electrode portion are formed on the first extension and the second extension, respectively, wherein the first electrode portion and the first extension constitute the drain electrode, and the second electrode portion and the second extension constitute the source electrode.

21. The method of manufacturing a nitride semiconductor device as described in claim 18, further comprising: An oxide layer is formed at the bottom of the opening, wherein the gate insulating layer is located on the oxide layer.

22. The method of manufacturing a nitride semiconductor device as described in claim 18 further comprises: A dielectric layer is formed on the gate and the gate insulating layer; Partial etching of the interlayer dielectric layer is performed to expose the drain and the source. And to form a plurality of first metal plugs to connect the drain and the source.

23. The method of manufacturing a nitride semiconductor device as described in claim 22 further comprises: A metal interlayer dielectric layer is formed on the interlayer dielectric layer and on the plurality of the first metal pins; Partial etching of the intermetallic dielectric layer exposes a plurality of the first metal pins; a plurality of second metal pins are formed to connect the plurality of the first metal pins; A third passivation layer is formed on the plurality of the second metal pins and the inter-metal dielectric layer, and the third passivation layer is partially etched to expose the plurality of the second metal pins.

24. A method for manufacturing a nitride semiconductor device, comprising: A channel layer, a first spacer layer, a first polarization layer, a polarization control layer, a second spacer layer, and a second polarization layer are sequentially formed on a substrate; the channel layer, the first spacer layer, the first polarization layer, the polarization control layer, the second spacer layer, and the second polarization layer are partially etched to form a platform structure, wherein the platform structure exposes the channel layer; a passivation layer, a drain, and a source are formed on the platform structure and on both sides of the platform structure, wherein the drain and the source are located on the passivation layer and extend from the passivation layer to the channel layer; the passivation layer is partially etched to give the passivation layer an opening, wherein the opening extends to the second spacer layer; and a gate is formed in the opening.

25. The method of manufacturing a nitride semiconductor device as claimed in claim 24, further comprising, prior to the step of forming the gate: A gate insulating layer is formed on the passivation layer and in the opening, so that the gate is formed on the gate insulating layer.

26. A method for manufacturing a nitride semiconductor device as claimed in claim 24, comprising forming the passivation layer, the drain, and the source on the platform structure and on both sides of the platform structure, comprising: A first extension and a second extension are formed on both sides of the platform structure; The passivation layer is formed on the platform structure, the first extension, and the second extension; the passivation layer is partially etched to expose the first extension and the second extension; a first electrode portion and a second electrode portion are formed on the first extension and the second extension, respectively, wherein the first electrode portion and the first extension constitute the drain electrode, and the second electrode portion and the second extension constitute the source electrode.

27. The method of manufacturing a nitride semiconductor device as described in claim 24, further comprising: An oxide layer is formed at the bottom of the opening, wherein the gate insulating layer is located on the oxide layer.

28. The method of manufacturing a nitride semiconductor device as described in claim 24, further comprising: A dielectric layer is formed on the gate and the gate insulating layer; Partial etching of the interlayer dielectric layer is performed to expose the drain and the source. And to form a plurality of first metal plugs to connect the drain and the source.

29. The method of manufacturing a nitride semiconductor device as described in claim 28 further comprises: A metal interlayer dielectric layer is formed on the interlayer dielectric layer and on the plurality of the first metal pins; Partial etching of the intermetallic dielectric layer exposes a plurality of the first metal pins; a plurality of second metal pins are formed to connect the plurality of the first metal pins; A third passivation layer is formed on the plurality of the second metal pins and the inter-metal dielectric layer, and the third passivation layer is partially etched to expose the plurality of the second metal pins.

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