Testing circuitry and methods for analog neural memory in artificial neural network

Abstract

This invention discloses test circuitry and methods for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises an array of one or more non-volatile memory cells. The test circuitry and methods can be used to verify the programmed operation of one or more cells during classification tests, pass / fail tests, and other tests.

Description

Technical Field

[0001] [PRIORITY CLAIM] This application claims priority to U.S. Provisional Patent Application No. 62 / 876,515, filed on July 19, 2019, entitled “Testing Circuitry and Methods for Analog Neural Memory in Artificial Neural Network,” and U.S. Patent Application No. 16 / 569,647, filed on September 12, 2019, entitled “Testing Circuitry and Methods for Analog Neural Memory in Artificial Neural Network.”

[0002] A test circuit and method for an analog neural memory used in a deep learning artificial neural network are disclosed. The analog neural memory includes one or more non-volatile flash memory cell arrays. Prior Art

[0003] Artificial neural networks (ANNs) simulate biological neural networks (the central nervous system of animals, particularly the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are often unknown. ANNs typically consist of layers of interconnected "neurons" that can exchange information with each other.

[0004] Figure 1 illustrates an artificial neural network, where circles represent neuronal inputs or layers. Connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the neural network to adapt to the input and learn. Typically, a neural network consists of a layer with multiple inputs. There are typically one or more intermediate layers of neurons and an output layer of neurons that provides the network's output. Neurons in each layer make decisions individually or collectively based on the data they receive from their synapses.

[0005] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of adequate hardware technology. Practical neural networks rely on extremely large numbers of synapses to enable high connectivity between neurons (i.e., very high computational parallelism). In principle, such complexity could be achieved using digital supercomputers or clusters of dedicated graphics processing units. However, in addition to high costs, these approaches suffer from mediocre energy efficiency compared to biological networks, which consume very little energy, primarily because they perform low-precision analog computations. CMOS analog circuits have been used in artificial neural networks, but given the large number of neurons and synapses required, the synapses in most CMOS implementations are too large.

[0006] Applicant previously disclosed in U.S. Patent Application No. 15 / 594,439 (published as U.S. Patent Publication No. 2017 / 0337466), which is hereby incorporated by reference, an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses. The non-volatile memory array operates as an analog neural memory. The neural network device includes a plurality of first synapses configured to receive a plurality of first inputs and thereby generate a plurality of first outputs; and a plurality of first neurons configured to receive the plurality of first outputs. The plurality of first synapses include a plurality of memory cells, each of which includes spaced-apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween; a floating gate disposed over and insulated from a first portion of the channel region; and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on a floating gate. The plurality of memory cells are configured to multiply a plurality of first inputs by the stored weight values ​​to generate a plurality of first outputs. A memory cell array used in this manner may be referred to as a vector-matrix multiplication (VMM) array.

[0007] Each non-volatile memory cell used in an analog neural memory system must be erased and programmed to maintain a very specific and precise charge level, or number of electrons, in the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0008] Precision and accuracy are crucial in operations involving VMM arrays because each individual memory cell can store one of N different levels, where N can be greater than 2, as opposed to traditional memory cells, where N is always 2. This makes testing an extremely important operation. For example, verification of programming operations is required to ensure that each individual cell or row of cells is accurately programmed to the expected value. As another example, identifying bad cells or groups of cells is crucial so that they can be removed from the set of cells used to store data during VMM array operations.

[0009] What are needed are improved testing circuits and methods for VMM arrays. Summary of the Invention

[0010] Disclosed are test circuits and methods for analog neural memories used in deep learning artificial neural networks. The analog neural memories include one or more arrays of non-volatile flash memory cells. The test circuits and methods can be used to verify the characteristics and operability of one or more cells during classification testing, cycling testing, high-temperature operating life (HTOL) testing, qualification testing, and other testing.

[0011] One embodiment includes a method for verifying values ​​within a plurality of non-volatile memory cells in an array of non-volatile memory cells programmed as analog neural networks, wherein the array is arranged in columns and rows, wherein each column is coupled to a word line and each row is coupled to a bit line, and wherein each word line is selectively coupled to a column decoder and each bit line is selectively coupled to a row decoder, the method comprising: asserting all word lines in the array by the column decoder; asserting a bit line in the array by the row decoder; sensing a current received from the bit line by a sense amplifier; and comparing the current to a reference current to determine whether the non-volatile memory cells coupled to the bit line contain an expected value.

[0012] Another embodiment includes a method of measuring current drawn by a plurality of non-volatile memory cells in an array of analog neural non-volatile memory cells, wherein the array is arranged in columns and rows, wherein each column is coupled to a word line and each row is coupled to a bit line, and wherein each word line is selectively coupled to a column decoder and each bit line is selectively coupled to a row decoder, the method comprising: asserting all word lines in the array by the column decoder; asserting a bit line in the array by the row decoder; and measuring the current received from the bit line.

[0013] Another method includes a method of testing a plurality of analog neural non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in columns and rows, wherein each column is coupled to a word line and each row is coupled to a bit line, and wherein each word line is selectively coupled to a column decoder and each bit line is selectively coupled to a row decoder, the method comprising: asserting all word lines in the array by the column decoder; asserting all bit lines in the array by the row decoder; performing a deep programming operation on all non-volatile memory cells in the array; and measuring a total current received from the bit lines.

[0014] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, wherein the array is arranged in columns and rows, wherein each column is coupled to a word line and each row is coupled to a bit line, the method comprising: programming a plurality of cells coupled to a bit line; measuring a current drawn by the plurality of cells at K different times and storing each measurement value at the K different times, where K is an integer; calculating an average value based on the K measurements; and identifying the bit line as a bad bit line if any of the K measurements is less than the average value by more than a first threshold value or greater than the average value by more than a second threshold value.

[0015] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, wherein the array is arranged in columns and rows, wherein each column is coupled to a word line and each row is coupled to a bit line, the method comprising: programming a plurality of cells coupled to a bit line; measuring a voltage on a control gate line coupled to a control gate terminal of the plurality of cells at K different times and storing each measurement value at the K different times, where K is an integer; calculating an average value based on the K measurements; and identifying the bit line as a bad bit line if any of the K measurements is less than the average value by more than a first threshold value or greater than the average value by more than a second threshold value.

[0016] Another embodiment includes a method of testing an analog neural non-volatile memory cell for storing N different values, where N is an integer, the method comprising: programming the cell to a target value representing one of the N values; verifying that the value stored in the cell is within an acceptable range of values ​​about the target value; repeating the programming and reading steps for each of the N values; and identifying the cell as defective if any of the verification steps indicates that the value stored in the cell is outside the acceptable range of values ​​about the target value.

[0017] Another embodiment includes a method of compensating for leakage current in an array of analog neural non-volatile memory cells, wherein the array is arranged in columns and rows, wherein each column is coupled to a word line and each row is coupled to a bit line, the method comprising: measuring leakage current of a row of non-volatile memory cells coupled to a bit line; storing the measured leakage current value; and applying the measured leakage current value during a read operation of the row of non-volatile memory cells to compensate for the leakage current.

[0018] Another embodiment includes a method for testing a selected non-volatile memory cell in an analog neural non-volatile memory cell array, the method comprising: determining a logarithmic slope factor for the selected non-volatile memory cell when the selected non-volatile memory cell is operating in a subcritical region; storing the logarithmic slope factor; determining a linear slope factor for the selected non-volatile memory cell when the selected non-volatile memory cell is operating in a linear region; storing the linear slope factor; and utilizing one or both of the logarithmic slope factor and the linear slope factor when programming the selected cell to a target current.

[0019] Another embodiment includes a method of measuring current drawn by a row of non-volatile memory cells in an array of analog neural non-volatile memory cells, wherein the array is arranged in columns and rows, wherein each column is coupled to a word line and each row is coupled to a bit line, and wherein each word line is selectively coupled to a column decoder and each bit line is selectively coupled to a row decoder, the method comprising: asserting all word lines in the array by the column decoder; asserting a bit line in the array by the row decoder to select a row of non-volatile memory cells; and measuring the current received from the bit line.

[0020] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, the method comprising: erasing the non-volatile memory cells in the array by applying a voltage sequence to a terminal of each non-volatile memory cell in the array, wherein the voltage in the voltage sequence increases over time at a fixed step; and reading all non-volatile memory cells to determine the effectiveness of the erase step.

[0021] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, the method comprising: programming the non-volatile memory cells in the array by applying a voltage sequence to a terminal of each non-volatile memory cell in the array, wherein the voltage in the voltage sequence increases over time at a fixed step; and reading all non-volatile memory cells to determine the effectiveness of the programming step.

[0022] Another embodiment includes a method of testing a plurality of analog neural non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each column is coupled to a word line and each row is coupled to a bit line, and wherein each word line is selectively coupled to a column decoder and each bit line is selectively coupled to a row decoder, the method comprising: programming a plurality of non-volatile memory cells to store one of N different values, wherein N is the number of different levels that can be stored in any one of the non-volatile memory cells; measuring current drawn by the plurality of non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of non-volatile memory cells as defective if the difference between the measured value and the target value exceeds a threshold value.

[0023] Another embodiment includes a method of testing a plurality of analog neural non-volatile memory cells in a non-volatile memory cell array, wherein the memory array is arranged in rows and columns, wherein each column is coupled to a word line and each row is coupled to a bit line, and wherein each word line is selectively coupled to a column decoder and each bit line is selectively coupled to a row decoder, the method comprising: programming one of the plurality of non-volatile memory cells at a level among N levels corresponding to a minimum cell current; The invention relates to a first selection unit; programming second selection units of the plurality of non-volatile memory cells at a level corresponding to a maximum cell current among the N levels, wherein each unit of the second selection units is adjacent to one or more units of the first selection units; measuring the current drawn by the plurality of non-volatile memory cells; comparing the measured current with a target value; and identifying the plurality of non-volatile memory cells as defective if the difference between the measured value and the target value exceeds a threshold value. Simple diagram description

[0024] FIG1 is a schematic diagram illustrating an artificial neural network according to the prior art.

[0025] FIG. 2 illustrates a prior art split-gate flash memory cell.

[0026] FIG. 3 illustrates another prior art split-gate flash memory cell.

[0027] FIG. 4 illustrates another prior art split-gate flash memory cell.

[0028] FIG. 5 illustrates another prior art split-gate flash memory cell.

[0029] FIG. 6 illustrates another prior art split-gate flash memory cell.

[0030] FIG. 7 depicts a prior art stacked-gate flash memory cell.

[0031] FIG8 is a schematic diagram illustrating different levels of an exemplary artificial neural network utilizing one or more non-volatile memory arrays.

[0032] FIG9 is a block diagram illustrating a vector-matrix multiplication system.

[0033] FIG10 is a block diagram illustrating an exemplary artificial neural network utilizing one or more vector-matrix multiplication systems.

[0034] FIG11 depicts another specific example of a vector-matrix multiplication system.

[0035] FIG12 depicts another specific example of a vector-matrix multiplication system.

[0036] FIG13 depicts another specific example of a vector-matrix multiplication system.

[0037] FIG14 depicts another specific example of a vector-matrix multiplication system.

[0038] FIG15 depicts another specific example of a vector-matrix multiplication system.

[0039] FIG16 depicts another specific example of a vector-matrix multiplication system.

[0040] FIG17 depicts another specific example of a vector-matrix multiplication system.

[0041] FIG18 depicts another specific example of a vector-matrix multiplication system.

[0042] FIG19 depicts another specific example of a vector-matrix multiplication system.

[0043] FIG20 depicts another specific example of a vector-matrix multiplication system.

[0044] FIG21 depicts another specific example of a vector-matrix multiplication system.

[0045] FIG22 depicts another specific example of a vector-matrix multiplication system.

[0046] FIG23 depicts another specific example of a vector-matrix multiplication system.

[0047] FIG24 depicts another specific example of a vector-matrix multiplication system.

[0048] Figure 25 depicts a specific example of a vector-matrix multiplication system including test control logic.

[0049] FIG26 depicts a reference current source.

[0050] FIG27 depicts a reference subcircuit for the reference current source of FIG26.

[0051] FIG28 depicts a sense amplifier.

[0052] FIG. 29A depicts verification of an analog-to-digital converter.

[0053] FIG. 29B depicts verification of the analog-to-digital converter.

[0054] FIG30 depicts a high voltage generating circuit.

[0055] FIG31 depicts an exemplary test algorithm implemented by the test control logic in a vector-matrix multiplication system.

[0056] FIG32 depicts a specific example of a bit line neural read test.

[0057] FIG33 depicts a specific example of a bit-line neurometric test.

[0058] FIG34 depicts a specific example of an LSB screening test.

[0059] FIG. 35 depicts a specific example of a bit line sampling screening test.

[0060] FIG. 36 depicts another embodiment of a bit line sampling screening test.

[0061] FIG37 depicts a specific example of a read window check test.

[0062] FIG. 38 depicts a specific example of a read correction test.

[0063] FIG39 depicts a specific example of a read slope test.

[0064] FIG40 depicts a specific example of a read neuron qualification test.

[0065] FIG41 depicts a specific example of a soft erase test.

[0066] FIG42 depicts a specific example of soft programming testing.

[0067] FIG43 depicts a specific example of a verification test.

[0068] FIG44 depicts a specific example of a checkerboard verification test. Implementation Method

[0069] The artificial neural network of the present invention utilizes a combination of CMOS technology and a non-volatile memory array. Non-volatile memory unit

[0070] Digital non-volatile memory systems are well known. For example, U.S. Patent No. 5,029,130 ​​(the "'130 patent") discloses an array of split-gate non-volatile memory cells (flash memory cells) and is incorporated herein by reference. Such a memory cell 210 is shown in FIG. 2 . Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A wordline terminal 22 (typically coupled to a wordline) has a first portion and a second portion, wherein the first portion is disposed over and insulated from (and controls the conductivity of) the second portion of the channel region 18, and the second portion extends upward and over the floating gate 20. The floating gate 20 and wordline terminal 22 are insulated from the substrate 12 by a gate oxide. The bit line terminal 24 is coupled to the drain region 16 .

[0071] The memory cell 210 is erased (where electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22 , which causes the electrons on the floating gate 20 to tunnel from the floating gate 20 through the intermediate insulator to the word line terminal 22 via Fowler-Nordheim tunneling.

[0072] Memory cell 210 is programmed (where electrons are placed on the floating gate) by applying a positive voltage to wordline terminal 22 and a positive voltage to source region 14. Electrons flow from source region 14 (source line terminal) to drain region 16. When electrons reach the gap between wordline terminal 22 and floating gate 20, they accelerate and heat up. Due to the electrostatic attraction from floating gate 20, some of the heated electrons are injected through the gate oxide onto floating gate 20.

[0073] Memory cell 210 is read by applying a positive read voltage to drain region 16 and wordline terminal 22 (which turns on the portion of channel region 18 beneath the wordline terminal). If floating gate 20 is positively charged (i.e., erased of electrons), the portion of channel region 18 beneath floating gate 20 is also turned on, and current flows through channel region 18, which is sensed as an erased state or state "1." If floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region beneath floating gate 20 is mostly or completely off, and current does not flow (or barely flows) through channel region 18, which is sensed as a programmed state or state "0."

[0074] Table 1 depicts typical voltage ranges that may be applied to the terminals of the memory cell 210 to perform read, erase, and program operations: [ , , ] [] [surface] [1] [:picture] [2] [Flash memory unit]

[0210] [Operation] [] WL BL SL Read 1 0.5-3V 0.1-2V 0V Read 2 0.5-3V 0-2V 2-0.1V Erase ~11-13V 0V 0V Programming 1-2V 1-3µA 9-10V "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0075] FIG3 shows a memory cell 310, which is similar to the memory cell 210 of FIG2 , but with the addition of a control gate (CG) terminal 28. During programming, control gate terminal 28 is biased at a high voltage, such as 10V. During erasing, control gate terminal 28 is biased at a low voltage, such as 0V / −8V, or a negative voltage. During reading, control gate terminal 28 is biased at a low voltage, such as 0V / 2.5V, or a mid-range voltage. Other terminals are biased similarly to FIG2 .

[0076] FIG4 depicts a four-gate memory cell 410 comprising a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 22 over a second portion of the channel region 18 (typically coupled to a word line WL), a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Patent No. 6,747,310, which is incorporated herein by reference for all purposes. Here, except for the floating gate 20, all other gates are non-floating, meaning they are electrically connected or connectable to a voltage source. Programming is performed by injecting heated electrons from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0077] Table 2 depicts typical voltage ranges that may be applied to the terminals of the memory cell 410 to perform read, erase, and program operations: [surface] [2] [:picture] [4] [Flash memory unit]

[0410] [Operation] WL / SG BL CG EG SL Read 1 0.5-2V 0.1-2V 0-2.6V 0-2.6V 0V Read 2 0.5-2V 0-2V 0-2.6V 0-2.6V 2-0.1V Erase -0.5V / 0V 0V 0V / -8V 8-12V 0V Programming 1V 1µA 8-11V 4.5-9V 4.5-5V "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0078] FIG5 shows a memory cell 510, which is similar to the memory cell 410 of FIG4 , except that memory cell 510 does not include an erase gate EG terminal. Erasing is performed by biasing substrate 18 with a high voltage and control gate CG terminal 28 with a low or negative voltage. Alternatively, erasing is performed by biasing word line terminal 22 with a positive voltage and control gate terminal 28 with a negative voltage. Programming and reading are similar to those of FIG4 .

[0079] FIG6 depicts a 3-gate memory cell 610, another type of flash memory cell. Memory cell 610 is identical to memory cell 410 of FIG4 , except that it lacks a separate control gate terminal. Erase operations (using the erase gate terminal for erasing) and read operations are similar to those of FIG4 , except that no control gate bias is applied. Programming operations are also performed without a control gate bias. Consequently, a higher voltage must be applied to the source line terminal during programming operations to compensate for the lack of a control gate bias.

[0080] Table 3 depicts typical voltage ranges that may be applied to the terminals of memory cell 610 to perform read, erase, and program operations: [surface] [3] [:picture] [6] [Flash memory unit]

[0610] [Operation] WL / SG BL EG SL Read 1 0.5-2.2V 0.1-2V 0-2.6V 0V Read 2 0.5-2.2V 0-2V 0-2.6V 2-0.1V Erase -0.5V / 0V 0V 11.5V 0V Programming 1V 2-3µA 4.5V 7-9V "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0081] FIG7 depicts a stacked-gate memory cell 710, another type of flash memory cell. Memory cell 710 is similar to memory cell 210 of FIG2 , except that floating gate 20 extends over the entire channel region 18 and control gate terminal 22 (here coupled to a word line) extends over floating gate 20 and is separated by an insulating layer (not shown). Erase, programming, and read operations are performed in a manner similar to that previously described for memory cell 210.

[0082] Table 4 depicts typical voltage ranges that may be applied to the terminals of the memory cell 710 and the substrate 12 to perform read, erase, and program operations: [surface] [4] [:picture] [7] [Flash memory unit]

[0710] [Operation] [] CG BL SL substrate Read 1 0-5V 0.1–2V 0-2V 0V Read 2 0.5-2V 0-2V 2-0.1V 0V Erase -8 to -10V / 0V FLT FLT 8-10V / 15-20V Programming 8-12V 3-5V / 0V 0V / 3-5V 0V

[0083] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal. Optionally, in an array comprising columns and rows of memory cells 210, 310, 410, 510, 610, or 710, the source line can be coupled to a row of memory cells or two adjacent rows of memory cells. That is, the source line terminal can be shared by adjacent rows of memory cells.

[0084] To utilize a memory array comprising one of the aforementioned types of non-volatile memory cells in an artificial neural network, two modifications are implemented. First, as further described below, the circuitry is configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array. Second, continuous (analog) programming of the memory cells is provided.

[0085] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be independently and continuously changed from a fully erased state to a fully programmed state with minimal disruption to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be independently and continuously changed from a fully programmed state to a fully erased state, and vice versa, with minimal disruption to other memory cells. This means that the cell stores analog values, or at least can store one of many discrete values ​​(e.g., 16 or 64 different values), which allows very precise and individual adjustments to all cells in the memory array, and makes the memory array well-suited for storing and fine-tuning the synaptic weights of neural networks.

[0086] The methods and approaches described herein can be applied to other non-volatile memory technologies, such as, but not limited to, SONOS (silicon-oxide-nitride-oxide-silicon, charge trapping in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapping in nitride), ReRAM (resistive RAM), PCM (phase-change RAM), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), OTP (two-layer or multi-layer one-time programmable), and CeRAM (correlated electron RAM). The methods and approaches described herein can also be applied to volatile memory technologies used in neural networks, such as, but not limited to, SRAM, DRAM, and volatile synaptic cells. Neural networks using arrays of non-volatile memory cells

[0087] FIG8 conceptually illustrates a non-limiting example of a neural network utilizing the non-volatile memory array of the present embodiment. This example uses the non-volatile memory array neural network for a facial recognition application, but any other suitable application can be implemented using a non-volatile memory array-based neural network.

[0088] S0 is the input layer, which, for this example, is a 32×32 pixel RGB image with 5-bit precision (i.e., three 32×32 pixel arrays, one for each color R, G, and B, with 5 bits of precision per pixel). Synapse CB1 from input layer S0 to layer C1 applies different sets of weights in some cases and shared weights in others, and scans the input image with a 3×3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel, as dictated by the model). Specifically, values ​​for 9 pixels in a 3×3 portion of the image (i.e., called a filter or kernel) are provided to synapse CB1, where these 9 input values ​​are multiplied by the appropriate weights. After calculating the sum of the multiplication outputs, a single output value is determined and provided by the first synapse of CB1 to generate a pixel in one of the several layers of feature maps C1. The 3×3 filter is then shifted one pixel to the right within input layer S0 (i.e., the row of three pixels on the right is added and the row of three pixels on the left is discarded). The nine pixel values ​​from this newly positioned filter are then presented to synapse CB1, where they are multiplied by the same weights, and the second single output value is determined by the associated synapse. This process continues until the 3×3 filter has scanned the entire 32×32 pixel image of input layer S0 for all three colors and all bits (precision values). This process is then repeated using a different set of weights to produce a different feature map for C1, until all feature maps for layer C1 have been calculated.

[0089] In this example, layer C1 has 16 feature maps, each 30×30 pixels. Each pixel is a new feature pixel resulting from the multiplication of the input by the kernel, so each feature map is a two-dimensional array. Therefore, in this example, layer C1 comprises 16 layers of two-dimensional arrays (remember that the references to layers and arrays here are logical, not necessarily physical—that is, arrays are not necessarily oriented as physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all relate to different aspects of the same image feature, such as edge recognition. For example, the first map (generated using a first set of weights, shared by all scans used to generate it) can identify circular edges, while the second map (generated using a second set of weights, different from the first) can identify rectangular edges or the aspect ratio of certain features, and so on.

[0090] Before passing from layer C1 to layer S1, activation function P1 (pooling) is applied. This pooling function pools the values ​​from a continuous, non-overlapping 2×2 region in each feature map. The purpose of the pooling function is to average nearby locations (or alternatively, a maximum function) to reduce dependencies, such as at edges, and to reduce data size before entering the next stage. At layer S1, there are 16 15×15 feature maps (i.e., 16 different arrays, each with 15×15 pixels). Synapse CB2 from layer S1 to layer C2 scans the map in S1 using a 4×4 filter with a filter shift of one pixel. At layer C2, there are 22 12×12 feature maps. Before passing from layer C2 to layer S2, activation function P2 (pooling) is applied. This pooling function pools the values ​​from a continuous, non-overlapping 2×2 region in each feature map. At layer S2, there are 22 6×6 feature maps. An activation function (pooling) is applied at synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected to each graph in layer S2 via a separate synapse on CB3. Layer C3 has 64 neurons. Synapse CB4 from layer C3 to output layer S3 fully connects C3 to S3, meaning that every neuron in layer C3 is connected to every neuron in layer S3. The output from S3 consists of 10 neurons, with the highest output neuron determining the class. This output might, for example, represent the recognition or classification of the content of the original image.

[0091] Each layer of synapses is implemented using an array of non-volatile memory cells or a portion of an array of non-volatile memory cells.

[0092] FIG9 is a block diagram of a system that can be used for this purpose. A vector-matrix multiplication (VMM) array 32 includes non-volatile memory cells and serves as a synapse between one layer and the next (e.g., CB1, CB2, CB3, and CB4 in FIG6 ). Specifically, VMM array 32 includes a VMM array 33 (which includes non-volatile memory cells arranged in rows and columns), an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs of the non-volatile memory cell array 33. Inputs to VMM array 33 can come from either erase gate and word line gate decoder 34 or from control gate decoder 35. In this example, source line decoder 37 also decodes the output of VMM array 33. Alternatively, bit line decoder 36 can decode the output of VMM array 33.

[0093] VMM array 33 serves two purposes. First, it stores weights to be used by VMM system 32. Second, VMM array 33 efficiently multiplies inputs by the weights stored in VMM array 33 and adds them together according to the output lines (source lines or bit lines) to produce outputs, which will be the inputs for the next or final layer. By performing multiplication and addition functions, VMM array 33 eliminates the need for separate multiplication and addition logic circuits and is also power-efficient due to in-memory calculations.

[0094] The outputs of the VMM array 33 are supplied to a differential adder (e.g., a summing operational amplifier or a summing current mirror) 38, which sums the outputs of the VMM array 33 to produce a single value for convolution. The differential adder 38 is configured to sum the positive weighted inputs and the negative weighted inputs to output the single value.

[0095] The summed output value of the differential adder 38 is then supplied to the activation function circuit 39, which rectifies the output. The activation function circuit 39 can provide a sigmoid, tanh, ReLU function, or any other nonlinear function. The rectified output value of the activation function circuit 39 becomes an element of the feature map of the next layer (e.g., C1 in FIG8 ), and is then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the VMM array 33 constitutes a plurality of synapses (which receive their inputs from the previous neuron layer or from an input layer such as an image database), and the adder 38 and activation function circuit 39 constitute a plurality of neurons.

[0096] The inputs to the VMM system 32 in FIG9 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog levels, binary levels, digital pulses (in which case a pulse-to-analog converter, PAC, may be required to convert the pulses to the appropriate input analog levels), or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs can be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0097] Figure 10 is a block diagram depicting the use of multiple layers of VMM systems 32, labeled VMM systems 32a, 32b, 32c, 32d, and 32e. As shown in Figure 10, the input (denoted as Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be either voltage or current. Input D / A conversion for the first layer can be accomplished using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog level for the matrix multiplier of the input VMM system 32a. Input conversion can also be accomplished using an analog-to-analog (A / A) converter to convert external analog input into a mapped analog input for the input VMM system 32a. Input conversion can also be accomplished using a digital-to-digital pulse (D / P) converter to convert external digital input into a mapped digital pulse for the input VMM system 32a.

[0098] The output generated by input VMM system 32a is provided as input to the next VMM system (hidden layer 1) 32b, which in turn generates output that is provided as input to the next VMM system (hidden layer 2) 32c, and so on. The various layers of VMM systems 32 act as synapses and neurons in different layers of a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e can be a separate physical system including its own non-volatile memory array, or multiple VMM systems can utilize different portions of the same physical non-volatile memory array, or multiple VMM systems can utilize overlapping portions of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also time-multiplex portions of its array or neurons. The example shown in FIG10 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). A person skilled in the art will understand that this is merely exemplary and that the system may include more than two hidden layers and more than two fully connected layers. VMM array

[0099] FIG11 depicts a neuron VMM array 1100, which is particularly suitable for use with memory cells 310 shown in FIG3 and serves as a component for synapses between the input layer and the next layer to neurons. VMM array 1100 includes a memory array 1101 of non-volatile memory cells and a reference array 1102 of non-volatile reference memory cells (located above the array). Alternatively, another reference array can be placed below.

[0100] In VMM array 1100, control gate lines, such as control gate line 1103, run in the vertical direction (thus, reference array 1102 in the column direction is orthogonal to control gate line 1103), and erase gate lines, such as erase gate line 1104, run in the horizontal direction. Inputs to VMM array 1100 are provided on control gate lines (CG0, CG1, CG2, CG3), while outputs from VMM array 1100 appear on source lines (SL0, SL1). In one embodiment, only even-numbered columns are used, while in another embodiment, only odd-numbered columns are used. The current on each source line (SL0, SL1) performs a summation function of all currents from the memory cells connected to that particular source line.

[0101] As described herein with respect to neural networks, the non-volatile memory cells of the VMM array 1100 (ie, the flash memory of the VMM array 1100) are preferably configured to operate in a subcritical region.

[0102] Applying bias to the non-volatile reference memory cell and the non-volatile memory cell described herein in weak inversion: Ids=Io*e(Vg-Vth) / nVt=w*Io*e(Vg) / nVt, Where w=e(-Vth) / nVt Where Ids is the drain-to-source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the thermal voltage = k*T / q, where k is the Boltzmann constant, T is the Kelvin temperature, and q is the charge; n is the slope factor = 1+(Cdep / Cox), where Cdep = the capacitance of the depletion layer and Cox is the capacitance of the gate oxide layer; Io is the memory cell current when the gate voltage equals the threshold voltage. Io is proportional to (Wt / L)*u*Cox*(n-1)*Vt², where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0103] For an I to V logarithmic converter that uses a memory cell (e.g., a reference memory cell or a peripheral memory cell) or a transistor to convert an input current Ids to an input voltage Vg: Vg= n*Vt*log [Ids / wp*Io] Here, wp refers to the w of the reference or peripheral memory unit.

[0104] For an I to V logarithmic converter that uses a memory cell (e.g., a reference memory cell or a peripheral memory cell) or a transistor to convert an input current Ids to an input voltage Vg: Vg= n*Vt*log [Ids / wp*Io]

[0105] Here, wp refers to the w of the reference or peripheral memory unit.

[0106] For a memory array used as a vector-matrix multiplier (VMM) array, the output current is: Iout=wa*Io*e(Vg) / nVt, that is Iout=(wa / wp)*Iin=W*Iin W=e(Vthp-Vtha) / nVt Iin=wp*Io*e(Vg) / nVt Here, wa = w for each memory cell in the memory array.

[0107] The word line or control gate may be used as the input of the memory cell for the input voltage.

[0108] Alternatively, the non-volatile memory cells of the VMM array described herein may be configured to operate in the linear region: Ids=beta*(Vgs-Vth)*Vds;beta=u*Cox*Wt / L, Wα(Vgs-Vth), It indicates that the weight W in the linear region is proportional to (Vgs-Vth).

[0109] The word line or control gate or bit line or source line can be used as the input of the memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0110] For an I-to-V linear converter, a memory cell (eg, a reference memory cell or a peripheral memory cell) or a transistor or a resistor operating in a linear region can be used to linearly convert an input / output current into an input / output voltage.

[0111] Alternatively, the memory cells of the VMM array described herein may be configured to operate in the saturation region: Ids=½*beta*(Vgs-Vth)2;beta=u*Cox*Wt / L Wα(Vgs-Vth)2 indicates that the weight W is proportional to (Vgs-Vth)2.

[0112] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region. The bit line or source line can be used as the output of an output neuron.

[0113] Alternatively, memory cells of the VMM array described herein may be used in all regions or a combination thereof (subcritical, linear, or saturated).

[0114] Other embodiments of the VMM array 32 of FIG9 are described in U.S. patent application Ser. No. 15 / 826,345, which is incorporated herein by reference. As described in the aforementioned application, source lines or bit lines can be used as neuron outputs (current summing outputs).

[0115] FIG12 depicts a neuron VMM array 1200, which is particularly suitable for use with memory cell 210 shown in FIG2 and serves as a synapse between the input layer and the next layer. VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of first non-volatile reference memory cells, and a reference array 1202 of second non-volatile reference memory cells. Reference arrays 1201 and 1202, arranged in the row direction of the array, are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are connected to their current inputs in diode form via a multiplexer 1214 (only partially depicted). The reference cells are adjusted (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0116] Memory array 1203 serves two purposes. First, it stores weights on its individual memory cells that will be used by VMM array 1200. Second, memory array 1203 effectively multiplies inputs (i.e., current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3; reference arrays 1201 and 1202 convert these current inputs into input voltages for supply to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory array 1203. All results (memory cell currents) are then summed to produce outputs on individual bit lines (BL0-BLN), which will serve as inputs for the next or final layer. By performing multiplication and addition functions, memory array 1203 eliminates the need for separate multiplication and addition logic circuits and is also power-efficient. Here, voltage inputs are provided on word lines WL0, WL1, WL2, and WL3, and outputs appear on bit lines BL0-BLN during a read (inference) operation. The current on each of the bit lines BL0-BLN performs a summing function of the currents from all non-volatile memory cells connected to that particular bit line.

[0117] Table 5 depicts the operating voltages of VMM array 1200. The rows in the table represent the voltages on the word line of a selected cell, the word line of an unselected cell, the bit line of a selected cell, the bit line of an unselected cell, the source line of a selected cell, and the source line of an unselected cell, where FLT represents floating, i.e., no voltage applied. The columns represent read, erase, and program operations. [surface] [5] [:picture]

[12] [of] [VMM] [Array]

[1200] [Operation] [WL] [WL-unsel] [BL] [BL-unsel] [SL] [SL-unsel] [Read] 0.5-3.5V -0.5V / 0V 0.1-2V (I neuron) 0.6V-2V / FLT 0V 0V [ERASE] ~5-13V 0V 0V 0V 0V 0V [Stylized] 1-2V -0.5V / 0V 0.1-3 uA Vinh~2.5V 4-10V 0-1V / FLT

[0118] FIG13 depicts a neuron VMM array 1300, which is particularly suitable for use with memory cell 210 shown in FIG2 and serves as a component for synapsing neurons between the input layer and the next layer. VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 of first nonvolatile reference memory cells, and a reference array 1302 of second nonvolatile reference memory cells. Reference arrays 1301 and 1302 extend in the column direction of VMM array 1300. VMM array 1300 is similar to VMM 1100, except that the word lines extend vertically in VMM array 1300. Here, inputs are provided on word lines (WLA0, WLB0, WLA1, WLB1, WLA2, WLB2, WLA3, WLB3), and outputs appear on source lines (SL0, SL1) during read operations. The current on each source line performs a summing function of all the currents from the memory cells connected to that particular source line.

[0119] Table 6 depicts the operating voltages of the VMM array 1300. The rows in the table represent the voltages on the word line of a selected cell, the word line of an unselected cell, the bit line of a selected cell, the bit line of an unselected cell, the source line of a selected cell, and the source line of an unselected cell. The columns represent read, erase, and program operations. [] [surface] [6] [:picture]

[13] [of] [VMM] [Array]

[1300] [Operation] WL WL-unsel BL BL-unsel SL SL-unsel [Read] 0.5-3.5V -0.5V / 0V 0.1-2V 0.1V-2V / FLT ~0.3-1V (I neuron) 0V [ERASE] ~5-13V 0V 0V 0V 0V SL-Disable (~4-8V) [Stylized] 1-2V -0.5V / 0V 0.1-3 uA Vinh~2.5V 4-10V 0-1V / FLT

[0120] FIG14 depicts a neuron VMM array 1400, which is particularly suitable for use with memory cell 310 shown in FIG3 and serves as a component for synapsing neurons between the input layer and the next layer. VMM array 1400 includes a memory array 1403 of nonvolatile memory cells, a reference array 1401 of first nonvolatile reference memory cells, and a reference array 1402 of second nonvolatile reference memory cells. Reference arrays 1401 and 1402 are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second nonvolatile reference memory cells are connected in diode form via multiplexer 1412 (only partially shown) to the current inputs flowing into them via BLR0, BLR1, BLR2, and BLR3. Multiplexers 1412 each include a respective multiplexer 1405 and a cascaded transistor 1404 to ensure a fixed voltage on the bit line (such as BLR0) of each of the first and second non-volatile reference memory cells during a read operation. The reference cells are adjusted to a target reference level.

[0121] Memory array 1403 serves two purposes. First, it stores weights to be used by VMM array 1400. Second, memory array 1403 effectively multiplies inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3; reference arrays 1401 and 1402 convert these current inputs into input voltages for supply to control gates (CG0, CG1, CG2, and CG3)) by the weights stored in the memory array. All results (cell currents) are then summed to produce an output, which appears on BL0-BLN and will be the input to the next or final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also power-efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the outputs appear on the bit lines (BL0-BLN) during a read operation. The current on each bit line performs a summing function of all the currents from the memory cells connected to that particular bit line.

[0122] VMM array 1400 performs unidirectional programming on the non-volatile memory cells in memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is achieved. This can be performed, for example, using the precision programming technique described below. If too much charge is placed on the floating gate (causing an incorrect value to be stored in the cell), the cell must be erased and the sequence of partial programming operations must be restarted. As shown, two columns sharing the same erase gate (e.g., EG0 or EG1) need to be erased together (called a page erase), after which each cell is partially programmed until the desired charge on the floating gate is achieved.

[0123] Table 7 depicts the operating voltages of the VMM array 1400. The rows in the table represent the voltages on the word line of a selected cell, the word line of an unselected cell, the bit line of a selected cell, the bit line of an unselected cell, the control gate of a selected cell, the control gate of an unselected cell in the same segment as the selected cell, the control gate of an unselected cell in a different segment from the selected cell, the erase gate of a selected cell, the erase gate of an unselected cell, the source line of a selected cell, and the source line of an unselected cell. The columns represent read, erase, and program operations. [ , , ] [] [surface] [7] [:picture]

[14] [of] [VMM] [Array]

[1400] [Operation] [WL] [WL-] [unsel] [BL] [BL-] [unsel] [CG] [In the same district] [Middle of the paragraph] [CG-] [unsel] [CG-] [unsel] [EG] [EG-] [unsel] [SL] [SL-] [unsel] [Read] 0.5-2V -0.5V / 0V 0.1-2V (I neuron) 0V / FLT 0-2.6V 0-2.6V -2.6V 0-2.6V 0-2.6V 0V 0V [ERASE] 0V 0V 0V 0V 0V 0-2.6V 0-2.6V 5-12V 0-2.6V 0V 0V [Stylized] 0.7-1V -0.5V / 0V 0.1-1uA Vinh (1-2V) 4-11V 0-2.6V 0-2.6V 4.5-5V 0-2.6V 4.5-5V 0-1V

[0124] FIG15 depicts a neuron VMM array 1500, which is particularly suitable for use with memory cell 310 shown in FIG3 and serves as a component for synapses between the input layer and the next layer to neurons. VMM array 1500 includes a memory array 1503 of non-volatile memory cells, a reference array 1501 of first non-volatile reference memory cells, and a reference array 1502 of second non-volatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and WL lines WL0, WL1, WL2, and WL3 extend horizontally. VMM array 1500 is similar to VMM array 1400, except that VMM array 1500 implements bidirectional regulation, where each individual cell can be fully erased, partially programmed, and partially erased as needed to achieve the desired charge on the floating gate due to the use of the individual EG lines. As shown, reference arrays 1501 and 1502 convert input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 applied to the memory cells in the row direction (via the action of reference cells connected as diodes via multiplexer 1514). The current outputs (neurons) are located on bit lines BL0-BLN, where each bit line calculates the sum of all currents from the non-volatile memory cells connected to that particular bit line.

[0125] Table 8 depicts the operating voltages of the VMM array 1500. The rows in the table represent the voltages on the word line of a selected cell, the word line of an unselected cell, the bit line of a selected cell, the bit line of an unselected cell, the control gate of a selected cell, the control gate of an unselected cell in the same segment as the selected cell, the control gate of an unselected cell in a different segment from the selected cell, the erase gate of a selected cell, the erase gate of an unselected cell, the source line of a selected cell, and the source line of an unselected cell. The columns represent read, erase, and program operations. [surface] [8] [:picture]

[15] [of] [VMM] [Array]

[1500] [Operation] [WL] [WL-] [unsel] [BL] [BL-] [unsel] [CG] [In the same] [In section] [CG-unsel] [CG-] [unsel] [EG] [EG-] [unsel] [SL] [SL-] [unsel] [Read] 1.0-2V -0.5V / 0V 0.6-2V (I neuron) 0V / FLT 0-2.6V 0-2.6V 0-2.6V 0-2.6V 0-2.6V 0V 0V / FLT [ERASED] 0V 0V 0V 0V 0V 4-9V 0-2.6V 5-12V 0-2.6V 0V 0V [Stylized] 0.7-1V 0.5V / 0V 0.1-1uA Vinh (1-2V) 4-11V 0-2.6V 0-2.6V 4.5-5V 0-2.6V 4.5-5V 0-1V

[0126] FIG16 depicts a neuron VMM array 1600, which is particularly well-suited for memory cell 210 shown in FIG2 and serves as a component for synapsing neurons between an input layer and the next layer. In VMM array 1600, inputs INPUT0, ..., INPUTN are received on bit lines BL0, ..., BLN, respectively, and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0127] FIG17 depicts a neuron VMM array 1700, which is particularly well-suited for memory cell 210 shown in FIG2 and serves as a component for synapsing neurons between an input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ..., OUTPUTN are generated on bit lines BL0, ..., BLN.

[0128] FIG18 depicts a neuron VMM array 1800, which is particularly well-suited for the memory cell 210 shown in FIG2 and is used as a component for synapsing neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUTM are received on word lines WL0, ..., WLM, respectively, and outputs OUTPUT0, ..., OUTPUTN are generated on bit lines BL0, ..., BLN, respectively.

[0129] FIG19 depicts a neuron VMM array 1900, which is particularly well-suited for memory cell 310 shown in FIG3 and is used as a component for synapsing neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUTM are received on word lines WL0, ..., WLM, respectively, and outputs OUTPUT0, ..., OUTPUTN are generated on bit lines BL0, ..., BLN.

[0130] FIG20 depicts a neuron VMM array 2000, which is particularly well-suited for the memory cell 410 shown in FIG4 and is used as a component for synapses between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUTn are received on vertical control gate lines CG0, ..., CGN, respectively, and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0131] FIG21 depicts a neuron VMM array 2100, which is particularly well-suited for memory cell 410 shown in FIG4 and serves as a component for synapsing neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUTN are received at the gates of bitline control gates 2901-1, 2901-2, ..., 2901-(N-1), and 2901-N, which are coupled to bitlines BL0, ..., BLN, respectively. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1, respectively.

[0132] FIG22 depicts a neuron VMM array 2200, which is particularly well-suited for memory cell 310 shown in FIG3 , memory cell 510 shown in FIG5 , and memory cell 710 shown in FIG7 , and is used as a component for synapses between an input layer and the next layer to neurons. In this example, inputs INPUT0, ..., INPUTM are received on word lines WL0, ..., WLM, and outputs OUTPUT0, ..., OUTPUTN are generated on bit lines BL0, ..., BLN, respectively.

[0133] FIG23 depicts a neuron VMM array 2300, which is particularly well-suited for memory cell 310 shown in FIG3 , memory cell 510 shown in FIG5 , and memory cell 710 shown in FIG7 , and is used as a component for synapses between an input layer and the next layer to neurons. In this example, inputs INPUT0, ..., INPUTM are received on control gate lines CG0, ..., CGM, and outputs OUTPUT0, ..., OUTPUTN are generated on vertical source lines SL0, ..., SLN, respectively, where each source line SLi is coupled to the source lines of all memory cells in the i-th row.

[0134] FIG24 depicts a neuron VMM array 2400, which is particularly well-suited for memory cell 310 shown in FIG3 , memory cell 510 shown in FIG5 , and memory cell 710 shown in FIG7 , and is used as a component for synapses between an input layer and the next layer to neurons. In this example, inputs INPUT0, ..., INPUTM are received on control gate lines CG0, ..., CGM, and outputs OUTPUT0, ..., OUTPUTN are generated on vertical bit lines BL0, ..., BLN, respectively, where each bit line BLi is coupled to the bit lines of all memory cells in the i-th row. Test circuit and method

[0135] 25 depicts a VMM system 2500. VMM system 2500 includes a VMM array 2501 (which may be based on any of the previously discussed VMM array designs, such as VMM arrays 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, and 2400, or other VMM array designs), a low-voltage column decoder 2502, a high-voltage column decoder 2503, a row decoder 2504, a row driver 2505, control logic 2506, a bias circuit 2507, an output circuit block 2508, an input VMM circuit block 2509, an algorithm controller 2510, a high-voltage generator block 2511, an analog circuit block 2515, control logic 2516, and test control logic 2517.

[0136] Input circuit block 2509 serves as an interface for external input to the input terminals of memory array 2501. Input circuit block 2509 may include, but is not limited to, a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter), an APC (analog-to-pulse converter), an IVC (current-to-voltage converter), an AAC (analog-to-analog converter, e.g., a voltage-to-voltage converter), or an FAC (frequency-to-analog converter). Output circuit block 2508 serves as an interface for output from the memory array to an external interface (not shown). Output circuit block 2508 may include, but is not limited to, an ADC (analog-to-digital converter), an APC (analog-to-pulse converter), a DPC (digital-to-pulse converter), an IVC (current-to-voltage converter), or an IFC (current-to-frequency converter). Output circuit block 2508 may include, but is not limited to, an excitation function, a normalization circuit, and / or a rescaling circuit.

[0137] The low voltage column decoder 2502 provides bias voltages for read and program operations and provides decoded signals to the high voltage column decoder 2503. The high voltage column decoder 2503 provides high bias signals for program and erase operations.

[0138] Algorithm controller 2510 provides control functions to the bit lines during program, verify, and erase operations.

[0139] The high voltage generator block 2511 includes a charge pump 2512, a charge pump regulator 2513 and a high voltage generating circuit 2514. The high voltage generating circuit 2514 provides multiple voltages required for various programming, erasing, programming verification and reading operations.

[0140] Test control logic 2517 includes various test control circuits for performing the tests described below with respect to Figures 26-31.

[0141] FIG26 depicts a reference current source 2600 that may be used during a verification operation following a programming operation of one or more non-volatile memory cells, or during other types of testing. For example, reference current source 2600 may be used for a verification operation of a single non-volatile memory cell, or for a verification operation of a row of non-volatile memory cells (e.g., all cells connected to a particular bit line), or some other grouping of non-volatile memory cells.

[0142] Reference current source 2600 includes a buffer mirror 2601 (which includes a buffer operational amplifier 2602 with an output I REF 2607 and a PMOS transistor 2603), an adjustable bias current source 2604, and a two-dimensional array 2605 (which includes i columns and j rows of devices 2606), where a particular device 2606 is indicated by the label 2606-(column)(row). Various combinations of devices 2606 can be activated to adjust the amount of reference current I REF 2607 output by buffer mirror 2601. As shown, array 2605 includes 16 devices 2606, each of which can be implemented as a current mirror. Reference current source 2600 essentially converts four digital inputs into a reference bias current whose value is 1 to 16 times I bias unit, where I bias unit is provided by bias current source 2604. The reference current source 2600 is essentially a thermometer-coded digital-to-current converter whose buffered output IREF 2607 corresponds to one of 16 levels. This particular level responds to the four digital inputs and can be stored by any memory cell in the aforementioned VMM array.

[0143] For example, bias current source 2604 can provide a 1 nA current, Ibiasunit, which is mirrored into device 2606. Here, the first row consists of devices 2606-11 through 2606-1j and are enabled sequentially from left to right, one device 2606 at a time. The next row is then enabled sequentially from left to right, adding to the first row. This means enabling five, then six, then seven, and then eight devices 2606. By enabling devices 2606 sequentially, transistor mismatch issues associated with conventional binary decoding are avoided. The sum of the enabled devices 2606 is then mirrored by buffer mirror 2601 and output as current IREF 2607. Bias current source 2604 can provide an adjustable range of current, Ibiasunit, such as 50 pA, 100 pA, 200 pA, ..., and 100 nA. Array 2605 is shown here as a 4×4 array, but it should be understood that array 2605 can have other sizes, such as 32×32 or 8×32.

[0144] FIG27 depicts a reference subcircuit 2700, which can be used with any of the devices 2606 in FIG26. Reference subcircuit 2700 includes NMOS transistors 2701 and 2702, configured as shown. Transistor 2702 is a current mirror bias transistor that receives current Ibiasunit (discussed above with respect to FIG26) at its gate, and transistor 2701 is an enable transistor (to connect current mirror bias transistor 2702 to output node OUTPUT). Current Ibiasunit is provided, for example, by a diode-connected NMOS transistor (similar to transistor 2702) (not shown).

[0145] FIG28 depicts a sense amplifier 2800 used with a reference current source 2600 during a verify operation following a programming operation of a nonvolatile memory cell, a row of nonvolatile memory cells, or some other grouping of nonvolatile memory cells, or during another type of testing. Sense amplifier 2800 receives current IREF 2607, described above with respect to FIG26 . IREF 2607 can be modeled as a PMOS transistor 2813 having a gate controlled by VIREF 2814. Sense amplifier 2800 further includes an inverter 2801, a current source 2802 for limiting the current in inverter 2801, switches 2803 and 2806, a capacitor 2804, and a series-connected NMOS transistor 2805 (to apply a fixed voltage to the memory bit line). Sense amplifier 2800 receives current IREF 2607 from reference current source 2600. This current may be, for example, one of sixteen possible levels to be stored in a nonvolatile memory cell of the VMM array. Sense amplifier 2800 is coupled to cell 2808, the nonvolatile memory cell whose contents are to be verified. When NMOS transistor 2805 is on, cell 2808 draws current ICELL. Alternatively, cell 2808 may be replaced by row 2809 (which, for the sake of illustration, will draw a current still referred to as ICELL, which will be the neuron current drawn by row 2809).

[0146] In one embodiment, IREF2607 starts from the lowest possible value (e.g., the lowest level among 16 possible levels that can be stored in cell 2808 or row 2809), and then sequentially increases to each subsequent level for the verification operation. Switch 2806 can be turned off to generate an initial state for capacitor 2804 (e.g., ground or pre-charge voltage to provide offset cancellation). Switch 2803 can be turned off to make the input and output of inverter 2801 equal, which removes the offset from inverter 2801 for comparison during the verification operation. During the verification operation, switches 2806 and 2803 are turned on. If ICELL >= IREF2607, the voltage on node 2810 will decrease, and then through capacitive coupling via capacitor 2804, causing the voltage on node 2811 to decrease, resulting in the inverter output switching to '1', which means the input of inverter 2801 will be the value '0', and the output of inverter 2801 will be the value '1'. If ICELL < IREF2607, the voltage on node 2810 will increase, and then through capacitive coupling via capacitor 2804, causing the voltage on node 2811 to increase, resulting in the inverter output switching to '0', which means the input of inverter 2801 will switch to the value '1', and the output of inverter 2801 will switch to the value '0'. The value of IREF2607 at which this occurs corresponds to the value stored in cell 2808.

[0147] FIG. 29A depicts a verification operation of non-volatile memory cell 2930 or row 2931 after a programming pulse operation (e.g., verifying whether a memory cell reaches a target current during a weight adjustment process), or during another type of test (e.g., verifying tail memory bits (e.g., abnormal bits) in a memory array that do not meet the cell current requirements), using a verification ramp analog-to-digital converter (ADC) 2900 in conjunction with reference current source 2600. ICELL2906 is the output current from cell 2930 or row 2931. Verification ADC 2900 converts ICELL2906 into a series of digital output bits, and its output is taken as output 2940, where output 2940 represents the value stored in cell 2930 or row 2931.

[0148] Verification ADC 2900 includes an operational amplifier 2901, an adjustable capacitor 2902, an operational amplifier 2904, a counter 2920, and switches 2908, 2909, and 2910. Adjustable capacitor 2902 integrates ICELL 2906 and the current IREF provided by adjustable current source 2807. During the initialization phase, switch 2908 is closed. Vout 2903 of operational amplifier 2901 and the input of its inverting input are equal to the value of reference voltage VREF applied to the non-inverting input of operational amplifier 2901. Switch 2908 is then opened, and during a fixed period tref, switch 2910 is closed, integrating the neuron current ICELL 2906 upward. During the fixed period tref, Vout 2903 rises, with its slope reflecting the value of ICELL 2906. Thereafter, during the period tmeas, the fixed reference current IREF provided by the adjustable current source 2807 is integrated downward by opening the switch 2910 and closing the switch 2909, during which Vout decreases, where tmeas is the time required to integrate Vout downward to VREF.

[0149] When VOUT 2903 > VREF, the output of operational amplifier 2904, EC 2905, is high; otherwise, it is low. Therefore, EC 2905 generates a pulse whose width reflects the time period tmeas and is proportional to the current ICELL 2906.

[0150] Optionally, output EC 2905 is input to counter 2920, which counts the number of clock pulses 2921 received while output EC 2905 is high and generates output 2940, which will be a set of digital bits representing a digital count of the number of clock pulses 2921 that occurred while EC 2905 was high, which number is proportional to ICELL 2906 and corresponds to the value stored in cell 2930 or row 2931.

[0151] Figure 29B illustrates a verification ramp analog-to-digital converter 2950, ​​which includes a current source 2953 (representing the received neuron current Ineu or the current of a single memory cell), a switch 2954, a variable capacitor 2952, and a comparator 2951. Comparator 2951 receives the voltage (Vneu) developed across variable capacitor 2952 at its non-inverting input and a configurable reference voltage Vreframp at its inverting input, and generates an output Cout. The circuitry for clearing the voltage across variable capacitor 2952 is not shown. With each comparison clock cycle, Vreframp is stepped up (increased) by a discrete level. Comparator 2951 compares Vneu with Vreframp. When Vneu > Vreframp, output Cout is "1"; otherwise, it is "0." Therefore, output Cout is a pulse whose width varies in response to the value of Ineu. A larger Ineu causes Cout to be "1" for a longer period of time, resulting in a larger pulse width for output Cout. Digital counter 2960 converts output Cout into digital output bits DO[n:0] 2970, which reflect the number of clock cycles 2961 during which Cout was at the value "1." Alternatively, ramp voltage Vreframp is a continuous ramp voltage. A multi-ramp embodiment can be implemented to reduce conversion time by utilizing a coarse-fine ramp conversion algorithm. First, a coarse reference ramp voltage is rapidly ramped to calculate each subrange of Ineu. Next, a fine reference ramp voltage is used for each subrange to convert the Ineu current within the respective subrange. There may be more than two coarse / fine steps or two subranges.

[0152] Other ADC architectures may be used as the verification ADC, such as, but not limited to, flash ADC, SAR (successive approximation register) ADC, algorithmic ADC, pipeline ADC, Sigma Delta ADC.

[0153] FIG30 depicts an embodiment of the high voltage generation circuit 2511 previously described with respect to FIG25 . High voltage generation circuit 2511 can be used with any of the previously discussed VMM arrays. High voltage generation circuit 2511 includes a charge pump 2512 and a high voltage generation circuit 2514. Charge pump 2512 receives input 3004 and generates a high voltage 3005, which is then provided to high voltage generators 3002 and 3003. High voltage (HV) generator (HVDAC_EG) 3002 is an HV digital-to-analog converter that provides a voltage (e.g., a delta voltage) represented by VEG 3008 suitable for application to the erase gate terminal of a split-gate flash memory cell in response to a digital bit 3006 and the received high voltage 3005. The high voltage generator (HVDAC CGSL) 3003 is a HV digital-to-analog converter that provides voltages (e.g., delta voltages) represented by VCG 3009 and VSL 3010 suitable for application to the control gate terminal and source line terminal of the split-gate flash memory cell, respectively, in response to the digital bit 3007 and the received high voltage 3005.

[0154] FIG31 depicts the VMM system 2500 previously described with respect to FIG25 , but shown here in a test configuration. Test control logic 2517 provides control signals to other components of VMM system 2500 (shown in FIG25 but not shown in FIG31 ), such as VMM array 2501, row decoder 2502, column decoder 2504, input block 2509, high voltage decoder 2503, row driver 2505, high voltage generation block 2511, analog block 2515, algorithm controller 2510, and output circuit block 2508, to implement one or more test algorithms 3100. VMM array 2501 receives control signals from column decoder 2502, thereby establishing one or more columns within VMM array 2501. VMM array 2501 provides signals from one or more bit lines to column decoder 2504, which in turn provides outputs from one or more bit lines to output circuit block 2508. The output circuit block 2508 may include an analog-to-digital converter block (e.g., the verification ADC 2900 previously described with respect to FIG. 29A or the verification ramp ADC 2950 previously described with respect to FIG. 29B ) that provides a digital output representing the analog current received by the output circuit block 2508 from the VMM array 2501.

[0155] Table 9 includes exemplary values ​​to be applied to the word lines, control gate lines, erase gate lines, source gate lines, and bit lines within VMM array 2501 during program, erase, read, and verify operations performed on a single memory cell; during verify neuron and read neuron operations performed on a selected bit line coupled to a row of memory cells; and during a read array operation (whereby every bit line coupled to a row of memory cells is read). [surface] [9] [:used for] [VMM] [Array]

[2501] [Example values ​​of the operations within] [] WL CG EG SL BL sel unsel sel unsel sel unsel sel unsel sel unsel Programming 0.9V 0v Up to 10.5V 0v Up to 4.5V 0v Up to 4.5V ~0.5v Iprog Vinh Erase 0v 0v 0v 0v 6V-11.5V 0v 0v 0v 0v 0v Read 1.1V 0v 2.5V 2.5V 2.5V 2.5V 0v 0v 0.6V 0v Verification Neuron 1.1V 0v 0V-1.5V 0v 0V 0v 0v 0v 0.6V 0v Reading neurons 1.1V 1.1V 0V-1.5V 0V-1.5V 0V 0V 0v 0V 0.6V 0.6V Reading the array 1.1V 1.1V 0V-1.5V 0V-1.5V 0V 0V 0v 0V 0.6V 0v

[0156] More details will now be provided regarding the types of testing that may be performed with reference to test algorithm 3100 described in FIG. 31 and described in more detail in FIGS. 32-44 , which are performed by test control logic 2517 and other components of VMM system 2500 .

[0157] Referring to FIG. 32 , the bitline neural read test 3101 simultaneously measures the values ​​in all memory cells coupled to a bitline. That is, the bitline neural read test 3101 reads neurons in the VMM array. First, the row decoder 2502 asserts all wordlines in the array (step 3201). Second, the row decoder 2504 selects (asserts) a bitline (step 3202). Third, the bitline is read by, for example, sensing the current received from the bitline using the sense amplifier 2800 (step 3203). Fourth, the value of the selected bitline can be determined by comparing it with a reference current generated by the reference current source 2600 to determine whether the non-volatile memory cell (i.e., neuron) coupled to the selected bitline contains the expected value (step 3204).

[0158] Referring to FIG. 33 , the bitline neural measurement test 3102 is similar to the bitline neural read test 3101 . The column decoder 2502 asserts all wordlines (step 3301 ). A bitline is selected by the row decoder 2504 (step 3302 ). The current drawn by the bitline during the read operation is measured (step 3303 ). Unlike the bitline neural read test 3101 , the current from the selected bitline is measured without comparison to a reference current.

[0159] Referring to Figure 34 , during the least significant bit (LSB) screening test 3103, the row decoder 2502 asserts all word lines (step 3401), and the row decoder 2504 asserts all bit lines (step 3402). Deep programming is performed on all memory cells in the VMM array 2501 (step 3403). Deep programming is used to program all memory cells beyond their normal programming state for typical reads. This requires a longer programming timing or a higher programming voltage than normal operation. The total current drawn from all bit lines is then measured (step 3404). The total current of the deeply programmed array is expected to be significantly less than the LSB value. Furthermore, each individual cell is checked to ensure that the current drawn from the individual cell is also below the LSB value, for example, 50-100 pA. This type of testing is suitable for testing during the manufacturing process to quickly identify defective dies.

[0160] Referring to FIG. 35 , during the bit line sampling screening test 3104, a memory cell or a group of memory cells is programmed to a specific level, e.g., Lx, where x ranges from 1 to N, where N is the total number of levels that can be stored in the cell (e.g., N=16) (step 3501). The bit line current (meaning the current drawn by a cell or group of cells in the selected bit line, referred to as IBL) is then measured K times (step 3502). For example, if K=8, the bit line current is measured 8 times. An average value (IAVG) is then calculated based on the K measured values ​​(i.e., IBL1...IBLK) from step 3502 (step 3503).

[0161] Next, each of the K current measurements IBL1...IBLK is checked against IAVG (step 3504). If IBLi (where i is between i and K) > (IAVG + threshold 3506) or IBLi < (IAVG - threshold 3505), the bit line is considered bad. Each cell in the bad bit line is then checked and replaced with a redundant cell (e.g., a cell from a redundant column or redundant row).

[0162] FIG36 depicts another embodiment of a bit line sampling screening test 3104. Voltage VCG is measured by forcing a current Iref into the bit line at K different times (step 3601). For example, voltage VCG can be swept until the bit line current matches a fixed Iref, and the specific VCG can be measured and stored. The fixed Iref can be provided by reference current source 2600, and a verification operation can be performed by sense amplifier 2800 to determine whether the bit line current matches the fixed Iref. An average value VAVG is then calculated based on the K different VCG values. Next, each of the K measured VCG voltages is checked against VAVG (step 3603). If VCGi (where i is between i and K) > (VAVG + threshold 3605) or VCGi < (VAVG - threshold 3604), the bit line is considered defective. Each cell in the defective bit line is then checked and replaced with a redundant cell (redundant column or redundant row).

[0163] During the read tripoint test 3105, coarse and fine read reference current adjustments are performed using different levels of Iref during the read operation. The purpose of the read tripoint test 3105 is to determine whether the selected memory cell can deliver a predetermined current percentage target, for example, ~40% of a fully erased cell for an erased cell or ~5% of a fully programmed cell for a programmed cell. This ensures that the memory cell is within the main distribution and not at the tail end of the distribution (i.e., a statistical outlier), which could cause potential reliability issues over the operating lifetime.

[0164] Referring to FIG. 37 , during a read range check test 3107, a cell is tested to ensure that it can store each of N possible levels. First, the cell is programmed with a target value representing one of the N values ​​(step 3701). Next, a verification operation is performed to determine whether the value stored in the cell is within an acceptable range of values ​​3710 around the target value (step 3702). Steps 3701 and 3702 are repeated for each of the N values ​​(step 3703). The acceptable range of values ​​3710 can be different for each value of N. If any instance of step 3702 being performed indicates that the value stored in the cell is outside the acceptable range of values ​​around the target value, the cell is identified as defective. Read range check test 3107 can be performed by sense amplifier 2800, ADC 2900, ADC 2950, ​​or other components. This is useful for performing weight adjustments on memory cells. While the above description provides an example in which a fixed range is used for each of N values ​​centered around a nominal value, it should be understood that in another example, an upper and lower critical value are used for each of the N values, and these critical values ​​do not have to be the same for all N values ​​without exceeding the range.

[0165] Referring to FIG. 38 , during a read calibration test 3108, leakage current is measured for a cell or group of cells (e.g., cells coupled to a bit line) (step 3801), the measured leakage current (ILEAKAGE) is stored (step 3802), and the measured leakage current value is later used during a read operation to compensate for leakage current under various combinations of process / voltage / temperature (PVT) (step 3803). In one embodiment, a plurality of cells are each programmed with a known value. The word line and control gate line are set to ground, while the bit line is set to a read bias voltage. A sequence of different reference currents is injected into the array, and the resulting data is read by a sense amplifier, such as ADC circuits 2900 or 2950 or sense amplifier 2800. The injected current that produces the best result (compared to the known value programmed into the cell) is stored as ILEAKAGE. ILEAKAGE is then applied during a read operation of the same cell, for example, to compensate for leakage current occurring in the selected cell by subtracting the stored leakage current level from the converted data during the read operation.

[0166] Referring to FIG. 39 , during the read slope test 3109, the IV slope factors of the control gate voltage versus two reference currents (CG1 for current IR1 and CG2 for current IR2) are determined. The first step is determining the logarithmic slope factor of the selected non-volatile memory cell when the selected non-volatile memory cell operates in the subcritical region (step 3901). The second step is storing the logarithmic slope factor (step 3902). The third step is determining the linear slope factor of the selected non-volatile memory cell when the selected non-volatile memory cell operates in the linear region (step 3903). The fourth step is storing the linear slope factor (step 3904). The fifth step is using one or both of the logarithmic and linear slope factors when programming the selected cell to the target current (step 3905).

[0167] Referring to FIG. 40 , during the read neuron qualification test 3110 , neurons (bit lines) are read without checking the values ​​against expected values. The first step is to measure the current in the bit line and store the measured value (step 4001 ). The second step is to perform the read virtual neuron test 4010 (described below) for a predetermined amount of time, such as a burn-in time during the qualification process. The third step is to measure the current from the bit line (step 4003 ). The fourth step is to compare the measured current with the stored measured current from step 4001 (step 4004 ). If the difference is greater than or less than a certain amount, the bit line is considered a bad bit line.

[0168] The read virtual neuron test 4010 includes a series of steps. The first step is to assert all word lines in the array via the row decoder (step 4011). The second step is to assert all bit lines in the array via the row decoder to select all rows of non-volatile memory cells (step 4012). The third step is to perform a read operation (read condition) on the array without checking the read output (step 4013). For burn-in purposes, the read virtual neuron test 4010 serves as a read stress on the array.

[0169] Referring to FIG. 41 , during a soft erase test 3111, the entire array or a sector is tested to check the erase performance of the memory array. The first step is to erase the non-volatile memory cells in the array by applying a voltage sequence to one terminal of each non-volatile memory cell in the array, where the voltage in the voltage sequence increases over time at a fixed step (step 4101). This erases the cells incrementally, for example, by increasing the voltage on the erase gate in steps of 0.5 or 1 volt between 5 and 12.5 volts. Erasing in this manner reduces stress on the memory cells. The second step is to read all non-volatile memory cells to determine the effectiveness of the erase process (step 4102), for example, by determining that the cell current after the erase in step 4101 is within an acceptable range around the nominal value. Optionally, an endurance test can be performed to determine how many program / erase cycles can be sustained, or a background test can be performed to transition the array to an erased state.

[0170] Referring to Figure 42, during soft programming test 3112, the entire array or a row of cells is tested. The first step is to program the non-volatile memory cells in the array by applying a voltage sequence to one terminal of each non-volatile memory cell in the array, where the voltage in the voltage sequence increases over time in fixed steps (step 4201). The cells are programmed in increments, for example, between 3 and 10 volts in steps of 10 mV, 0.3 V, or 1 V, to check the programming performance of the memory array. Programming in this manner reduces stress on the memory cells. The second step is to read all non-volatile memory cells to determine the effectiveness of the programming step (step 4202), for example, by determining that the cell current after programming in step 4201 is within an acceptable range around the nominal value. Optionally, an endurance test or background test can be used.

[0171] Referring to FIG. 43 , a read verification test 3106 may be performed. The first step is to program a plurality of non-volatile memory cells to store one of N different values, where N is the number of different levels that can be stored in any non-volatile memory cell (step 4301). The second step is to measure the current drawn by the plurality of non-volatile memory cells (step 4302). The third step is to compare the measured current to a target value (step 4303). The fourth step is to identify the plurality of non-volatile memory cells as defective if the difference between the measured value and the target value exceeds a threshold factor (step 4304).

[0172] 44 , a checkerboard verification test 3113 can be performed, whereby a test pattern is implemented using a checkerboard or pseudo-checkerboard pattern and sampled levels rather than all possible levels (e.g., 4 levels, L0, Ln, Ln / 4, Ln*3 / 4, rather than all N levels). For example, the pattern can be used to check for worst-case electric field stress within a memory array (meaning one cell is at a high electric field level while an adjacent cell is at a low electric field level).

[0173] In one embodiment, the first step is to program a first group of cells in a plurality of non-volatile memory cells at a level corresponding to a minimum cell current among N levels (step 4401). The second step is to program a second group of cells in a plurality of non-volatile memory cells at a level corresponding to a maximum cell current among N levels (step 4402). Each cell in the second group of cells is adjacent to one or more cells in the first group of cells. The third step is to measure the current drawn by the plurality of non-volatile memory cells (step 4403). The fourth step is to compare the measured current with a target value (step 4404). The fifth step is to identify the plurality of non-volatile memory cells as defective if the difference between the measured value and the target value exceeds a threshold value (step 4405).

[0174] Table 10 contains other exemplary test patterns of physical array diagrams that may be used during checkerboard verification testing 3113: [surface]

[10] [:Example test pattern] [] Figure 1: Ldeep Ln Ldeep Ln Ln Ldeep Ln Ldeep Ldeep Ln Ldeep Ln Ln Ldeep Ln Ldeep Pattern 2: Ldeep Lm Ldeep Lm Lm Ldeep Lm Ldeep Ldeep Lm Ldeep Lm Lm Ldeep Lm Ldeep Pattern 3: L0 [[ID=?7]] Ln L0 Ln Ln L0 Ln L0 L0 Ln L0 Ln Ln L0 Ln L0 Pattern 4: L0 Lq Lm Ln It should be noted that there is an unclear "u" in the original text at line 60 which might be an error. Also, the translation is done as accurately as possible based on the given rules while maintaining the original format and tags. Ln L0 Lq Lm Lm Ln L0 Lq Lq Lm Ln L0

[0175] Classification test 3114, final test 3115, qualification test 3116, and data retention test 3117 are test suites that may be performed during the manufacturing and qualification process of wafers, dies, or packaged devices that include the VMM system disclosed herein.

[0176] Classification testing 3114 can be performed on wafers during the manufacturing process. In one embodiment, classification testing 3114 includes the following test suite: First, relatively fast tests are performed to quickly identify bad wafers or dies, such as soft erase testing 3111, soft programming testing 3112, and various stress mode tests (e.g., erase gate oxide gox, coupled gate oxide cox, source line oxide sol, reverse disturb tunneling rtsts (tunneling from floating gate to word line, disturbing unselected columns), leakage current mpt (disturbance from source to drain of unselected columns), and read disturb rdist (disturbance from read conditions)). Second, neural test patterns are performed, such as LSB screening tests 3103 for upper and lower segments and bit line sampling screening 3104. The neural test patterns are more time-consuming than the tests performed during the first step, but they save time by screening and identifying bad wafers or dies in the first batch of less time-consuming tests.

[0177] Final testing 3115 can be performed on the packaged device. In one embodiment, final testing 3115 includes performing a soft erase test 3111 and a soft program test 3112. Optionally, test patterns for neural applications can be used instead of full testing to reduce test time, for example, testing K of N levels in M ​​segments or testing all N levels in certain segments (e.g., upper and lower segments).

[0178] During qualification testing 3116, a dummy bitline read cycle is performed (this is a read operation performed without actually determining the read data content), and endurance testing is performed by applying soft erase test 3111 and soft program test 3112. Bitline testing is performed instead of individual memory cell testing because bitline reads are used instead of individual memory cell reads during neural memory applications.

[0179] Data retention testing 3117 can include, for example, baking the programmed wafer at an elevated temperature (e.g., 250°C) for 24-72 hours. In one embodiment, a checkerboard or pseudo-checkerboard test pattern is imposed, rather than performing a full test as in digital memory testing. Using the read bitline current mode, data retention checks are performed on the bitline current in a neural mode (rather than checking each memory cell as in digital memory). For example, one query is to check if the delta IBL is < + / - p%, where delta IBL is defined as the difference between the measured bitline current and the expected bitline current. (WholeBLmeas mode, used for target accuracy of the neural network, allows a percentage error p% for software neural network modeling). The delta IBL is tested against the neural mode to identify whether the bitline output current exceeds or falls below the target, defined here as a predetermined percentage "p" of the target. Alternatively, each cell can be checked / tested with a delta of + / - the target.

[0180] Other tests can be performed using the hardware and algorithms described herein.

[0181] It should be noted that as used herein, the terms "over" and "on" include both "directly on" (without intervening materials, elements, or spaces disposed therebetween) and "indirectly on" (with intervening materials, elements, or spaces disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (without intervening materials, elements, or spaces disposed therebetween) and "indirectly adjacent" (with intervening materials, elements, or spaces disposed therebetween), "mounted to" includes "directly mounted to" (without intervening materials, elements, or spaces disposed therebetween) and "indirectly mounted to" (with intervening materials, elements, or spaces disposed therebetween), and "electrically coupled to" includes "directly electrically coupled to" (without intervening materials or elements electrically connecting the elements together) and "indirectly electrically coupled to" (with intervening materials or elements electrically connecting the elements together). For example, forming a component "over a substrate" can include forming the component directly on the substrate without intervening materials / elements therebetween, as well as forming the component indirectly on the substrate with one or more intervening materials / elements therebetween.

[0182] 12:Semiconductor substrate 14: Source region 16: Drain area 18: Channel area 20: Floating Gate 22: Word line terminal (select gate) 24: Bit line terminal 28: Control gate (CG) terminal 30: Erase Gate 31: Digital to Analog Converter 32: VMM system 32a:MM system 32b: VMM system 32c: VMM system 32d: VMM system 32e: VMM system 33: VMM array (non-volatile memory unit array) 34: Erase gate and word line gate decoder 35: Control gate decoder 36: Bit Line Decoder 37: Source Line Decoder 38: Differential adder 39: Excitation function circuit 210:Memory unit 310: memory unit 410:4-gate memory cell 510: memory unit 610:3-gate memory cell 710: Stacked Gate Memory Cell 1100: Neuron VMM Array 1101: Memory array of non-volatile memory cells 1102: Reference array of non-volatile reference memory cells 1103: Control gate line 1104: Erase gate line 1200: Neuron VMM Array 1201: Reference array of first non-volatile reference memory cell 1202: Reference array of second non-volatile reference memory cells 1203: Memory array of non-volatile memory cells 1214: Multiplexer 1300: Neuron VMM Array 1301: Reference array of first non-volatile reference memory cell 1302: Reference array of second non-volatile reference memory cells 1303: Memory array of non-volatile memory cells 1400: Neuron VMM Array 1401: Reference array of first non-volatile reference memory cell 1402: Reference array of second non-volatile reference memory cells 1403: Memory array of non-volatile memory cells 1404: Stacked transistor 1405: Multiplexer 1412: Multiplexer 1500:Neural VMM Array 1501: Reference array of first non-volatile reference memory cell 1502: Reference array of second non-volatile reference memory cells 1503: Memory array of non-volatile memory cells 1514: Multiplexer 1600: Neuron VMM Array 1700:Neural VMM Array 1800:Neural VMM Array 1900: Neuron VMM Array 2000: Neuron VMM Array 2100:Neural VMM Array 2200:Neural VMM Array 2300:Neural VMM Array 2400:Neural VMM Array 2500: VMM system 2501:VMM array 2502: Low Voltage Column Decoder 2503: High Voltage Column Decoder 2504: Row decoder 2505: Row driver 2506: Control Logic 2507: Bias circuit 2508: Output circuit block 2509: Input VMM circuit block 2510: Algorithm Controller 2511: High voltage generator block 2512: Charge Pump 2513: Charge Pump Regulator 2514: High voltage generating circuit 2515:Analog circuit block 2516: Control Logic 2517:Test control logic 2600: Reference current source 2601: Buffer mirror 2602: Buffered Operational Amplifier 2603:PMOS transistor 2604: Adjustable bias current source 2605: Two-dimensional array 2606:Device 2607: Output IREF 2700: Reference subcircuit 2701:NMOS transistor 2702:NMOS transistor 2800: Sense Amplifier 2801:Inverter 2802: Current Source 2803:Switch 2804:Capacitor 2805: Series NMOS transistor 2806:Switch 2807:Adjustable Current Source 2808: Unit 2809: OK 2810: Node 2811: Node 2813:PMOS transistor 2814:VIREF 2900: Verify tilt analog-to-digital converter (ADC) 2901: Operational Amplifier 2901-1-2901-N: Bit Line Control Gate 2902:Adjustable capacitor 2903:Vout 2904: Operational Amplifier 2905: Output EC 2906:ICELL 2908:Switch 2909:Switch 2910: Switch 2920: Counter 2921:Clock pulse 2930: Non-volatile memory unit 2931: OK 2940: Output 2950: Verifying a Ramped Analog-to-Digital Converter 2951: Comparator 2952:Variable capacitor 2953: Current Source 2954:Switch 2960:Digital Counter 2961:Clock cycle 2970: Digital output bit DO [n:0] 3002: High voltage generator 3003: High voltage generator 3004: Input 3005: High Voltage 3006:Digital Bits 3007:Digital Bits 3008: Voltage VEG 3009: Voltage VCG 3010: voltage VSL 3505: critical value 3506: critical value 3604: critical value 3605: critical value 3710: Acceptable value range BL0-BLN: bit lines BLR0: terminal BLR1: terminal BLR2: terminal BLR3: terminal C1: Layer C2: Layer C3: Layer CB1: synapse CB2: Synapses CB3: synapses CB4: synapses CG0: Control gate line (voltage input) CG1: Control gate line (voltage input) CG2: Control gate line (voltage input) CG3: Control gate line (voltage input) CG0-CGM: control gate line CG0-CGN: Control gate line Cout: output EG0:EG line EG1:EG line EGR0:EG line EGR1:EG line ICELL: Current Ineu: neuronal current INPUT0-INPUTM: input INPUT0-INPUTN: input Inputx: Input IREF: Fixed reference current OUTPUT: Output node OUTPUT0-OUTPUTN: output P1: Activation function P2: Activation function S0: Input layer S1: Layer S2: Layer S3: Output layer SL0: Source line SL1: Source line SL2: Source line SL3: Source line SL0-SLN: Source line Vneu: voltage VREF: reference voltage Vreframp: configurable reference voltage WL0: voltage input (word line) WL1: Voltage input (word line) WL2: Voltage input (word line) WL3: Voltage input (word line) WL0-WLM: word line WLA0: word line WLA1: word line WLA2: word line WLA3: word line WLB0: word line WLB1: character line WLB2: character line WLB3: character line

Claims

1. A method for testing a plurality of analog neural nonvolatile memory cells in an array of nonvolatile memory cells, wherein, The memory array is configured in columns and rows, wherein each column is coupled to a word line and each row is coupled to a bit line, and wherein each word line is selectively coupled to a column decoder and each bit line is selectively coupled to a row decoder. The method includes: programming a first group of cells in a plurality of non-volatile memory cells with a level corresponding to the minimum cell current among N levels, wherein N is the number of different levels that can be stored in any of the plurality of non-volatile memory cells and wherein the plurality of non-volatile memory cells is less than all non-volatile memory cells in the array; programming a second group of cells in the plurality of non-volatile memory cells with a level corresponding to the maximum cell current among the N levels, wherein each cell in the second group of cells is adjacent to one or more cells in the first group of cells, thereby generating the highest electric field that can be generated among all combinations of the N levels in adjacent cells; The current drawn by the first group of cells and the second group of cells is measured; the measured current is compared with a target value; and if the difference between the measured value and the target value exceeds a threshold value, the plurality of non-volatile memory cells are identified as defective.

2. As in request item 1, where, Each non-volatile memory cell is a stacked gate flash memory cell.

3. As in request item 1, where, Each non-volatile memory cell is a discrete gate flash memory cell.

4. As in request item 1, where, This array is part of a neural network.

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