Fail bits detection device and method for flash memory

Abstract

This invention provides a failure bit detection device and method for flash memory, applicable to high-capacity and high-performance three-dimensional NAND flash memory. The failure bit detection device includes a capacitive conductor, a pre-charge circuit, a conversion circuit, and a judgment circuit. The pre-charge circuit pre-charges the capacitive conductor. The conversion circuit converts the current logic values ​​of different data buses in the page buffer of the flash memory into discharge current. The conversion circuit draws discharge current from the capacitive conductor. The judgment circuit checks the node voltage of the capacitive conductor. The judgment circuit determines a fall time length based on the fall rate of the node voltage during the judgment period. The judgment circuit determines whether the current logic value of the different data buses is a failure based on the fall time length.

Claims

1. A flash memory failure bit detection device, comprising: A capacitive wire; A pre-charge circuit coupled to the capacitive conductor, wherein the pre-charge circuit pre-charges the capacitive conductor during a pre-charge period; a conversion circuit, wherein a plurality of inputs of the conversion circuit are coupled to different data buses of a page buffer of the flash memory, the conversion circuit converts the current logic value of the different data buses into a discharge current during a decision period after the pre-charge period, a current terminal of the conversion circuit is coupled to the capacitive conductor, and the conversion circuit draws the discharge current from the capacitive conductor during the decision period; and a decision circuit coupled to the capacitive conductor, wherein the decision circuit checks a node voltage of the capacitive conductor during the decision period, the decision circuit determines a fall time length based on a fall rate of the node voltage during the decision period, and the decision circuit determines whether the current logic value of the different data buses is a failure based on the fall time length, wherein the capacitive conductor includes a wire-wound capacitor for storing the pre-charge charge output by the pre-charge circuit during the pre-charge period.

2. The failure bit detection device as described in claim 1, wherein, The current logic value of a target data bus in the different data buses is a first logic value, indicating that the programming result of a corresponding word line in the flash memory has failed; the current logic value of the target data bus is a second logic value, indicating that the programming result of a corresponding word line in the flash memory has passed; in response to the current logic value of the target data bus indicating a programming result failure, the conversion circuit converts the current logic value of the target data bus into a corresponding current component in the discharge current; and in response to the current logic value of the target data bus indicating a programming result pass, the conversion circuit abandons converting the current logic value of the target data bus into the corresponding current component in the discharge current.

3. The failure bit detection device as described in claim 1, wherein, The pre-charging circuit stops pre-charging the capacitive conductor during the judgment period following the pre-charging period; the switching circuit draws the discharge current into the capacitive conductor during the judgment period, causing the node voltage to continuously decrease during the judgment period, wherein the more data buses in the different data buses that indicate a programming failure, the larger the discharge current, and the faster the node voltage decreases; the judgment circuit compares the node voltage to a reference voltage during the judgment period; the judgment circuit determines the fall time length based on the comparison result of the node voltage and the reference voltage; the judgment circuit compares the fall time length to a reference time length; and the judgment circuit determines whether the current logic value of the different data buses is a failure based on the comparison result of the fall time length and the reference time length.

4. The failure bit detection device as claimed in claim 1, wherein the pre-charge circuit includes: A precharged crystal, wherein a first terminal of the precharged crystal is coupled to a power supply voltage source, a second terminal of the precharged crystal is coupled to a capacitive wire, and a control terminal of the precharged crystal is controlled by a precharge control signal.

5. The failure bit detection device as claimed in claim 1, wherein the conversion circuit comprises: A plurality of switches, wherein a first terminal of each of the switches is coupled to the capacitive wire, and a control terminal of each of the switches is coupled to a corresponding one of the different data buses of the page buffer; and a plurality of first transistors, wherein a first terminal of each of the first transistors is coupled to a second terminal of a corresponding one of the switches, a second terminal of each of the first transistors is coupled to a first reference voltage source, and a control terminal of each of the first transistors is controlled by a bias voltage.

6. The failure bit detection device as described in claim 5, further comprising: A bias voltage generating circuit is coupled to the conversion circuit to provide the bias voltage.

7. The failure bit detection device as claimed in claim 6, wherein the bias voltage generating circuit includes: A current source; And a second transistor, wherein a first terminal of the second transistor is coupled to the current source, a second terminal of the second transistor is coupled to a second reference voltage source, and a control terminal of the second transistor is coupled to the first terminal of the second transistor and the control terminal of each of the first transistors to provide the bias voltage.

8. The failure bit detection device as claimed in claim 1, wherein the determination circuit includes: A first comparator, coupled to the capacitive wire to receive the node voltage, wherein the first comparator compares the node voltage to a reference voltage during the determination period; a counter having a coherent power input coupled to an output of the first comparator, wherein the first comparator controls a counting time length of the counter as the fall time length based on the comparison result of the node voltage and the reference voltage, and the counter counts a clock signal during the counting time length to generate a count value; And a second comparator, coupled to an output of the counter to receive the count value, wherein the second comparator compares the count value to a reference value during the determination period, and the second comparator determines whether the current logic value of the different data bus is a failure based on the comparison result of the count value and the reference value.

9. The failure bit detection device as described in claim 8, wherein the determination circuit further comprises: A reference voltage generation circuit generates an original reference voltage; And a temperature compensation circuit having an input terminal coupled to an output terminal of the reference voltage generation circuit to receive the original reference voltage, wherein the temperature compensation circuit compensates the original reference voltage based on a current temperature to generate a compensated reference voltage as the reference voltage for the first comparator.

10. The failure bit detection device as claimed in claim 8, wherein the determination circuit further comprises: A clock generation circuit generates a primary clock signal; And a temperature compensation circuit having an input terminal coupled to an output terminal of the clock generation circuit to receive the original clock signal, wherein the temperature compensation circuit compensates the original clock signal based on a current temperature to generate a compensated clock signal as the clock signal to the counter.

11. The failure bit detection device as claimed in claim 1, wherein the determination circuit includes: A first comparator, coupled to the capacitive wire to receive the node voltage, wherein the first comparator compares the node voltage to a reference voltage during the determination period; a counter having a control terminal coupled to an output terminal of the first comparator, wherein the first comparator controls a counting time length of the counter as the fall time length based on the comparison result of the node voltage and the reference voltage, and the counter counts a clock signal during the counting time length to generate a count value; a temperature compensation circuit having an input terminal coupled to an output terminal of the counter to receive the count value, wherein the temperature compensation circuit compensates the count value based on a current temperature to generate a compensated count value; And a second comparator, coupled to an output of the temperature compensation circuit to receive the compensated count value, wherein the second comparator compares the compensated count value to a reference value during the determination period, and the second comparator determines whether the current logic value of the different data buses is a failure based on the comparison result of the compensated count value and the reference value.

12. A method for detecting failure bits in flash memory, comprising: A pre-charge circuit of the flash memory pre-charges a capacitive wire of the flash memory during a pre-charge period, wherein the pre-charge circuit is coupled to the capacitive wire; a conversion circuit of the flash memory converts the current logic value of different data buses of a page buffer of the flash memory into a discharge current during a decision period after the pre-charge period, wherein multiple inputs of the conversion circuit are coupled to the different data buses; the conversion circuit draws the discharge current from the capacitive wire during the decision period, wherein a current terminal of the conversion circuit is coupled to the capacitive wire; a decision circuit of the flash memory checks a node voltage of the capacitive wire during the decision period, wherein the decision circuit is coupled to the capacitive wire; the decision circuit determines a fall time length based on a fall rate of the node voltage during the decision period; and the decision circuit determines whether the current logic value of the different data buses is a failure based on the fall time length, wherein the capacitive wire includes a wire-wound capacitor for storing the pre-charge charge output by the pre-charge circuit during the pre-charge period.

13. The failure bit detection method as described in claim 12, wherein the current logic value of a target data bus in different data buses is a first logic value indicating that the programming result of a corresponding word line in the flash memory is a failure, and the current logic value of the target data bus is a second logic value indicating that the programming result of a corresponding word line in the flash memory is a success, and the failure bit detection method further includes: In response to a failure in the programming result of the current logic value of the target data bus, the conversion circuit converts the current logic value of the target data bus into a corresponding current component in the discharge current; and in response to a success in the programming result of the current logic value of the target data bus, the conversion circuit abandons the conversion of the current logic value of the target data bus into the corresponding current component in the discharge current.

14. The failure bit detection method as described in claim 12 further includes: The pre-charging circuit stops pre-charging the capacitive wire during the determination period following the pre-charging period. The conversion circuit draws discharge current from the capacitive conductor during the judgment period, causing the node voltage to continuously decrease during the judgment period. The more data buses in the different data buses that indicate a programming failure, the larger the discharge current, resulting in a faster decrease in the node voltage. The judgment circuit compares the node voltage to a reference voltage during the judgment period. The judgment circuit determines the fall time length based on the comparison result of the node voltage and the reference voltage. The judgment circuit compares the fall time length to a reference time length. The judgment circuit determines whether the current logic value of the different data buses is a failure based on the comparison result of the fall time length and the reference time length.

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