LED current overshoot reduction apparatus and method

Abstract

The present invention discloses an apparatus comprising: a reference current generation circuit coupled between a first voltage bus and a second voltage bus, wherein the reference current generation circuit is configured to generate a predetermined reference current; a first reference current path including a first switch, wherein the predetermined reference current is configured to be mirrored to generate a first reference current in the first reference current path; a load current path including a power switch; and a pulse width modulation (PWM) anti-spiking circuit configured to control the first switch to reduce an overshoot occurring at a leading edge of a load current flowing through the power switch.

Description

[Technical Field]

[0001] This disclosure generally relates to the field of integrated circuits, and in a particular embodiment, to a technique and mechanism for an LED current overshoot reduction device. [Previous Technology]

[0002] A light-emitting diode (LED) is a semiconductor light source. When a voltage is applied to an LED, a current flows through the LED. In response to the current flowing through the LED, electrons and holes recombine in the PN junction of the diode. During the recombination process, energy is released in the form of photons.

[0003] In a typical LED system, a power switch and an LED are connected in series between a power source and ground. A pulse width modulation (PWM) controller is used to control the power switch. During operation, the PWM controller is configured to generate a gate drive signal applied to one of the gates of the power switch. The gate drive signal is controlled so that an average current flowing through the LED can be adjusted according to different operating requirements. This PWM technology, used to control the average current of the LED, is widely used to control LED brightness.

[0004] Power PWM dimming is a technique used to control the brightness of an LED by varying the amount of time an LED is energized and de-energized. PWM dimming rapidly turns the LED on and off at a high frequency, rather than adjusting the voltage or current supplied to the LED. The brightness is determined by the ratio of the on-time to the off-time in each cycle (called the duty cycle).

[0005] In operation, when power PWM dimming is applied to an LED, the average power delivered to the LED over time controls the brightness. A higher duty cycle means the LED is on for a longer portion of each cycle, resulting in higher brightness. Conversely, a lower duty cycle means the LED is on for a shorter portion, resulting in dimmer light. Power PWM dimming is widely used in applications requiring precise and efficient control of LED brightness, such as automotive lighting.

[0006] Accuracy and linearity are critical design specifications in power PWM dimming. Achieving desired dimming accuracy and linearity requires considering or minimizing the delay time between the PWM signal and the LED current response, especially in high-frequency PWM control. During PWM transitions, high-frequency operation can cause LED current overshoot (inrush current), resulting in inaccurate dimming, nonlinearity, and undesirable LED flicker. While LED flicker is generally harmless to most people's eyes, it can cause discomfort, eye strain, headaches, and visual impairment in some individuals. There is a desire for a simple device that can reduce LED current overshoot. This disclosure describes a simple and cost-effective device for reducing LED current overshoot, thereby enabling the development of high-quality LED lighting products without LED flicker. [Summary of the Invention]

[0007] Technical advantages are generally achieved through the embodiments disclosed herein, which illustrate an LED current overshoot reduction device.

[0008] According to one embodiment, an apparatus includes: a reference current generation circuit coupled between a first voltage bus and a second voltage bus, wherein the reference current generation circuit is configured to generate a predetermined reference current; a first reference current path including a first switch, wherein the predetermined reference current is configured to be mirrored to generate a first reference current in the first reference current path; a load current path including a power switch; and a pulse width modulation (PWM) deglitch circuit configured to control the first switch to reduce an overshoot occurring at a leading edge of a load current flowing through the power switch.

[0009] According to another embodiment, a method includes: using a reference current generating circuit coupled between a first voltage bus and a second voltage bus to generate a predetermined reference current; mirroring the predetermined reference current to generate a first reference current in a first reference current path including a first switch; and controlling the first switch by a PWM anti-spiking circuit to reduce an overshoot occurring at a leading edge of a load current flowing through a power switch.

[0010] According to another embodiment, a system includes: a PWM switch, an integrated circuit, and a light-emitting diode connected in series between a power supply and ground; and a system controller configured to control the PWM switch, wherein the integrated circuit includes: a low-dropout regulator having an input configured to receive an input voltage and an output configured to generate a bias voltage on a first voltage bus; and an undervoltage lockout circuit configured to receive the bias voltage and generate a control signal applied to a gate of a power switch, wherein a current flowing through the power switch is approximately equal to the current flowing through the light-emitting diode. The power supply includes: a current; a bandgap reference circuit configured to receive the bias voltage and generate a bandgap reference; a reference current generation circuit coupled between the first voltage bus and a second voltage bus, wherein the reference current generation circuit is configured to generate a predetermined reference current; a first reference current path including a first switch, wherein the predetermined reference current is configured to be mirrored to generate a first reference current in the first reference current path; and a PWM anti-spiking circuit configured to control the first switch to reduce an overshoot occurring at a leading edge of a load current flowing through the power switch.

[0011] The foregoing has provided a fairly broad overview of the features and technical advantages of this disclosure in order to better understand the detailed description of this disclosure below. Additional features and advantages of this disclosure, which form the subject matter of the claims of this disclosure, will be set forth below. Those skilled in the art will understand that the disclosed concepts and specific embodiments can be readily used as a basis for modifying or designing other structures or procedures for performing the same purpose as this disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure as set forth in the appended claims.

Implementation Method

[0023] Cross-reference to related applications This patent application claims priority to U.S. Application No. 18 / 789,342, filed on July 30, 2024, entitled “LED Current Overshoot Reduction Apparatus and Method”, and is specifically a successor application to that U.S. application, which is incorporated herein by reference in its entirety.

[0024] The following describes in detail the making and use of the embodiments disclosed herein. However, it should be understood that the concepts disclosed herein may be embodied in a variety of specific contexts, and the specific embodiments discussed herein are merely illustrative and not intended to limit the scope of the claims. Furthermore, it should be understood that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0025] Furthermore, features from one or more of the embodiments described below may be combined to create alternative embodiments not explicitly described, and features suitable for such combinations should be understood to be within the scope of this disclosure. Therefore, it is intended that any such modifications or embodiments be covered by the appended claims.

[0026] This disclosure will be described with reference to an embodiment in a specific context, namely an LED current overshoot reduction device. However, this disclosure can also be applied to various LED systems. Various embodiments will be explained in detail below with reference to the accompanying drawings.

[0027] Figure 1 is a block diagram illustrating one of the various embodiments of a light-emitting diode system according to the present disclosure. As shown in Figure 1, a PWM switch SPWM, an integrated circuit 100, and a light-emitting diode D1 are connected in series between a power supply VB and ground. A system controller 150 is configured to generate a PWM signal (PWM) for controlling the PWM switch SPWM.

[0028] It should be noted that the block diagram shown in Figure 1 is only one example. The system configuration can vary depending on different applications and design requirements. For example, the light-emitting diode D1 can be placed between the PWM switch SPWM and the integrated circuit 100. Furthermore, the PWM switch SPWM can be directly connected to ground. In this system configuration, the PWM switch SPWM can be implemented as an n-type switch. Compared to a p-type switch of the same size, the n-type switch typically has a lower on-resistance, resulting in a lower voltage drop and higher efficiency in the light-emitting diode system.

[0029] As shown in Figure 1, the common node of the PWM switch SPWM and one of the integrated circuits 100 is labeled VIN. The common node of the integrated circuit 100 and the light-emitting diode D1 is labeled VSS. The current flowing through the light-emitting diode D1 is labeled ILED. Throughout the description, ILED can be alternatively referred to as LED current.

[0030] In some embodiments, the system controller 150 controls the PWM switch SPWM according to power PWM dimming technology. In operation, the brightness of the light-emitting diode D1 can be controlled by varying the amount of time the diode is energized and de-energized. The brightness of the light-emitting diode D1 is determined by the ratio of the on-time to the off-time in each cycle. When the light-emitting diode D1 is energized, the power supply VB supplies power to the integrated circuit 100 through the energized PWM switch SPWM. When the light-emitting diode D1 is de-energized, no power is supplied to the integrated circuit 100. Under power PWM dimming, the light-emitting diode D1, along with the integrated circuit 100, is rapidly energized and de-energized at a high frequency. To ensure accurate and linear dimming, the delay time from the PWM signal to the LED current response (e.g., soft-start) must be minimized. In a high-frequency power PWM dimming procedure, soft-start cannot be used to reduce rapid PWM transitions. High-frequency power PWM dimming procedures typically result in LED current overshoot. This disclosure describes four different implementation schemes for reducing LED current overshoot. These four different implementation schemes mitigate LED current overshoot, which will be explained in detail with reference to Figures 2, 5, 6 and 8.

[0031] In some embodiments, the system controller 150 is implemented as a microcontroller. In alternative embodiments, the system controller 150 may be implemented as any suitable processor, such as a digital signal processing (DSP) controller, a field programmable gate array (FPGA) processor, and the like.

[0032] The PWM switch SPWM shown in Figure 1 can be implemented as an n-type metal-oxide-semiconductor (NMOS) transistor. Alternatively, such switches can be implemented as other suitable controllable devices, such as metal-oxide-semiconductor field-effect transistor (MOSFET) devices, bipolar junction transistor (BJT) devices, super junction transistor (SJT) devices, insulated-gate bipolar transistor (IGBT) devices, gallium nitride (GaN) based power devices, any combination thereof, and the like.

[0033] The integrated circuit 100 serves as an LED driver. Throughout the description, the integrated circuit 100 may alternatively be referred to as an LED driver 100. In some embodiments, the LED driver 100 includes a bias power supply, an undervoltage protection circuit, a reference circuit, a reference current generation circuit, a PWM anti-spiking circuit, a plurality of reference current paths, a precisely controlled current mirror, a power switch, a gate protection circuit, and a start-up circuit.

[0034] In some embodiments, the bias power supply is implemented as a low-dropout regulator. One input of the low-dropout regulator is configured to receive the voltage across VIN and generate a bias voltage. The undervoltage protection circuit is implemented as an undervoltage lockout circuit. The undervoltage lockout circuit is configured to receive the bias voltage. Once the bias voltage exceeds a predetermined threshold, the undervoltage lockout circuit is configured to generate a control signal applied to the gate of the power switch in the LED driver 100. The current flowing through the power switch is approximately equal to the current flowing through the light-emitting diode D1. The reference circuit is implemented as a bandgap reference circuit. The bandgap reference circuit is configured to receive the bias voltage and generate a bandgap reference.

[0035] The reference current generation circuit is coupled between the bias voltage and VSS. The reference current generation circuit is configured to generate a predetermined reference current.

[0036] In a first embodiment of the LED driver 100, the LED driver 100 includes a first reference current path. The first reference current path includes a first switch. A predetermined reference current is mirrored to generate a first reference current in the first reference current path. Furthermore, the first reference current is mirrored to generate a load current flowing through a power switch in the LED driver 100. A PWM anti-spiking circuit is configured to control the first switch to reduce overshoot occurring at a leading edge of the load current flowing through the power switch. The detailed structure and operating principle of the first embodiment of the LED driver 100 will be described below with reference to FIG2.

[0037] In a second embodiment of the LED driver 100, the LED driver 100 includes a first reference current path and a second reference current path. The second reference current path is connected in parallel with the first reference current path. The first reference current path includes a first switch. A predetermined reference current is mirrored to generate a first reference current in the first reference current path and a second reference current in the second reference current path. Furthermore, the sum of the first and second reference currents is mirrored to generate a load current flowing through a power switch in the LED driver 100. A PWM anti-spiking circuit is configured to control the first switch to reduce overshoot occurring at the leading edge of the load current flowing through the power switch. The detailed structure and operating principle of the second embodiment of the LED driver 100 will be described below with reference to FIG. 5.

[0038] In a third embodiment of the LED driver 100, the LED driver 100 includes a first reference current path, a second reference current path, a third reference current path, and a fourth reference current path. The second reference current path is connected in parallel with the first reference current path. The first reference current path includes a first switch. The third reference current path includes a second switch. The third reference current path is connected in parallel with the first reference current path. The fourth reference current path includes a third switch. The fourth reference current path is connected in parallel with the first reference current path. A predetermined reference current is mirrored to generate a first reference current in the first reference current path, a second reference current in the second reference current path, a third reference current in the third reference current path, and a fourth reference current in the fourth reference current path. Furthermore, the sum of the first, second, third, and fourth reference currents is mirrored to generate a load current flowing through the power switch. A PWM anti-spiking circuit is configured to control the first, second, and third switches to reduce an overshoot occurring at the leading edge of the load current flowing through the power switch. The following section will describe the detailed structure and operating principle of the third embodiment of the LED driver 100 with reference to Figures 6 and 7.

[0039] In a fourth embodiment of the LED driver 100, the LED driver 100 includes a first reference current path, a second reference current path, a third reference current path, a fourth reference current path, and a reference current subtraction circuit. The second reference current path is connected in parallel with the first reference current path. The first reference current path includes a first switch. The third reference current path includes a second switch. The third reference current path is connected in parallel with the first reference current path. The fourth reference current path includes a third switch. The fourth reference current path is connected in parallel with the first reference current path. A predetermined reference current is mirrored to generate a first reference current in the first reference current path, a second reference current in the second reference current path, a third reference current in the third reference current path, and a fourth reference current in the fourth reference current path. Furthermore, the sum of one of the first, second, third, and fourth reference currents is mirrored to generate a load current flowing through one of the power switches. A PWM anti-spiking circuit is configured to control the first, second, and third switches to reduce overshoot at the leading edge of the load current flowing through the power switches. Furthermore, a reference current subtraction circuit is configured to subtract a current component from the sum of reference currents. Reducing the sum of reference currents further reduces overshoot. The detailed structure and operating principle of the fourth embodiment of the LED driver 100 will be described below with reference to Figure 8.

[0040] It should be noted that the LED system shown in Figure 1 is only one example. The system configuration may vary depending on the application and design requirements. For example, a current sensing resistor may be placed between the LED and ground. Furthermore, although Figure 1 illustrates one LED, the LED system can accommodate any number of LEDs connected in series and / or parallel.

[0041] Figure 2 illustrates a schematic diagram of a first embodiment of an LED driver shown in Figure 1 according to various embodiments of the present disclosure. The LED driver includes a low-dropout regulator 202, an undervoltage lockout circuit 204, a bandgap reference circuit 206, a PWM anti-spiking pulse circuit 208, a reference current generation circuit 222, a first reference current path 231, a power switch Q1, a precision-controlled current mirror 228, a gate protection circuit 224, and a start-up circuit 226.

[0042] As shown in Figure 2, one input of the low-dropout regulator 202 is configured to receive an input voltage VIN. The low-dropout regulator 202 is configured to generate a bias voltage VDD. Throughout this description, the voltage bus on which the bias voltage VDD is generated may be referred to as a first voltage bus. The voltage bus labeled VSS may be referred to as a second voltage bus.

[0043] The undervoltage lockout circuit 204 is configured to receive the bias voltage VDD. Once the bias voltage VDD exceeds a predetermined threshold, the undervoltage lockout circuit 204 is configured to generate a control signal applied to one of the gates of the power switch Q1. This control signal keeps the power switch Q1 on. In other words, the control signal serves as a power good (PG) signal.

[0044] The bandgap reference circuit 206 is configured to receive the bias voltage VDD and generate a bandgap reference VBG. As shown in Figure 2, the bandgap reference VBG is used to set a reference current IREF.

[0045] The reference current generation circuit 222 includes a first p-type transistor MP1, a resistor RSET, and a first amplifier 212. The first p-type transistor MP1 and the resistor RSET are connected in series between a first voltage bus VDD and a second voltage bus VSS. One inverting input of the first amplifier 212 is configured to receive a bandgap reference VBG. One non-inverting input of the first amplifier 212 is connected to a common node of the first p-type transistor MP1 and the resistor RSET. As shown in Figure 2, the voltage at the common node of the first p-type transistor MP1 and the resistor RSET is labeled VREF. One output of the first amplifier 212 is connected to a gate of the first p-type transistor MP1.

[0046] In operation, the first amplifier 212 forces the voltage across node VREF to be equal to the bandgap reference VBG. The current flowing through resistor RSET is equal to the bandgap reference VBG divided by the resistance value of RSET. This current is the reference current IREF of the LED driver. Throughout this description, the voltage across node VREF may be referred to as a reference voltage signal.

[0047] The first reference current path 231 includes a second p-type transistor MP2 and a first switch S1 connected in series between the first voltage bus VDD and a voltage node VDA. The gate of the first switch S1 is controlled by a PWM anti-spiking circuit 208.

[0048] In operation, the first p-type transistor MP1 and the second p-type transistor MP2 form a first current mirror. Through the first current mirror, the reference current IREF generated by the reference current generation circuit 222 is mirrored to generate a first reference current IREF1 in the first reference current path 231.

[0049] The precisely controlled current mirror 228 includes a first n-type transistor MN1, a second n-type transistor MN2, and a second amplifier 214. As shown in FIG2, the first n-type transistor MN1 and the first reference current path 231 are connected in series between the second voltage bus VSS and the first voltage bus VIN. The second n-type transistor MN2 is connected in series with the power switch Q1. One inverting input of the second amplifier 214 is connected to one drain of the first n-type transistor MN1. As shown in FIG2, the drain of the first n-type transistor MN1 is labeled VDA. One non-inverting input of the second amplifier 214 is connected to one drain of the second n-type transistor MN2. As shown in FIG2, the drain of the second n-type transistor MN2 is labeled VDB. One output of the second amplifier 214 is connected to the gate of the first n-type transistor MN1 and the gate of the second n-type transistor MN2.

[0050] In operation, the second amplifier 214 forces the voltage across the drain of the first n-type transistor MN1 to be equal to the voltage across the drain of the second n-type transistor MN2. This voltage relationship helps to achieve a precisely controlled current mirror. The first reference current IREF1 in the first reference current path 231 is mirrored through the precisely controlled current mirror 228 to generate the load current IL flowing through the power switch Q1. In some embodiments, the ratio of the current flowing through the second n-type transistor MN2 to the current flowing through the first n-type transistor MN1 is in the range of about 1000 to about 10,000. Throughout the description, the precisely controlled current mirror 228 may alternatively be referred to as a second current mirror.

[0051] The PWM anti-spiking circuit 208 is configured to receive the voltage at voltage node VREF. This voltage is proportional to the reference current IREF. Based on the received voltage at VREF, the PWM anti-spiking circuit 208 is configured to generate a plurality of control signals to control the switches in different reference current paths in order to reduce an overshoot occurring at the leading edge of a load current flowing through power switch Q1. In the first embodiment of the LED driver shown in Figure 2, the PWM anti-spiking circuit 208 generates a control signal at a first terminal T1. This control signal is applied to the gate of the first switch S1 to reduce the overshoot of the load current IL.

[0052] In operation, PWM switching typically introduces transient noise into functional blocks of the LED driver (e.g., the low-dropout regulator 202 and / or the bandgap reference circuit 206). During power switching or power-on, transient noise can cause overshoot of the load current flowing through the power switch Q1. The PWM anti-spiking circuit 208 can detect transient noise at node VREF and convert it into a digital signal to control the on and off of the first switch S1. More specifically, when transient noise occurs at node VREF, the PWM anti-spiking circuit 208 converts the transient noise into a logic high signal to turn off the first switch S1. Once the first switch S1 is temporarily turned off, the first reference current IREF1 decreases, thereby reducing the overshoot of the load current IL flowing through the power switch Q1.

[0053] The load current path of the LED driver includes the power switch Q1. The load current IL flows through the power switch Q1. The LED current ILED includes some bias current (e.g., IREF). Since the bias current of the LED driver is quite small, the load current IL is approximately equal to the LED current ILED.

[0054] Gate protection circuit 224 is connected between the gate of power switch Q1 and the second voltage bus VSS. Gate protection circuit 224 includes a first resistor R1, a second resistor R2, a capacitor C1, and a third n-type transistor MN3. The third n-type transistor MN3 is connected between the gate of power switch Q1 and the second voltage bus VSS. The first resistor R1 and the capacitor C1 are connected in series between the gate of power switch Q1 and the second voltage bus VSS. The second resistor R2 is connected between the gate of power switch Q1 and the second voltage bus VSS.

[0055] In operation, the gate protection circuit 224 provides two functions. First, capacitor C1, first resistor R1, and third n-type transistor MN3 form a voltage clamping circuit configured to provide various protections, such as electrostatic discharge (ESD) and electrical overload (EOS) protection. When a fast voltage event (such as ESD or power switching) occurs from the input voltage bus VIN, a high-voltage transient can travel from the drain terminal of power switch Q1 to its gate through the parasitic Miller capacitance of power switch Q1. This fast transient can turn on the third n-type transistor MN3, thereby keeping the gate voltage of Q1 at a safe level. Second, the second resistor R2 provides a passive pull-down to power switch Q1, thereby helping the undervoltage lockout circuit 204 keep power switch Q1 off when the LED driver operates in an undervoltage condition.

[0056] The starting circuit 226 includes a third current mirror, which includes a fourth n-type transistor MN4 and a fifth n-type transistor MN5. The starting circuit 226 further includes a sixth p-type transistor MP6. As shown in Figure 2, the sixth p-type transistor MP6 and the fifth n-type transistor MN5 are connected in series between the first voltage bus VDD and the second voltage bus VSS. The power switch Q1 and the fourth n-type transistor MN4 are connected in series between the input voltage bus VIN and the second voltage bus VSS. The gate of the sixth p-type transistor MP6 is connected to the gate of the first p-type transistor MP1. The reference current IEF is mirrored to generate a current flowing through the sixth p-type transistor MP6.

[0057] During operation, the precisely controlled current mirror 228 has multiple stable states. The starting circuit 226 ensures an initial current flow, thereby causing the precisely controlled current mirror 228 to enter its correct operating state.

[0058] Figure 3 illustrates a schematic diagram of a PWM anti-spiking circuit shown in Figure 2 according to various embodiments of the present disclosure. The PWM anti-spiking circuit 208 includes a first inverter 311, a second inverter 312, a current source IB, a leading edge blocking circuit 302, a mutual exclusion OR gate 304, an inverter 306, and an inverse OR gate 308. The first inverter 311 is formed by a p-type transistor M1 and an n-type transistor M2 connected in series between VDD and VSS. The second inverter 312 is formed by a p-type transistor M3 and an n-type transistor M4 connected in series between VDD and VSS.

[0059] As shown in Figure 3, the first inverter 311 is configured to receive a reference voltage signal VREF. The reference voltage signal VREF is proportional to the reference current IREF. In some embodiments, the threshold voltage of the first inverter 311 is selected such that when VREF exceeds its target or steady-state value, the first inverter 311 switches its output from a logic high state to a logic low state. In other words, the steady-state value of VREF can be selected as the threshold voltage of the first inverter 311. Once VREF is greater than this threshold voltage, the first inverter generates a logic low signal that is fed into the second inverter 312.

[0060] As shown in Figure 3, the second inverter 312 has an input connected to the output of the first inverter 311. The output of the second inverter 312 is configured to generate a first control signal applied to a first terminal T1. Referring back to Figure 2, T1 is connected to the gate of the first switch S1. When an overshoot occurs, the leading edge of VREF exceeds the steady-state value of VREF. In response, the first inverter 311 generates a logic low signal. The second inverter 312 converts this logic low signal into a logic high signal applied to the gate of the first switch S1. Since the first switch S1 is a p-type transistor, the logic high signal turns off the first switch S1. Referring back to Figure 2, once the first switch S1 is turned off, the current flowing through the power switch Q1 decreases. The reduced load current helps reduce the overshoot of the LED current ILED.

[0061] The leading edge blocking circuit 302 may include a timer, an inverter, and an AND gate. A current source IB provides a bias current to the timer. The timer is configured to generate a blocking pulse in response to the leading edge of VREF. The blocking pulse is fed into the inverter. A first input of the AND gate is configured to receive a first control signal (T1). A second input of the AND gate is configured to receive the output signal of the inverter. In this way, the AND gate only allows the first control signal to pass through and reach the third terminal T3 after the end of the blocking cycle. The signal generated at the third terminal T3 is a third control signal. The third control signal will be described in detail below with reference to FIG6.

[0062] As shown in Figure 3, the OR gate 304, inverter 306, and inverse OR gate 308 are cascaded. A first input of the OR gate 304 is configured to receive a first control signal (T1). A second input of the OR gate 304 is configured to receive a third control signal (T3). An input of the inverter 306 is connected to an output of the OR gate 304. A first input of the inverse OR gate 308 is configured to receive the third control signal (T3). A second input of the inverse OR gate 308 is connected to an output of the inverter 306. An output of the inverse OR gate 308 is configured to generate a control signal at a second terminal T2. The signal generated at the second terminal T2 is a second control signal. The second control signal will be described in detail below with reference to Figure 6.

[0063] In response to an overshoot of VREF, the PWM anti-spiking circuit 208 generates three control signals. The duration of the logic high state of the first control signal (T1) is approximately equal to the duration of the VREF overshoot. The first control signal is simultaneously divided into two parts. The leading part is the second control signal (T2). The trailing part is the third control signal (T3). These three control signals are used as three control variables to shut off the corresponding reference current path, thereby reducing the overshoot of the load current IL flowing through the power switch Q1.

[0064] Figure 4 illustrates the various signals associated with the PWM anti-spiking circuit shown in Figure 3 according to various embodiments of this disclosure. The horizontal axis represents the time interval. There are five columns. The first column represents the PWM signal shown in Figure 1. The second column represents the reference voltage signal VREF. The third column represents the first control signal T1. The fourth column represents the second control signal T2. The fifth column represents the third control signal T3.

[0065] At time t1, the PWM signal changes from a logic low state to a logic high state. In response to this change, the PWM switch is turned on and power is supplied to the LED driver. After an appropriate circuit delay, the reference voltage signal VREF begins to build from time t2. As shown in Figure 4, an overshoot occurs in VREF. At time t3, this overshoot exceeds the threshold voltage VTH of the first inverter 311. The first inverter 311 and the second inverter 312 together act as a buffer. From time t3 to time t5, the overshoot is greater than the threshold voltage VTH. Therefore, from time t3 to time t5, the first control signal (T1) has a logic high state. Referring back to Figure 3, the leading portion of the first control signal (T1) (from time t3 to time t4) is generated as the second control signal (T2) through the "mutually exclusive OR" gate 304, the inverter 306, and the "inverse OR" gate 308. Through the leading edge blocking circuit 302, the tail portion of the first control signal (T1) (from t4 to t5) is generated as the third control signal (T3).

[0066] Figure 5 illustrates a schematic diagram of a second embodiment of an LED driver shown in Figure 1 according to various embodiments of the present disclosure. The second embodiment of the LED driver is similar to the first embodiment of the LED driver shown in Figure 2, except that a second reference current path 232 is added. As shown in Figure 5, the second reference current path 232 is connected in parallel with the first reference current path 231. The second reference current path 232 includes a third p-type transistor MP3. The reference current IEF is mirrored to generate a second reference current IEF2 in the second reference current path 232. The sum of the first reference current IEF1 and the second reference current IEF2 is mirrored to generate a load current IL flowing through the power switch Q1.

[0067] The second reference current path 232 does not include a switch controlled by the PWM anti-spiking circuit 208. In operation, the second reference current IREF2 in the second reference current path 232 does not change. The PWM anti-spiking circuit 208 can only partially eliminate overshoot by turning off the first switch S1 in the first reference current path 231.

[0068] FIG6 illustrates a schematic diagram of a third embodiment of an LED driver shown in FIG1 according to various embodiments of the present disclosure. The third embodiment of the LED driver is similar to the second embodiment of the LED driver shown in FIG5, except that a third reference current path 233 and a fourth reference current path 234 are added to further improve the performance of the LED driver.

[0069] As shown in Figure 6, the third reference current path 233 is connected in parallel with the first reference current path 231. The third reference current path 233 includes a fourth p-type transistor MP4 and a second switch S2 connected in series. The second switch S2 is implemented as a p-type transistor. The second switch S2 is controlled by a PWM anti-spiking circuit 208.

[0070] The fourth reference current path 234 is connected in parallel with the first reference current path 231. The fourth reference current path 234 includes a fifth p-type transistor MP5 and a third switch S3 connected in series. The third switch S3 is implemented as a p-type transistor. The third switch S3 is controlled by a PWM anti-spiking circuit 208.

[0071] In operation, the reference current IREF is mirrored to generate a first reference current IREF1 in the first reference current path 231. The reference current IREF is mirrored to generate a second reference current IREF2 in the second reference current path 232. The reference current IREF is mirrored to generate a third reference current IREF3 in the third reference current path 233. The reference current IREF is mirrored to generate a fourth reference current IREF4 in the fourth reference current path 234. The sum of one of the first reference currents IREF1, the second reference current IREF2, the third reference current IREF3, and the fourth reference current IREF4 is mirrored to generate the load current IL flowing through the power switch Q1. In response to the overshoot of the reference voltage signal VREF, the PWM anti-spiking pulse circuit 208 is configured to turn off the control switches S1, S2, and S3 to reduce the sum of the reference currents, thereby reducing the overshoot of the load current IL flowing through the power switch Q1.

[0072] Figure 7 illustrates the various signals associated with the LED driver shown in Figure 6 according to various embodiments of this disclosure. The horizontal axis represents the time interval. There are three columns. The first column represents the PWM signal. The second column represents the LED current (LED_P) when a conventional LED driver is used to drive a light-emitting diode. The third column represents the LED current (LED_N) when the LED driver shown in Figure 6 is used to drive a light-emitting diode.

[0073] At time t1, the PWM signal changes from a logic low state to a logic high state. In response to this change, the PWM switch is turned on and power is supplied to the LED driver. After an appropriate circuit delay, the LED current begins to build up at time t2. When a conventional LED driver is used to drive an LED, there is an overshoot from t2 to t3. As shown in Figure 7, the LED current rapidly increases to a peak value, remains constant for a period of time, and then begins to decrease linearly to its steady-state value. In contrast, when the LED driver shown in Figure 6 is used to drive the LED, the LED current increases linearly to an intermediate value and then curves downward to a first valley. The LED current increases from the first valley to a first peak value and then decreases linearly to a second valley. The LED current increases from the second valley to a second peak value and then begins to decrease linearly to its steady-state value. The peak value in the third column (e.g., the second peak value) is much lower than the peak value in the second column.

[0074] FIG8 illustrates a schematic diagram of a fourth embodiment of an LED driver shown in FIG1 according to various embodiments of the present disclosure. The fourth embodiment of the LED driver is similar to the third embodiment of the LED driver shown in FIG6, except that a reference current subtraction circuit 802 is added to further improve the performance of the LED driver.

[0075] The reference current subtraction circuit 802 includes a first current subtraction transistor M11, a rising detection capacitor C11, a rising detection resistor R11, a second current subtraction transistor M12, a falling detection resistor R12, and a falling detection capacitor C12.

[0076] As shown in Figure 8, the first current subtraction transistor M11 is connected between the drain of the first n-type transistor MN1 and the second voltage bus VSS. A rise-detection capacitor C11 and a rise-detection resistor R11 are connected in series between the common node of the first p-type transistor MP1 and the resistor RSET and the second voltage bus VSS. One of the common nodes of the rise-detection capacitor C11 and the rise-detection resistor R11 is connected to the gate of the first current subtraction transistor M11.

[0077] The second current subtraction transistor M12 is connected between the drain of the first n-type transistor MN1 and the second voltage bus VSS. The fall detection resistor R12 and the fall detection capacitor C12 are connected in series between the common node of the first p-type transistor MP1 and the resistor RSET and the second voltage bus VSS. The common node of the fall detection resistor R12 and the fall detection capacitor C12 is connected to the gate of the second current subtraction transistor M12.

[0078] In operation, the reference current subtraction circuit 802 is configured to subtract a current component from the sum of reference currents, thereby reducing overshoot occurring at the leading edge of the load current IL. The rising detection capacitor C11 and rising detection resistor R11 set the delay timing of the rising segment of the overshoot signal, while the falling detection resistor R12 and falling detection capacitor C12 set the delay timing of the falling segment of the overshoot signal. To further improve the subtraction amplitude, only the channel widths of the first current subtraction transistor M11 and the second current subtraction transistor M12 need to be adjusted.

[0079] Figure 9 illustrates a flowchart of a method for controlling the LED driver shown in Figure 1 according to various embodiments of the present disclosure. This flowchart shown in Figure 9 is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize numerous variations, alternatives, and modifications. For example, the various steps illustrated in Figure 9 can be added, removed, replaced, reconfigured, and repeated.

[0080] At step 902, a predetermined reference current is generated using a reference current generating circuit coupled between a first voltage bus and a second voltage bus.

[0081] At step 904, the predetermined reference current is mirrored to generate a first reference current in a first reference current path including a first switch.

[0082] At step 906, a first switch is controlled by a PWM anti-spiking circuit to reduce an overshoot that occurs at the leading edge of a load current flowing through a power switch.

[0083] The method further includes mirroring a predetermined reference current to generate a second reference current in a second reference current path, and mirroring the sum of the first reference current and the second reference current to generate a load current flowing through a power switch, wherein the second reference current path is connected in parallel with the first reference current path.

[0084] The method further includes mirroring a predetermined reference current to generate a second reference current in a second reference current path, mirroring the predetermined reference current to generate a third reference current in a third reference current path, mirroring the predetermined reference current to generate a fourth reference current in a fourth reference current path, and mirroring the sum of one of the first reference current, the second reference current, the third reference current and the fourth reference current to generate a load current flowing through a power switch, wherein the second reference current path is connected in parallel with the first reference current path, the third reference current path is connected in parallel with the first reference current path, and wherein the third reference current path includes a second switch controlled by a PWM anti-spiking circuit, and the fourth reference current path is connected in parallel with the first reference current path, wherein the fourth reference current path includes a third switch controlled by a PWM anti-spiking circuit.

[0085] The reference current generation circuit includes: a first p-type transistor and a resistor connected in series between a first voltage bus and a second voltage bus; and a first amplifier having an inverting input configured to receive a bandgap reference, a non-inverting input connected to a common node of the first p-type transistor and the resistor, and an output connected to a gate of the first p-type transistor and a gate of a second p-type transistor. The first reference current path includes a second p-type transistor and a first switch connected in series, wherein the first p-type transistor and the second p-type transistor form a first current mirror, through which a predetermined reference current is mirrored to generate a first current in the first reference current path. A reference current and a second current mirror include: a first n-type transistor connected in series with a first reference current path; a second n-type transistor connected in series with a power switch, wherein the first n-type transistor and the second n-type transistor form a second current mirror through which the sum of the first reference current, the second reference current, the third reference current and the fourth reference current are mirrored to generate a load current flowing through the power switch; and a second amplifier having an inverting input connected to a drain of the first n-type transistor, a non-inverting input connected to a drain of the second n-type transistor, and an output connected to a gate of the first n-type transistor and a gate of the second n-type transistor.

[0086] The PWM anti-spiking circuit includes: a first inverter configured to receive a reference voltage signal proportional to a predetermined reference current; a second inverter having an input connected to an output of the first inverter and configured to generate an output of a first control signal applied to a gate of a first switch; a leading-edge blocking circuit having an input configured to receive the first control signal and an output configured to generate a third control signal applied to a gate of a third switch; and a "mutually exclusive OR" circuit. A gate, an inverter, and an "inverse OR" gate are cascaded together, wherein a first input of one of the "mutually exclusive OR" gates is configured to receive a first control signal, a second input of one of the "mutually exclusive OR" gates is configured to receive a third control signal, an input of one of the inverters is connected to an output of one of the "mutually exclusive OR" gates, a first input of one of the "inverse OR" gates is configured to receive the third control signal, a second input of one of the "inverse OR" gates is connected to an output of one of the inverters, and an output of one of the "inverse OR" gates is configured to generate a second control signal applied to one of the gates of one of the second switches.

[0087] Although this description has been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of this disclosure as defined by the appended claims. Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, as those skilled in the art will readily understand from this disclosure that, based on this disclosure, existing or later-developed programs, machines, articles of manufacture, components, methods, or steps can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such programs, machines, articles of manufacture, components, methods, or steps within their scope. [Simplified Explanation of the Diagram]

[0012] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description, together with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram illustrating one of the various embodiments of a light-emitting diode system according to the present disclosure;

[0014] FIG2 illustrates a schematic diagram of a first embodiment of an LED driver shown in FIG1 according to various embodiments of the present disclosure;

[0015] Figure 3 illustrates a schematic diagram of a PWM anti-spiking circuit shown in Figure 2 according to various embodiments of the present disclosure;

[0016] Figure 4 illustrates various signals associated with the PWM anti-spiking circuit shown in Figure 3 according to various embodiments of this disclosure;

[0017] Figure 5 illustrates a schematic diagram of a second embodiment of an LED driver shown in Figure 1 according to various embodiments of the present disclosure;

[0018] Figure 6 illustrates a schematic diagram of a third embodiment of an LED driver shown in Figure 1 according to various embodiments of the present disclosure;

[0019] Figure 7 illustrates various signals associated with the LED driver shown in Figure 6 according to various embodiments of the present disclosure;

[0020] Figure 8 illustrates a schematic diagram of a fourth embodiment of an LED driver shown in Figure 1 according to various embodiments of the present disclosure; and

[0021] Figure 9 illustrates a flowchart of a method for controlling an LED driver shown in Figure 1 according to various embodiments of the present disclosure.

[0022] The corresponding numbers and symbols in different figures generally refer to the corresponding components, unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

Claims

1. A device for reducing current overshoot in an LED, comprising: A reference current generation circuit coupled between a first voltage bus and a second voltage bus, wherein the reference current generation circuit is configured to generate a predetermined reference current; a first reference current path including a first switch, wherein the predetermined reference current is configured to be mirrored to generate a first reference current in the first reference current path; a load current path including a power switch; and a pulse width modulation (PWM) anti-spiking circuit configured to control the first switch to reduce an overshoot occurring at a leading edge of a load current flowing through the power switch.

2. The apparatus of claim 1, wherein: The first reference current is mirrored to generate the load current flowing through the power switch.

3. The apparatus of claim 1, further comprising: A second reference current path is connected in parallel with the first reference current path, wherein: the second reference current path includes a third p-type transistor; the predetermined reference current is configured to be mirrored to generate a second reference current in the second reference current path; and the sum of the first reference current and the second reference current is mirrored to generate the load current flowing through the power switch.

4. The apparatus of claim 1, further comprising: A second reference current path is connected in parallel with the first reference current path; a third reference current path is connected in parallel with the first reference current path, wherein the third reference current path includes a fourth p-type transistor and a second switch connected in series, and wherein the second switch is controlled by the PWM anti-spiking circuit; and a fourth reference current path is connected in parallel with the first reference current path, wherein the fourth reference current path includes a fifth p-type transistor and a third switch connected in series, and wherein the third switch is controlled by the PWM anti-spiking circuit, wherein: the predetermined reference current is configured to be mirrored to generate a second reference current in the second reference current path; the predetermined reference current is configured to be mirrored to generate a third reference current in the third reference current path; the predetermined reference current is configured to be mirrored to generate a fourth reference current in the fourth reference current path; and the sum of the first reference current, the second reference current, the third reference current and the fourth reference current is mirrored to generate the load current flowing through the power switch.

5. The apparatus of claim 4, wherein the PWM anti-spiking circuit comprises: A first inverter configured to receive a reference voltage signal proportional to the predetermined reference current; a second inverter having an input connected to an output of the first inverter and an output configured to generate a first control signal applied to a gate of the first switch; a leading-edge blocking circuit having an input configured to receive the first control signal and an output configured to generate a third control signal applied to a gate of the third switch; and a cascaded OR gate, an inverter, and an NOR gate, wherein: a first input of the OR gate is configured to receive the first control signal; a second input of the OR gate is configured to receive the third control signal; an input of the inverter is connected to an output of the OR gate; and a first input of the NOR gate is configured to receive the third control signal. The second input of the "inverse OR" gate is connected to one output of the inverter; and the output of the "inverse OR" gate is configured to generate a second control signal applied to one gate of the second switch.

6. The apparatus of claim 1, wherein: The reference current generation circuit includes: a first p-type transistor and a resistor connected in series between the first voltage bus and the second voltage bus; and a first amplifier having an inverting input configured to receive a bandgap reference, a non-inverting input connected to a common node of the first p-type transistor and the resistor, and an output connected to a gate of the first p-type transistor and a gate of the second p-type transistor; and the first reference current path includes the second p-type transistor and the first switch connected in series, wherein the first p-type transistor and the second p-type transistor form a first current mirror, through which the predetermined reference current is mirrored to generate the first reference current in the first reference current path.

7. The apparatus of claim 6, further comprising: A first n-type transistor connected in series with the first reference current path; a second n-type transistor connected in series with the power switch, wherein the first n-type transistor and the second n-type transistor form a second current mirror, through which the first reference current is mirrored to generate the load current flowing through the power switch; and a second amplifier having an inverting input connected to a drain of the first n-type transistor, a non-inverting input connected to a drain of the second n-type transistor, and an output connected to a gate of the first n-type transistor and a gate of the second n-type transistor.

8. The apparatus of claim 7, further comprising: A reference current subtraction circuit configured to reduce a first reference current in order to reduce the overshoot occurring at the leading edge of the load current, wherein the reference current subtraction circuit includes: a first current subtraction transistor connected between the drain of the first n-type transistor and the second voltage bus; a rising detection capacitor and a rising detection resistor connected in series between the common node of the first p-type transistor and the resistor and the second voltage bus, wherein the common node of the rising detection capacitor and the rising detection resistor is connected to the gate of the first current subtraction transistor; a second current subtraction transistor connected between the drain of the first n-type transistor and the second voltage bus; and a falling detection resistor and a falling detection capacitor connected in series between the common node of the first p-type transistor and the resistor and the second voltage bus, wherein the common node of the falling detection resistor and the falling detection capacitor is connected to the gate of the second current subtraction transistor.

9. The apparatus of any one of claims 1 to 8, further comprising: A low-dropout regulator having an input configured to receive an input voltage and an output configured to generate a bias voltage; an undervoltage lockout circuit configured to receive the bias voltage and generate a control signal applied to a gate of a power switch; and a bandgap reference circuit configured to receive a bias voltage from a bias power supply and generate a bandgap reference.

10. The apparatus of any one of claims 1 to 8, further comprising: A gate protection circuit is connected between a gate of a power switch and a second voltage bus. The gate protection circuit includes a first resistor, a second resistor, a capacitor, and a third n-type transistor. Specifically: the third n-type transistor is connected between the gate of the power switch and the second voltage bus; the capacitor and the first resistor are connected in series between the gate of the power switch and the second voltage bus; and the second resistor is connected between the gate of the power switch and the second voltage bus.

11. The apparatus of any one of claims 1 to 8, further comprising: A starting circuit includes a third current mirror, which includes a fourth n-type transistor, a fifth n-type transistor, and a sixth p-type transistor, wherein: the sixth p-type transistor and the fifth n-type transistor are connected in series between the first voltage bus and the second voltage bus; the power switch is connected in series with the fourth n-type transistor; and the predetermined reference current is configured to be mirrored to generate a current flowing through the sixth p-type transistor.

12. A method for reducing current overshoot in an LED, comprising: A predetermined reference current is generated using a reference current generation circuit coupled between a first voltage bus and a second voltage bus; and the predetermined reference current is mirrored to generate a first reference current in a first reference current path including a first switch; and the first switch is controlled by a PWM anti-spiking circuit to reduce an overshoot occurring at a leading edge of a load current flowing through a power switch.

13. The method of claim 12, further comprising: The predetermined reference current is mirrored to generate a second reference current in a second reference current path; and the sum of the first reference current and the second reference current is mirrored to generate the load current flowing through the power switch, wherein the second reference current path is connected in parallel with the first reference current path.

14. The method of claim 12, further comprising: The predetermined reference current is mirrored to generate a second reference current in a second reference current path; the predetermined reference current is mirrored to generate a third reference current in a third reference current path; the predetermined reference current is mirrored to generate a fourth reference current in a fourth reference current path; and the sum of one of the first reference current, the second reference current, the third reference current, and the fourth reference current is mirrored to generate the load current flowing through the power switch, wherein: the second reference current path is connected in parallel with the first reference current path; the third reference current path is connected in parallel with the first reference current path, and wherein the third reference current path includes a second switch controlled by the PWM anti-spiking circuit; and the fourth reference current path is connected in parallel with the first reference current path, and wherein the fourth reference current path includes a third switch controlled by the PWM anti-spiking circuit.

15. As in request item 14, wherein: The reference current generation circuit includes: a first p-type transistor and a resistor connected in series between the first voltage bus and the second voltage bus; and a first amplifier having an inverting input configured to receive a bandgap reference, a non-inverting input connected to a common node of the first p-type transistor and the resistor, and an output connected to a gate of the first p-type transistor and a gate of a second p-type transistor; the first reference current path includes the second p-type transistor and the first switch connected in series, wherein the first p-type transistor and the second p-type transistor form a first current mirror, through which a predetermined reference current is mirrored to generate the first reference current in the first reference current path; and a second current mirror includes: a first n-type transistor connected in series with the first reference current path; A second n-type transistor connected in series with the power switch, wherein the first n-type transistor and the second n-type transistor form a second current mirror, through which the sum of the first reference current, the second reference current, the third reference current and the fourth reference current is mirrored to generate the load current flowing through the power switch; and a second amplifier having an inverting input connected to a drain of the first n-type transistor, a non-inverting input connected to a drain of the second n-type transistor, and an output connected to a gate of the first n-type transistor and a gate of the second n-type transistor.

16. The method of claim 14 or 15, wherein the PWM anti-spiking circuit comprises: A first inverter configured to receive a reference voltage signal proportional to the predetermined reference current; a second inverter having an input connected to an output of the first inverter and configured to generate an output of a first control signal applied to a gate of the first switch; a leading-edge blocking circuit having an input configured to receive the first control signal and configured to generate an output of a third control signal applied to a gate of the third switch; and a cascaded OR gate, an inverter, and an NOR gate, wherein: a first input of the OR gate is configured to receive the first control signal; a second input of the OR gate is configured to receive the third control signal; an input of the inverter is connected to an output of the OR gate; and a first input of the NOR gate is configured to receive the third control signal. The second input of the "inverse OR" gate is connected to one output of the inverter; and the output of the "inverse OR" gate is configured to generate a second control signal applied to one gate of the second switch.

17. A system for reducing current overshoot in an LED, comprising: A PWM switch, an integrated circuit, and a light-emitting diode are connected in series between a power supply and ground. The system controller is configured to control the PWM switch, wherein the integrated circuit includes: a low-dropout regulator having an input configured to receive an input voltage and an output configured to generate a bias voltage on a first voltage bus; an undervoltage lockout circuit configured to receive the bias voltage and generate a control signal applied to a gate of a power switch, wherein a current flowing through the power switch is approximately equal to a current flowing through the light-emitting diode; a bandgap reference circuit configured to receive the bias voltage and generate a bandgap reference; and a reference current generation circuit coupled between the first voltage bus and a second voltage bus, wherein the reference current generation circuit is configured to generate a predetermined reference current. A first reference current path including a first switch, wherein the predetermined reference current is configured to be mirrored to generate a first reference current in the first reference current path; and a PWM anti-spiking circuit configured to control the first switch to reduce an overshoot occurring at a leading edge of a load current flowing through the power switch.

18. The system as described in request item 17, wherein: The reference current generation circuit includes: a first p-type transistor and a resistor connected in series between the first voltage bus and the second voltage bus; and a first amplifier having an inverting input configured to receive a bandgap reference, a non-inverting input connected to a common node of the first p-type transistor and the resistor, and an output connected to a gate of the first p-type transistor and a gate of the second p-type transistor; and the first reference current path includes the second p-type transistor and the first switch connected in series, wherein the first p-type transistor and the second p-type transistor form a first current mirror, through which the predetermined reference current is mirrored to generate the first reference current in the first reference current path.

19. The system of claim 18, further comprising: A second reference current path is connected in parallel with the first reference current path; a third reference current path is connected in parallel with the first reference current path, wherein the third reference current path includes a fourth p-type transistor and a second switch connected in series, and wherein the second switch is controlled by the PWM anti-spiking circuit; a fourth reference current path is connected in parallel with the first reference current path, wherein the fourth reference current path includes a fifth p-type transistor and a third switch connected in series, and wherein the third switch is controlled by the PWM anti-spiking circuit, wherein: the predetermined reference current is configured to be mirrored to generate a second reference current in the second reference current path; the predetermined reference current is configured to be mirrored to generate a third reference current in the third reference current path; the predetermined reference current is configured to be mirrored to generate a fourth reference current in the fourth reference current path; and the sum of the first reference current, the second reference current, the third reference current and the fourth reference current is mirrored to generate the load current flowing through the power switch; A first n-type transistor connected in series with the first reference current path; a second n-type transistor connected in series with the power switch, wherein the first n-type transistor and the second n-type transistor form a second current mirror, through which the first reference current is mirrored to generate the load current flowing through the power switch; and a second amplifier having an inverting input connected to a drain of the first n-type transistor, a non-inverting input connected to a drain of the second n-type transistor, and an output connected to a gate of the first n-type transistor and a gate of the second n-type transistor.

20. The system of claim 17 or 18 further includes: A gate protection circuit is connected between a gate of a power switch and a second voltage bus, wherein the second voltage bus is a common node of the integrated circuit and the light-emitting diode, and wherein the gate protection circuit includes a first resistor, a second resistor, a capacitor, and a third n-type transistor, wherein: the third n-type transistor is connected between the gate of the power switch and the second voltage bus; the capacitor and the first resistor are connected in series between the gate of the power switch and the second voltage bus; and the second resistor is connected between the gate of the power switch and the second voltage bus; and a starting circuit includes a third current mirror, the third current mirror including a fourth n-type transistor, a fifth n-type transistor, and a sixth p-type transistor, wherein: the sixth p-type transistor and the fifth n-type transistor are connected in series between the first voltage bus and the second voltage bus; The power switch is connected in series with the fourth n-type transistor; and the predetermined reference current is configured to be mirrored to generate a current flowing through one of the sixth p-type transistors.

21. The system of claim 19, wherein the PWM anti-spiking circuit includes: A first inverter configured to receive a reference voltage signal proportional to the predetermined reference current; a second inverter having an input connected to an output of the first inverter and an output configured to generate a first control signal applied to a gate of the first switch; a leading-edge blocking circuit having an input configured to receive the first control signal and an output configured to generate a third control signal applied to a gate of the third switch; and a cascaded OR gate, an inverter, and an NOR gate, wherein: a first input of the OR gate is configured to receive the first control signal; a second input of the OR gate is configured to receive the third control signal; an input of the inverter is connected to an output of the OR gate; and a first input of the NOR gate is configured to receive the third control signal. The second input of the "inverse OR" gate is connected to one output of the inverter; and the output of the "inverse OR" gate is configured to generate a second control signal applied to one gate of the second switch.

22. The system of claim 19, further comprising: A reference current subtraction circuit configured to reduce a first reference current in order to reduce the overshoot occurring at the leading edge of the load current, wherein the reference current subtraction circuit includes: a first current subtraction transistor connected between the drain of the first n-type transistor and the second voltage bus; a rising detection capacitor and a rising detection resistor connected in series between the common node of the first p-type transistor and the resistor and the second voltage bus, wherein the common node of the rising detection capacitor and the rising detection resistor is connected to the gate of the first current subtraction transistor; a second current subtraction transistor connected between the drain of the first n-type transistor and the second voltage bus; and a falling detection resistor and a falling detection capacitor connected in series between the common node of the first p-type transistor and the resistor and the second voltage bus, wherein the common node of the falling detection resistor and the falling detection capacitor is connected to the gate of the second current subtraction transistor.

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