A method of forming transistors and silicide regions

Abstract

A method includes forming source / drain regions, forming a contact etch-stop layer over the source / drain regions, forming an interlayer dielectric over the contact etch-stop layer, and performing an etching process to form contact openings in the interlayer dielectric and the contact etch-stop layer. The source / drain regions are exposed to the contact openings. A silicon formation process is performed to form silicon regions on the surface of the source / drain regions. An etching process is performed to remove metal deposited on the dielectric regions, wherein the dielectric regions are exposed during a first silicon formation process. A contact plug is formed in the contact opening.

Description

Prior Technology

[0001] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by the following steps: sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0002] The semiconductor industry continues to increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise and need to be addressed. Simple Explanation of the Diagram

[0003] The present disclosure is best understood when read in conjunction with the accompanying drawings, based on the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for ease of discussion, the dimensions of the various features may be arbitrarily increased or decreased. Figures 1A and 1B through 9A and 9B are views of intermediate stages in the formation of a complementary field-effect transistor (CFET) and silicide regions according to some embodiments. Figures 10A and 10B through 13A and 13B are views of intermediate stages in the formation of the CFET and silicon region according to some embodiments. Figures 14A and 14B through 19A and 19B are views of intermediate stages in the formation of the CFET and silicon region according to some embodiments. Figures 20 through 23 are views of intermediate stages in the formation of the CFET and silicon regions according to some embodiments. Figure 24 illustrates a flowchart of forming the CFET and silicon region according to some embodiments. Implementation

[0004] The following disclosure provides numerous different embodiments or instances of various features for implementing some embodiments of this disclosure. Specific examples of components and configurations are described below to simplify some embodiments of this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, some embodiments of this disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, for ease of description, spatial relative terms such as “under,” “below,” “lower,” “overlapping,” “upper,” and the like are used in some embodiments of this disclosure to describe the relationship between one element or feature and another element(s) shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used in some embodiments of this disclosure may be interpreted accordingly.

[0006] This invention provides a complementary field-effect transistor (CFET), a silicide region, and a method for forming the same. According to some embodiments disclosed herein, the silicide region is formed by depositing metal and simultaneously reacting with an epitaxial semiconductor layer to form the silicide region. An etching process can be performed to remove unwanted metal deposited on the surface of the dielectric region. A reduction process can be performed to reduce metal oxides formed due to vacuum disruption back to elemental metals. [, , ]

[0007] It should be understood that while CFETs include gate-all-around (GAA) transistors (such as nanostructured FETs) as examples, the concepts of some embodiments disclosed herein can also be applied to the formation of silicide regions for other types of transistors, such as planar transistors, Fin Field-Effect Transistors (FinFETs), and the like. Throughout the description, the terms "FET" and "transistor" are used interchangeably.

[0008] The embodiments described in this disclosure are intended to provide examples enabling the making or use of the main body of some embodiments of this disclosure, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, similar reference numerals are used to designate similar elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order. [, , ]

[0009] Figures 1A and 1B through 9A and 9B illustrate cross-sectional views of intermediate stages in the formation of the CFET and silicon regions according to some embodiments of this disclosure. The corresponding process is also schematically reflected in the process flow shown in Figure 24.

[0010] Figure 1A illustrates the formation of an exemplary CFET 10 (including FETs (transistors) 10U and 10L) according to some embodiments. Individual processes are illustrated as process 202 in the process flow 200 shown in Figure 24. The CFET 10 may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type), opposite to the first device type.

[0011] The nanostructure FETs 10U and 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26'L and an upper semiconductor nanostructure 26'U), wherein the semiconductor nanostructure 26 serves as the channel region of the nanostructure FET. The lower semiconductor nanostructure 26'L is used in the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26'U is used in the upper nanostructure FET 10U.

[0012] As shown in Figure 1A, a wafer 2 including a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The SOI substrate may include a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, such as a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, or the like, or combinations thereof.

[0013] In the illustrated example, each of the upper FET 10U and the lower FET 10L includes two semiconductor layers 26'U and 26'L as channels, respectively. It should be understood that the upper FET 10U and the lower FET 10L may include any number of channel regions, such as one, two, three, or more. The portion of the gate stack 90 covering and / or lying beneath the channel regions 26 forms a multilayer stack with the corresponding channel regions 26'U and 26'L.

[0014] Gate stacks 90 (including an upper gate stack 90U and a lower gate stack 90L) are formed between semiconductor layers 26. The upper gate stack 90U includes a gate dielectric 78 and an upper gate electrode 80U. The lower gate stack 90L includes a gate dielectric 78 and a lower gate electrode 80L. The gate dielectric 78 surrounds (when viewed in side view) the respective semiconductor nanostructures 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. A dielectric isolation layer 56 is formed to isolate the gate stack 90U of the upper FET 10U from the gate stack 90L of the lower FET 10L. A dummy semiconductor layer 26'M may be formed to contact the dielectric isolation layer 56.

[0015] Source / drain regions 62 (including lower source / drain region 62L and upper source / drain region 62U) are disposed on opposite sides of gate dielectric 78 and individual gate electrodes 80. The source / drain regions may individually or collectively refer to the source or drain depending on the context.

[0016] Internal spacers 54, serving as dielectric spacers, are formed on opposite sides of the portion of the gate stack 90 located between the semiconductor layers 26. The internal spacers 54 electrically insulate the source / drain regions 62L and 62U from the corresponding portions of the gate stack 90 to prevent and reduce leakage.

[0017] Gate spacers 44 are formed above the multilayer stack and on the sidewalls of the gate stack 90. ​​Gate spacers 44 may be formed by conformally forming one or more dielectric layers and subsequently anisotropically etching such dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like.

[0018] Source / drain regions 62L and 62U are laterally formed between the multilayer stack including channel region 26 and gate stack 90. ​​The lower source / drain region 62L is formed above and in contact with the substrate including semiconductor substrate 20. The lower source / drain region 62L is further in contact with the lower semiconductor nanostructure 26'L, but not with the upper semiconductor nanostructure 26'U.

[0019] The lower source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower source / drain region 62L is an n-type source / drain region, the individual materials may include silicon or carbon-doped silicon, doped with n-type dopants such as phosphorus, arsenic, or the like. When the lower source / drain region 62L is a p-type source / drain region, the individual materials may include silicon or silicon-germanium, doped with p-type dopants such as boron, indium, or the like. The lower source / drain region 62L may be in-situ doped and may or may not have the corresponding p-type or n-type dopants implanted.

[0020] A first contact etch-stop layer (CESL) 66 and a first ILD 68 are formed above the lower source / drain region 62L. Suitable dielectric materials for the first ILD 68 may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like. The first CESL 66 may be formed from a dielectric material that exhibits high etch selectivity for etching the first ILD 68. For example, the first CESL 66 may comprise silicon nitride, silicon oxide, silicon oxynitride, or the like, which can be formed by any suitable deposition process, such as CVD, ALD, or the like.

[0021] The upper source / drain region 62U is formed to overlap with the first CESL 66 and the first ILD 68, and also overlaps with the lower source / drain region 62L. Depending on the desired conductivity type of the upper source / drain region 62U, the material of the upper source / drain region 62U can be selected from the same group of candidate materials used to form the lower source / drain region 62L.

[0022] The conductivity type of the upper source / drain region 62U can be opposite to that of the lower source / drain region 62L. In other words, the upper source / drain region 62U can be doped in the opposite way to the lower source / drain region 62L. The upper source / drain region 62U can be doped in situ and / or implanted with n-type or p-type dopants.

[0023] The second CESL 70 and the second ILD 72 are formed above the upper source / drain region 62U. The materials and formation methods may be similar to, or different from, those of the first CESL 66 and the first ILD 68, and will not be discussed in detail here.

[0024] Figure 1B illustrates a cross-sectional view of the structure shown in Figure 1A. The cross-section shown may be cross-section 1B-1B in Figure 1A. Dielectric isolation region 32, sometimes also referred to as shallow trench isolation (STI) region 32, is formed above substrate 20. Semiconductor strips 20' (also refer to Figure 1A) are formed between STI regions 32. Fin spacers 45 may be formed on the top sidewall of semiconductor strips 20'. Lower source / drain region 62L, first CESL 66, first ILD 68, upper source / drain region 62U, second CESL 70, and second ILD 72 are shown.

[0025] Figure 1B further illustrates the formation of the contact plug 116. According to some embodiments, the formation of the contact plug 116 includes etching the second ILD 72, the second CESL 70, the first ILD 68, and the first CESL 66 to form a trench. The trench may extend to an intermediate level between the top and bottom surfaces of the isolation region 32. [, , ]

[0026] Dielectric pad 114 is formed in the trench. According to some embodiments, the formation of dielectric pad 114 includes deposition using conformal deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or the like to form a conformal dielectric layer. According to some embodiments, the material of dielectric pad 114 may include silicon oxide; silicon nitride; metal oxides of metals such as Hf, Ti, Al, W, Nb, Re, or the like; metal nitrides of metals such as Hf, Ti, Al, W, Nb, Re, or the like; or combinations thereof. [, , ]

[0027] Contact plug 116 is then formed. Contact plug 116 may also be referred to as a vertical partial interconnect. According to some embodiments, contact plug 116 comprises a metal, such as tungsten, molybdenum, ruthenium, iridium, or similar materials, or alloys thereof. According to some embodiments, contact plug 116 has a single-layer structure, wherein the entire contact plug 116 is formed of a homogeneous material such as described above.

[0028] According to an alternative embodiment, the formation of the contact plug 116 may include depositing a barrier layer, which may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. Next, a metallic material is deposited on and in contact with the barrier layer. The metallic material may include tungsten, cobalt, copper, nickel, molybdenum, ruthenium, iridium, or the like, or combinations thereof. [, , ]

[0029] After depositing the material used to form the contact plug 116, a planarization process, such as CMP or mechanical polishing, is performed to remove excess portions of one or more of the deposited material, leaving the contact plug 116. Thus, the contact plug 116 is surrounded by a dielectric pad 114. The top surfaces of the contact plug 116 and the dielectric pad 114 are coplanar, and may further be coplanar with the top surface of the second ILD 72 when the second ILD 72 is the top layer in the structure.

[0030] Referring to Figures 2A and 2B, an etch stop layer 118 and a dielectric layer 120 are formed. Each process is illustrated as process 204 in the process flow 200 shown in Figure 24. The etch stop layer 118 may comprise AlN, AlO, SiOC, or similar materials, or multiple layers thereof. The dielectric layer 120 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or similar materials. The etch stop layer 118 and the dielectric layer 120 are patterned by etching to form openings 121 and 122 through which the second ILD 72 and the contact plug 116 are exposed.

[0031] Figures 3A and 3B illustrate cross-sectional views of further forming source / drain contact openings 121 and 122 according to some embodiments. Each process is illustrated as process 206 in the process flow 200 shown in Figure 24. The cross-sectional view shown in Figure 3A is obtained from cross-sections 3A-3A in Figure 3B, and the cross-sectional view shown in Figure 3B is obtained from cross-sections 3B-3B in Figure 3A.

[0032] Contact openings 121 and 122 are formed through an etching process. During the etching process, the underlying second ILD 72, second CESL 70, contact plug 116, and dielectric pad 114 are exposed. The second ILD 72 and second CESL 70 are etched to expose the upper source / drain region 62U. On the right side of the illustrated contact plug 116, etching is performed through portions of the upper source / drain region 62U, followed by etching of the underlying first ILD 68 and first CESL 66. The etching terminates on the top surface of the lower epitaxial source / drain region 62L. Some top surfaces of the upper epitaxial source / drain region 62U may also be exposed. For example, on the left side of the illustrated contact plug 116, contact opening 121 terminates on the top surface of one of the upper source / drain regions 62U.

[0033] It should be understood that etching can be performed using one or more etch masks to achieve the desired pattern. For example, one etch mask can be used to etch through the upper source / drain region 62U, wherein the etching terminates on the lower source / drain region 62L. Another etch mask can be used to etch portions of the second ILD 72 and the second CESL 70, such that the top surface of a portion of the upper source / drain region 62U is exposed.

[0034] Referring to Figures 4A and 4B, dielectric pad 124 is formed. Individual processes are illustrated as process 208 in the process flow 200 shown in Figure 24. According to some embodiments, the formation of dielectric pad 124 includes depositing a conformal dielectric layer through a conformal deposition process, such as ALD, CVD, PVD, or the like. An anisotropic etching process is then performed to remove the horizontal portions of the conformal layer, leaving the vertical portions as dielectric pad 124.

[0035] The material of dielectric pad 124 may be selected from the same set of candidate materials used to form dielectric pad 114, and may be the same as or different from the material of dielectric pad 114. For example, dielectric pad 124 may be formed of and / or contain silicon nitride.

[0036] Referring to Figures 5A and 5B, silicide regions 126P are selectively formed. Individual processes are illustrated as process 210 in the process flow 200 shown in Figure 24. According to some embodiments, the formation of silicide regions 126P may include conducting certain precursors capable of reacting with germanium but not with silicon into individual reaction chambers. Thus, p-type silicide regions 126P are selectively formed on germanium or SiGe, while no silicide regions are formed on the exposed surfaces of the upper source / drain regions 62U (which may contain Si but not Ge) and the dielectric exposed surfaces. According to one embodiment, the precursors that may lead to the selective formation of silicide regions 126P may contain M(DAD)x (where M represents a metal and x is an integer). For example, the precursor may contain bis(1,4-di-tert-butyl-1,3-diazabutadienyl)nickel(II) (Ni(DAD)2) or MeCpMMex (such as trimethyl(methylcyclopentadienyl)platinum(IV)), where the second M indicates a metal and x indicates a number or the like. Additionally, an etching gas such as HCl is added to the precursor so that the silicate does not grow on the exposed dielectric material.

[0037] Throughout this description, silicates include silicates with a work function (these silicates are referred to as p-silicides), silicates with a low work function (these silicates are referred to as n-silicides), and silicates with a medium work function (medium work function silicates) that lies between the work functions of p-silicides and n-silicides. For example, a medium work function silicate may have a work function in the range of about 4.2 eV to about 4.4 eV. A p-silicide may have a work function greater than about 4.4 eV. An n-silicide may have a work function lower than about 4.2 eV.

[0038] According to some embodiments, silicates with a work function close to that of titanium silicate can be considered medium work function silicates, and silicates with a work function greater than that of Ti silicate (metal) are p-silicides. Conversely, silicates with a work function lower than that of Ti silicate (metal) are n-silicides. Medium work function silicates may include VSi, ZnSi, NbSi, AlSi, and the like.

[0039] According to some embodiments, depending on the precursor used, the p-type silicate region 126P may include (other than Ge or SiGe) a metal selected from molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), palladium (Pd), platinum (Pt), tungsten (W), cobalt (Co), chromium (Cr), osmium (Os), rhenium (Re), rhodium (Rh), iron (Fe), manganese (Mn), vanadium (V), tantalum (Ta), and combinations thereof.

[0040] For the silicide process, gases such as Ar, H2, and / or similar gases are conducted together with one or more precursor gases. Plasma (and RF power) is also activated. Additionally, wafer 2 is heated to a temperature, for example, between approximately 300°C and approximately 600°C. The metal in the precursor is deposited on the lower source / drain region 62L and reacts with the exposed surface layer of the lower source / drain region 62L to form a p-type silicide region 126P.

[0041] According to some embodiments, no additional annealing process is performed after the siliconization process to form the p-type siliconization region 126P. Furthermore, due to the high selectivity of the selective etching process, the metal in the precursor is not deposited on the surface of the dielectric material (such as the dielectric pad 124).

[0042] Figures 6A and 6B illustrate the formation of n-type silicide regions 130N (including n-type silicide regions 130N1 and 130N2). Individual processes are illustrated as process 212 in the process flow 200 shown in Figure 24. According to some embodiments, the formation process may include transferring a precursor containing an n-type metal into a corresponding reaction chamber.

[0043] The n-type metal may contain Zr, Sb, Ce, Sc, Y, Ub, Er, or similar elements, or combinations thereof. It can conduct gases such as Ar, H2, or similar substances. Plasma can also be initiated. Additionally, wafer 2 is heated to a temperature, for example, between approximately 300°C and approximately 600°C. The n-type silicide region 130N can be formed in situ simultaneously with the formation of the p-type silicide region 126P, without vacuum disruption between the two processes.

[0044] During the deposition process, silicon and Ge in the lower source / drain region 62L diffuse upward through the p-type silicate region 126P and react with the metal deposited from the precursor to form an n-type silicate region 130N1, which is located above the p-type silicate region 126P. Above the upper source / drain region 62U, silicon reacts with the metal deposited from the precursor to form an n-type silicate region 130N2. According to some embodiments, no additional annealing process is performed after the silicate process to form the n-type silicate region 130N. The n-type silicate regions 130N1 and 130N2 are collectively referred to as n-type silicate region 130N.

[0045] In the siliconization process, due to the low selectivity in the deposition of n-type metals, a thin metal layer 132 is deposited on the surface of the dielectric layer simultaneously with the siliconization process. Therefore, the metal layer 132 contains the same metal as the n-type siliconized region 130N. The metal in the metal layer 132 may contain one or more elemental metals, which include metal atoms rather than metal compounds. It should be understood that although the metal layer 132 is illustrated as a continuous layer, it may also be a discontinuous layer comprising a plurality of discrete metal islands. The surface of the underlying dielectric region (such as dielectric pad 124) may be exposed through the discrete metal islands. Exemplary discrete metal islands may be represented by discrete metal regions 182A and 182B, as shown in Figure 23.

[0046] Referring further to Figures 6A and 6B, an etching process 134 is performed to selectively etch the metal layer 132 without etching the silicate regions 132N (including silicate regions 132N1 and 132N2) and exposed dielectric regions (such as dielectric pads 124). Individual processes are illustrated as process 214 in the process flow 200 shown in Figure 24. According to some embodiments, selective etching is performed using an immersion process with an etching gas comprising one or more metal halides. The resulting structure is shown in Figures 7A and 7B.

[0047] Metal halides may be selected from titanium chloride (TiCl4), nickel halides (e.g., nickel fluoride (NiF2), nickel dichloride (NiCl2), nickel bromide (NiBr2), nickel iodide (NiI2), molybdenum halides (e.g., molybdenum fluoride (MoF4 and / or MoF5), molybdenum chloride (MoCl2, MoCl3, MoCl4, MoCl5, MoCl6), molybdenum bromide (MoBr2MoBr4) and the like), platinum halides (e.g., platinum fluoride (PtF2, PtF3), platinum chloride (PtCl2, PtCl4), platinum bromide (PtBr2), platinum iodide (PtI2, PtI4 and the like), palladium halides, etc. Cobalt halides (e.g., palladium fluoride (PdF2, PdF3, PdF4, PdF6), palladium dichloride (PdCl2, PdCl3, PdCl4), palladium bromide (PdBr2, PdBr4), palladium iodide (PdI2, PdI4), cobalt halides (e.g., cobalt fluoride (CoF2, CoF3), cobalt chloride (CoCl2, CoCl3), cobalt iodide (CoI2), titanium halides (e.g., titanium fluoride (TiF3, TiF4), titanium chloride (TiCl2, TiCl3, TiCl4), titanium bromide (TiBr2, TiBr3, TiBr4), titanium iodide (TiI2, TiI4) and the like).

[0048] Metal halides may also be selected from erbium halides (e.g., erbium fluoride (ErF2, ErF3), erbium chloride (ErCl3), erbium bromide (ErBr3), erbium iodide (ErI3) and the like), zirconium halides (e.g., zirconium fluoride (ZrF3, ZrF4), zirconium chloride (ZrCl2, ZrCl3, ZrCl4), zirconium bromide (ZrBr2, ZrBr3, ZrBr4), zirconium iodide (ZrI2, ZrI4 and the like), hafnium halides (hafnium fluoride (HfF3, HfF4), hafnium chloride (HfCl2, HfCl3, HfCl4)). Hafnium bromide (HfBr2, HfBr3, HFBr4), hafnium iodide (HfI2, HfI4 and the like), tungsten halides (e.g., tungsten fluoride (WF4, WF6), tungsten chloride (WCl2, WCl3, WCl4, WCl5, WCl6), tungsten bromide (WBr2, WBr5, WBr6), ruthenium halides (e.g., ruthenium chloride (RuCl2, RuCl3, RuCl4), ruthenium bromide (RuBr3, RuBr4), ruthenium fluoride (RuF3, RuF4), ruthenium iodide (RuI3 and the like), or combinations thereof.

[0049] The etching gas may or may not include hydrogen halides, such as HF, HBr, HCl, HI, or similar substances, or combinations thereof. No plasma is generated during the etching process. RF power may not be applied, or the applied RF power may be insufficient to generate plasma. Furthermore, Ar may not be introduced, and H2 may also not be introduced.

[0050] According to some embodiments, etching can be performed at wafer temperatures ranging from about 20°C to about 600°C.

[0051] In contrast, according to some embodiments, during the entire period after the formation of silicon region 126P and before the formation of n-type silicon region 130N (as shown in Figures 6A and 6B), no etching process using metal halides is performed to etch the metal. This is because the selective formation of silicon region 126P is highly selective, therefore no metal layer is formed on the dielectric material and the upper source / drain region 62U.

[0052] Next, referring to Figures 8A and 8B, contact plugs 140A and 140B are formed, which are individually and collectively referred to as contact plug 140. The respective processes are illustrated as process 216 in the process flow 200 shown in Figure 24. Contact plugs 140A and 140B may be referred to as source / drain contact plugs, and contact plug 140A may be referred to as upper source / drain contact plug. According to some embodiments, contact plugs 140A and 140B comprise a metal, such as tungsten, molybdenum, ruthenium, iridium, or similar materials, or alloys thereof. According to some embodiments, contact plugs 140A and 140B have a single-layer structure, wherein the entire contact plugs 140A and 140B are formed of a homogeneous material such as those described above.

[0053] According to an alternative embodiment, the formation of contact plugs 140A and 140B may include forming a barrier layer, which may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. Next, a metallic material is deposited on and in contact with the barrier layer. The metallic material may include tungsten, cobalt, copper, nickel, molybdenum, ruthenium, iridium, or the like, or combinations thereof. [, , ]

[0054] Referring further to Figures 8A and 8B, after depositing the material used to form contact plugs 116, a planarization process, such as CMP or mechanical polishing, is performed to remove excess portions of one or more of the deposited material, leaving contact plugs 140A and 140B. Therefore, contact plugs 140A and 140B are surrounded by dielectric pads 124. The top surfaces of contact plugs 140A and 140B and dielectric pads 124 are coplanar, and may further be coplanar with the top surface of dielectric layer 120. [, , ]

[0055] According to some embodiments, as discussed above, metal layer 132 is removed in etching process 134 (Figures 6A and 6B). According to alternative embodiments, etching process 134 is not performed, and metal layer 132 is not removed at this stage. After forming the structures shown in Figures 7A and 7B and before forming contact plugs 140A and 140B, vacuum destruction can be performed, causing metal layer 132 to be oxidized. Therefore, the processes shown in Figures 20 through 23 can be performed to reduce the oxidized metal layer 132 back to metal. According to these embodiments, discrete metal islands 182A and 182B are schematically depicted to represent elemental metal layer 132 when metal layer 132 is not removed. Discrete metal islands 182A and 182B contain the same metal as the underlying n-type silicate layer 130N. [, , ]

[0056] Figures 9A and 9B further illustrate the formation of the back-side source / drain contact plug 160 (electrically connected to the lower source / drain region 62L) and the formation of the back-side redistribution lines. Individual processes are illustrated as process 218 in the process flow 200 shown in Figure 24. According to some embodiments, substrate 20 (Figures 8A and 8B) is removed, for example, by a CMP process and / or one or more etching processes. A dielectric substrate 156 (Figure 9A) may then be formed.

[0057] Semiconductor strips 20' (Figures 8A and 8B) are etched to form back-side openings through which the bottom of the lower source / drain region 62L is exposed. Silicon region 158 is formed below and in contact with the bottom surface of the lower source / drain region 62L. The material and formation process of silicon region 158 may be substantially the same as those of silicon regions 126P and / or 130N, and will not be repeated here. For example, silicon region 158 may include the same p-type silicon region as p-type silicon region 126P, and may or may not include the same n-type silicon region as n-type silicon region 130N.

[0058] A back-side contact plug 160 is formed to fill the remaining back-side contact opening. The back-side contact plug 160 contacts the silicate region 158. The back-side contact plug 160 may be formed of a homogeneous metallic material, which may include tungsten, cobalt, ruthenium, or the like. Alternatively, the formation of the back-side contact plug 160 may include forming a barrier layer and a homogeneous metallic material on the barrier layer, which may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. A planarization process, such as CMP or mechanical polishing, is then performed to remove excess material from the deposited material, leaving the back-side contact plug 160. [, , ]

[0059] Then, a dielectric layer 164 is deposited. A back-side redistribution line 162 (or conductive feature) is formed on the back side of the CFET and within the dielectric layer 164. The back-side redistribution line 162 is electrically connected to the contact plug 116 and to the lower source / drain region 62L.

[0060] Figures 10A and 10B through 13A and 13B illustrate cross-sectional views of intermediate stages in the formation of a CFET according to some embodiments of the present disclosure. According to these embodiments, an n-type silicide region is formed on and in contact with the lower source / drain region 62L and the upper source / drain region 62U. Unless otherwise specified, the materials, structures, and formation processes of the components in these embodiments (and the embodiments in Figures 14A and 14B through 19A and 19B) are substantially the same as those of the similar components indicated by similar reference numerals in the foregoing embodiments. Throughout the description, details regarding the materials, structures, and formation processes provided in the embodiments may be applied to any other embodiments where applicable.

[0061] The initial steps of these embodiments are substantially the same as those shown in Figures 1A and 1B through 4A and 4B. Next, as shown in Figures 10A and 10B, silicide regions 130N (including 130N1 and 130N2) are formed. The materials, structures, and formation processes of silicide regions 130N1 and 130N2 are substantially the same as those shown in Figures 6A and 6B, and will not be repeated here. The n-type silicide regions 130N1 and 130N2 are in solid contact with the underlying lower source / drain regions 62L and 62U, respectively.

[0062] During the formation of n-type silicide regions 130N1 and 130N2, due to the low selectivity of n-type metal deposition, metal layer 132 can be simultaneously formed on the exposed dielectric regions. According to some embodiments, metal layer 132 is removed by an etching process 134, which can be substantially the same as the etching process 134 discussed with reference to Figures 6A and 6B. Thus, metal layer 132 is removed, and the resulting structure is shown in Figures 11A and 11B.

[0063] According to an alternative embodiment, the metal layer 132 is not removed, and the subsequent vacuum destruction process can cause the metal layer 132 to oxidize, thus forming a metal oxide. The process shown in Figures 21 through 24 can then be performed to reduce the metal oxide back to an elemental metal.

[0064] Figures 12A and 12B illustrate the formation of contact plugs 140A and 140B. The formation process may be substantially the same as that shown in Figures 8A and 8B. Therefore, details will not be repeated here. According to some embodiments, when the processes shown in Figures 21 to 24 are performed, metal islands 182A and 182B containing elemental metal (which may be discrete islands or continuous metal layers) may be present at the edges and bottom of contact plugs 140A and 140B. The metal in metal islands 182A and 182B may be the same metal used to form silicate regions 130N1 and 130N2. According to an alternative embodiment, metal islands 182A and 182B will not exist when metal layer 132 is removed by etching process 134. [, , ]

[0065] Figures 13A and 13B illustrate the formation of a backside structure connecting the backside of wafer 2 to the lower source / drain region 62L. The materials, structure, and formation process are substantially the same as those discussed with reference to Figures 9A and 9B, and will not be repeated here. [, , ]

[0066] Figures 14A and 14B through 19A and 19B are cross-sectional views of intermediate stages in the formation of the CFET and silicide regions according to some embodiments of the present disclosure. According to these embodiments, an n-type silicide region and a titanium silicide (TiSi) layer are formed on the lower source / drain region 62L and the upper source / drain region 62U. [, , ]

[0067] Referring to Figures 14A and 14B, n-type silicide regions 130N1 and 130N2 are formed. The materials, structure, and formation process are substantially the same as those described with reference to Figures 6A and 6B, and will not be repeated here. The n-type silicide regions 130N1 and 130N2 are in solid contact with the underlying lower source / drain regions 62L and 62U, respectively.

[0068] During the formation of n-type silicon regions 130N1 and 130N2, a metal layer 132 is also formed on the exposed dielectric regions. According to some embodiments, the metal layer 132 is removed by an etching process 134, which may be substantially the same as described with reference to Figures 6A and 6B. Thus, the metal layer 132 is removed, and the resulting structure is shown in Figures 15A and 15B.

[0069] According to an alternative embodiment, metal layer 132 is not removed, and a subsequent vacuum destruction process can lead to the formation of a metal oxide. The process shown in Figures 20 through 23 can then be performed to reduce the metal oxide back to an elemental metal.

[0070] Referring to Figures 16A and 16B, silicate regions 170A and 170B are formed. Silicide regions 170A and 170B are located above and in solid contact with the underlying n-type silicate regions 130N1 and 130N2, respectively. Silicide regions 170A and 170B (individually and collectively referred to as silicate region 170) are medium work function silicate regions and have a higher work function than the underlying n-type silicate region 130. According to some embodiments, silicate regions 170A and 170B are formed of or contain titanium silicate, while other silicates such as VSi, ZnSi, NbSi, AlSi, and the like can be used. It has been found that stacked layers including n-type silica layers and medium work function silica layers can improve the performance of n-type transistors and p-type transistors.

[0071] The formation of silicate regions 170A and 170B can be substantially the same as that of n-type silicate regions 130N1 and 130N2. For example, the formation process may include conducting a precursor containing a corresponding metal (such as Ti), conducting Ar and / or H2, initiating a plasma, and heating the wafer 2. The metal in the precursor reacts with silicon and / or germanium in the lower source / drain region 62L and the upper source / drain region 62U to form silicate regions 170A and 170B. For example, Si and Ge diffuse through n-type silicate regions 130N1 and 130N2 to react with the metal.

[0072] According to some embodiments, when silicon regions 170A and 170B are formed, a metal layer 174 is formed on the surface of the exposed dielectric region. Depending on the metal in the precursor, the metal layer 174 contains an elemental metal (not a metal compound) corresponding to a metal such as Ti.

[0073] According to some embodiments, the metal layer 174 is removed by an etching process 172, which may be substantially the same as the etching process 134 discussed with reference to Figures 6A and 6B. For example, the aforementioned metal halide (such as TiCl4) can be used as the etching gas, wherein no plasma is initiated and no Ar and H2 are introduced. Thus, the metal layer 174 is removed, and the resulting structure is shown in Figures 17A and 17B.

[0074] According to an alternative embodiment, metal layer 174 is not removed, and a subsequent vacuum destruction process can lead to the formation of a metal oxide. The process shown in Figures 20 through 23 can then be performed to reduce the metal oxide back to an elemental metal.

[0075] Figures 18A and 18B illustrate the formation of contact plugs 140A and 140B. The formation process may be substantially the same as that shown in Figures 8A and 8B. Therefore, details will not be repeated here. According to some embodiments, when the processes shown in Figures 20 through 23 are performed, metal islands 182A and 182B containing elemental metal (which may be discrete islands or continuous metal layers) may be present at the edges and bottom of contact plugs 140A and 140B. The metal in metal islands 182A and 182B may be the same metal used to form silicate regions 130N1 and 130N2 and / or silicate regions 170A and 170B. According to an alternative embodiment, metal islands 182A and 182B will not exist when metal layers 132 and 174 are removed by etching processes 134 and 172. [, , ]

[0076] Figures 19A and 19B illustrate the formation of a backside structure connecting the backside of wafer 2 to the lower source / drain region 62L and contact plug 116. The materials, structure, and formation process are substantially the same as those discussed with reference to Figures 9A and 9B, and will not be repeated here. [, , ]

[0077] Figures 20 through 23 illustrate some process steps that are performed as part of the processes shown in Figures 1A and 1B through 9A and 9B, Figures 10A and 10B through 13A and 13B, or Figures 14A and 14B through 19A and 19B. The processes shown in Figures 20 through 23 can be inserted after the formation of the silicate region and before the formation of contact plugs 140A and 140B. [, , ]

[0078] Referring to Figure 20, a silicate region 176 is formed. The structure shown in Figure 20 may represent the structure shown in Figures 6A and 6B (when metal layer 132 is not removed), or Figures 7A and 7B, or Figures 10A and 10B (when metal layer 132 is not removed), or Figures 11A and 11B, or Figures 16A and 16B (when metal layers 132 and / or 174 are not removed), or Figures 17A and 17B. Therefore, the silicate region 176 in Figure 20 may represent the corresponding silicate region in these figures.

[0079] Next, as shown in Figure 21, a vacuum destruction process is performed. The vacuum destruction process causes the exposed surface portion of the silicate region 176 to be oxidized, forming metal oxide regions 178 (including metal oxide regions 178A and 178B). Metal oxide region 178A is formed on the surface of the dielectric region. Metal oxide region 178B is formed on the surface of the silicate region 176. Metal oxide regions 178B, and possibly metal oxide regions 178A, may include metals and silicon / germanium from the silicate region 176. The corresponding metal oxides may be represented as M-Si-OX, where M represents a metal, Si represents silicon and / or Ge, and OX represents an oxide formed by M and Si.

[0080] According to some embodiments, metal oxide region 176A may include M-Si-OX, which can be formed on dielectric pad 124 by reacting the metal with oxygen in the open air and reacting with SiN when dielectric pad 124 contains SiN. Otherwise, when dielectric pad 124 contains silicon oxide, the resulting metal oxide region 176A contains metal oxide instead of M-Si-OX. Therefore, metal oxide region 178A formed on the top surface of dielectric pad 124 and dielectric region may contain Mi-Si-OX or metal oxide. Metal oxide region 178B, as the oxidized portion of silicate region 176, may contain Mi-Si-OX. It should be understood that metal oxide regions 178A and 178B may form discrete islands separated from each other or may form a continuous layer.

[0081] Figure 21 further illustrates reduction process 180, also known as pre-cleaning process. Reduction process 180 is performed to reduce metal oxide region 178 back to metal region 182 (including metal regions 182A and 182B), which contains elemental metal (rather than metal compounds). The resulting structure is shown in Figure 22.

[0082] The elemental metal is the same as the metal in the underlying silica region. According to some embodiments, the reduction process 180 is performed by an impregnation process using a reducing gas comprising one or more metal halides. Other reduction materials may be selected from the same group of candidate materials used in the etching process 134 (Figures 6A and 6B). According to some embodiments, the reducing gas may contain WCl5, TiCl4, and / or the like, and plasma is not initiated in the reduction process 180. Furthermore, process gases such as H2, Ar, or the like are not applied. RF power may also not be applied.

[0083] It should be understood that the same process gases can be used for etching process 134 (or 172) and reduction process 180. Whether the result is etching or reduction depends on the gas and process conditions. For example, TiCl4 is more likely to reduce TiOx back to titanium and is also more likely to etch titanium. Elemental metals reduced from metal oxides can also be etched upon further exposure to the process gas. Therefore, process conditions such as a particular process gas, a lower process gas flow rate, a shorter reaction time, and similar factors can result in reduction process 180, while other selected process gases, higher process gas flow rates, longer reaction times, and similar factors can result in etching processes 134 and 172. [, , ]

[0084] As shown in Figure 22, according to some embodiments, elemental metal regions 182 (including elemental metal islands 182A and / or 182B) are formed, which include the same metal as the silicate regions, the formation of which results in a metal layer. Furthermore, according to some embodiments using WCl5, in addition to the metals in metal layers 132 and 174, elemental tungsten may also remain as part of the elemental metal regions 182.

[0085] Figure 23 illustrates the formation of contact plugs 140A and 140B, which are also shown in Figures 9A and 9B, 13A and 13B, or 19A and 19B. The elemental metal region 182 can act as a nucleation layer for better deposition in the formation of contact plugs 140A and 140B. Therefore, the likelihood of voids forming in contact plugs 140A and 140B is lower. By converting the metal oxide into elemental metal regions, the contact resistance between the resulting contact plug and the silicate region is also reduced.

[0086] Some embodiments disclosed herein have several advantageous features. Contact plugs are easier to form by removing the metal layer formed in the contact openings, as the space occupied by the contact openings is freed up for contact plug formation. The undesirable resistance increases due to the reduction of the metal oxides formed by vacuum disruption, and the contact plug formation process is easier because the elemental metal is used as the nucleation layer. [, , ]

[0087] According to some embodiments of the present disclosure, a method includes forming a source / drain region; forming a contact etch-stop layer over the source / drain region; forming an interlayer dielectric over the contact etch-stop layer; performing an etching process to form a contact opening in the interlayer dielectric and the contact etch-stop layer, such that a plurality of dielectric regions are exposed to the contact opening, wherein the source / drain region is exposed to the contact opening; performing a first silicide formation process to form a first silicide region on the surface of the source / drain region; performing a first etching process to remove metal deposited on the dielectric region; and forming a contact plug in the contact opening.

[0088] In some embodiments, the first etching process is performed in a plasma-free and hydrogen-free (H2-free) environment. In some embodiments, the source / drain regions comprise germanium, and the method further includes, prior to the first silicide formation process, performing a selective deposition process to form a second silicide region located above and in contact with the source / drain regions, wherein the first silicide region is located above and in contact with the second silicide region. In some embodiments, the first silicide region is an n-type silicide region, and the second silicide region is a p-type silicide region.

[0089] In some embodiments, the first etching process is performed using a first metal halide as the etching gas, and the first silicate formation process is performed using a second metal halide as a precursor. In some embodiments, the first metal halide and the second metal halide comprise the same metal. In some embodiments, the method further includes, after the first silicate formation process, performing a second silicate formation process to form a second silicate region located above and in contact with the first silicate region; and after the second silicate formation process, performing a second etching process to remove additional metal deposited on the dielectric region. In some embodiments, the second silicate formation process is performed after the first etching process.

[0090] In some embodiments, the method further includes performing vacuum destruction to expose the first silicide region to the open air after forming the first silicide region, wherein a metal oxide is formed in the contact opening; and conducting a metal halide gas after vacuum destruction to reduce the metal oxide back to an elemental metal. In some embodiments, the first etching process is further performed using a metal halide gas. In some embodiments, the method further includes forming a dielectric pad in the contact opening prior to the first silicide formation process.

[0091] According to some embodiments of this disclosure, a method includes forming a lower source / drain region; forming a first contact etch-stop layer over the lower source / drain region; forming a first interlayer dielectric over the first contact etch-stop layer; forming an upper source / drain region over the first interlayer dielectric, wherein the upper source / drain region overlaps with the lower source / drain region; forming a second contact etch-stop layer over the upper source / drain region; forming a second interlayer dielectric over the second contact etch-stop layer; and performing a first etching process to etch the first contact etch-stop layer, the first interlayer dielectric, the second contact etch-stop layer, and the second interlayer dielectric. A contact opening is formed in the electrical field; a first silicide region is selectively formed above the lower source / drain region, wherein the top surface of the upper source / drain region is exposed when the selective formation of the first silicide region is completed; a second silicide region is formed, the second silicide region comprising a first portion located above and in contact with the first silicide region and a second portion located above and in contact with the upper source / drain region; a second etching process is performed, wherein the metal layer located in the contact opening and deposited by forming the second silicide region is removed; and a contact plug is formed in contact with the first and second portions of the second silicide region.

[0092] In some embodiments, at the start of forming the second silicide region, the dielectric region facing the contact opening is exposed. In some embodiments, the second silicide region and the metal layer are formed simultaneously. In some embodiments, the second silicide region and the second etching process are performed using a halide gas. In some embodiments, no etching process is performed to remove additional metal from the contact opening during the entire period after the formation of the first silicide region and before the formation of the second silicide region.

[0093] According to some embodiments of this disclosure, a method includes forming a lower source / drain region; forming a first contact etch-stop layer over the lower source / drain region; forming a first interlayer dielectric over the first contact etch-stop layer; forming an upper source / drain region over the first interlayer dielectric, wherein the upper source / drain region overlaps with the lower source / drain region; forming a second contact etch-stop layer over the upper source / drain region; forming a second interlayer dielectric over the second contact etch-stop layer; forming a first silicide region over the lower source / drain region, wherein the first silicide region includes a p-type silicide region and a first portion of an n-type silicide region located above the p-type silicide region; forming a second silicide region over the upper source / drain region, wherein the second silicide region includes a second portion of the n-type silicide region; and forming a contact plug connecting the first silicide region to the second silicide region.

[0094] In some embodiments, a second portion of the n-type silicide region is located between and in solid contact with the upper source / drain region and the contact plug. In some embodiments, the contact plug comprises a homogeneous material in contact with the first and second silicide regions. In some embodiments, the p-type silicide region is in solid contact with the lower source / drain region.

[0095] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of some embodiments disclosed herein. Those skilled in the art should understand that some embodiments of this disclosure can be used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments introduced in some embodiments of this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of some embodiments of this disclosure, and that various changes, substitutions, and modifications can be made to some embodiments of this disclosure without departing from the spirit and scope of these embodiments.

[0096] 1B-1B, 3A-3A, 3B-3B: Cross-section 2: Wafer 10:CFET 10L: Lower nanostructure FET 10U: Top nanostructure FET 20:Substrate 20': Semiconductor strip 26: Channel Region / Semiconductor Nanostructure 26'L: Lower semiconductor nanostructure 26'M: Dummy Semiconductor Layer 26'U: Upper semiconductor nanostructure 32: Isolation Area 44: Gate spacer 45: Fin spacers 54: Internal spacers 56: Dielectric isolation layer 62: Source / Drain Region 62L: Lower source / drain region 62U: Upper source / drain region 66: First CESL 68: First ILD 70: Second CESL 72: Second ILD 78: Gate Dielectric 80: Gate electrode 80L: Lower gate electrode 80U: Upper gate electrode 90: Gate Stacking 90L: Lower gate stack 90U: Upper gate stack 114, 124: Dielectric pads 116, 140, 140A, 140B: Contact plugs 118: Etching Termination Layer 120, 164: Dielectric layer 121, 122: Opening 126P: Silicon region 130, 130N, 130N1, 130N2: Silicate region 132, 174: Metallic layer 134, 172: Etching process 156: Dielectric substrate 158, 170, 170A, 170B, 176: Silicate regions 160: Contact plug 162: Redistribution line on the dorsal side 178, 178A, 178B: Metal oxide regions 180: Reduction Process 182, 182A, 182B: Metal areas / metal islands 200: Manufacturing Process 202, 204, 206, 208, 210, 212, 214, 216, 218: Process

[0097] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method of forming a transistor and a silicon region, comprising: forming a source / drain region; forming a contact etch-stop layer over the source / drain region; forming an interlayer dielectric over the contact etch-stop layer; performing an etching process to form a contact opening in the interlayer dielectric and the contact etch-stop layer, such that a plurality of dielectric regions are exposed to the contact opening, wherein the source / drain region is exposed to the contact opening; performing a first silicon formation process to form a first silicon region on a surface of the source / drain region; performing a first etching process to remove a metal deposited on the dielectric regions; and forming a contact plug in the contact opening.

2. The method as described in claim 1, wherein the first etching process is performed in a plasma-free and hydrogen-free environment.

3. The method of claim 1, wherein the source / drain region comprises germanium, and the method further comprises: performing a selective deposition process prior to the first silicide formation process to form a second silicide region located above and in contact with the source / drain region, wherein the first silicide region is located above and in contact with the second silicide region.

4. The method as described in claim 3, wherein the first silicate region is an n-type silicate region and the second silicate region is a p-type silicate region.

5. The method as claimed in claim 1, wherein the first etching process is performed using a first metal halide as an etching gas, and the first silicate formation process is performed using a second metal halide as a precursor.

6. The method as described in claim 5, wherein the first metal halide and the second metal halide comprise the same metal.

7. The method as described in claim 1, further comprising: performing a second silicon formation process after the first silicon formation process to form a second silicon region located above and in contact with the first silicon region; and performing a second etching process after the second silicon formation process to remove an additional metal deposited on the dielectric regions.

8. A method of forming a transistor and a silicon region, comprising: forming a lower source / drain region; forming a first contact etch-stop layer above the lower source / drain region; forming a first interlayer dielectric above the first contact etch-stop layer; forming an upper source / drain region above the first interlayer dielectric, wherein the upper source / drain region overlaps with the lower source / drain region; forming a second contact etch-stop layer above the upper source / drain region; forming a second interlayer dielectric above the second contact etch-stop layer; performing a first etching process to form a contact opening in the first contact etch-stop layer, the first interlayer dielectric, the second contact etch-stop layer, and the second interlayer dielectric; selectively forming a first silicon region above the lower source / drain region, wherein a top surface of the upper source / drain region is exposed when the selective formation of the first silicon region is completed; A second silicide region is formed, the second silicide region comprising a first portion located above and in contact with the first silicide region and a second portion located above and in contact with the upper source / drain region; a second etching process is performed, wherein a metal layer located in the contact opening and deposited by forming the second silicide region is removed; and a contact plug is formed in contact with the first portion and the second portion of the second silicide region.

9. The method as described in claim 8, wherein at the beginning of the formation of the second siliconized region, a plurality of dielectric regions facing the contact opening are exposed.

10. A method of forming a transistor and a silicon region, comprising: forming a lower source / drain region; forming a first contact etch-stop layer above the lower source / drain region; forming a first interlayer dielectric above the first contact etch-stop layer; forming an upper source / drain region above the first interlayer dielectric, wherein the upper source / drain region overlaps with the lower source / drain region; forming a second contact etch-stop layer above the upper source / drain region; forming a second interlayer dielectric above the second contact etch-stop layer; and forming a first silicon region above the lower source / drain region, wherein the first silicon region includes a p-type silicon region and a first portion of an n-type silicon region located above the p-type silicon region; A second silicate region is formed above the upper source / drain region, wherein the second silicate region includes a second portion of the n-type silicate region; and a contact plug is formed to connect the first silicate region to the second silicate region.

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