Built-in self-trim device and system and operating method thereof

Abstract

This document discloses a system, an apparatus, and a method of operating the system and apparatus. In one embodiment, a system includes memory circuitry, a plurality of bias generator circuits, and a built-in self-adjusting circuit, each bias generator circuit corresponding to an individual input of the memory circuitry. The built-in self-adjusting circuitry receives a feedback signal from a first bias generator circuit among the plurality of bias generator circuits. The built-in self-adjusting circuitry generates a fine-tuning code for the first bias generator circuitry based on the feedback signal and a voltage reference, causing the first bias generator circuitry to generate an output voltage for an individual input of the memory array.

Claims

1. A system with a built-in self-adjusting device, comprising: a memory circuit; a plurality of bias generator circuits, each of the bias generator circuits corresponding to an individual input of the memory circuit; and a built-in self-adjusting circuit for: receiving a feedback signal from a first bias generator circuit of the bias generator circuits; generating a trimming code for the first bias generator circuit based on the feedback signal and a voltage reference, causing the first bias generator circuit to generate an output voltage for the individual input of the memory circuit; and iteratively generating a plurality of trimming codes for the first bias generator circuit using a search operation, wherein the search operation includes a binary search operation.

2. The system as claimed in claim 1, further comprising a voltage reference generator circuit for generating a plurality of voltage references respectively corresponding to the bias generator circuits.

3. The system as claimed in claim 1, wherein the built-in self-adjusting circuitry is further configured to: perform a self-calibration process before generating the adjustment code; and generate a write signal to store the adjustment code in an adjustment register of the first bias generator circuit.

4. The system as described in claim 1, further comprising a one-time programmable memory circuit, wherein the built-in self-adjusting circuit is further configured to provide the adjustment code for storage in the one-time programmable memory circuit.

5. The system as claimed in claim 1, wherein the first bias generator circuit includes a feedback circuit for generating the feedback signal based on the output voltage of the first bias generator circuit.

6. The system as claimed in claim 1, wherein the first bias generator circuit includes a switch for providing the output voltage of the first bias generator circuit as the feedback signal.

7. The system as described in claim 1, wherein the built-in self-adjusting circuitry is further configured to perform a self-calibration process before generating the adjustment code.

8. The system as claimed in claim 1, wherein the built-in self-tuning circuitry and the memory circuitry are defined on the same semiconductor die.

9. A built-in self-adjusting device comprising: a comparator circuit; a first search circuit coupled to the comparator circuit; and a second search circuit configured to: generate a trim code for a bias generator circuit based on an output of the comparator circuit, wherein the output is generated based on a feedback signal from the bias generator circuit; and iteratively generate a plurality of trim codes for the bias generator circuit using a search operation, wherein the search operation includes a binary search operation.

10. A method of operating a built-in self-tuning device, comprising the steps of: calibrating a built-in self-tuning circuit of a memory device using a first search operation, wherein the first search operation includes a binary search operation; determining a tuning code for a bias generator circuit of the memory device using the built-in self-tuning circuit and a second search operation; and generating a voltage for at least one control input in a memory array of the memory device using the bias generator circuit.

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