Semiconductor device and method for fabricating the same

The formation of a trench within shallow trench isolations between epitaxial layers in semiconductor devices addresses issues with polysilicon gates, improving device performance by maintaining epitaxial layers and optimizing gate structures with metal gates.

TWI934595BActive Publication Date: 2026-08-01UNITED MICROELECTRONICS CORP
2 Cites 0 Cited by

Patent Information

Application Number
TW114117124
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-05-07
Publication Date
2026-08-01
Estimated Expiration
2045-05-06

AI Technical Summary

Technical Problem

Conventional semiconductor devices face issues with reduced device performance due to boron penetration and depletion effects in polysilicon gates, leading to increased equivalent gate dielectric layer thickness and decreased gate capacitance, particularly in I/O and core regions where epitaxial layers are lost during wet cleaning, resulting in voids.

Method used

A method involving the formation of a trench within a shallow trench isolation between epitaxial layers, using a substrate with defined transistor regions, and replacing polysilicon gates with metal gates, including high dielectric constant dielectric layers and work function metals to enhance electrical performance.

Benefits of technology

Improves electrical performance by maintaining epitaxial layers and optimizing gate structures, reducing void formation, and enhancing device drive capability.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

This invention discloses a method for fabricating a semiconductor device, which mainly involves first providing a substrate including a first transistor region and a second transistor region, then forming a shallow trench isolation around the first transistor region and the second transistor region, forming a gate structure extending from the first transistor region to the second transistor region, forming a first epitaxial layer next to the gate structure of the first transistor region and a second epitaxial layer next to the gate structure of the second transistor region, and finally forming a trench within the shallow trench isolation between the first epitaxial layer and the second epitaxial layer.
Need to check novelty before this filing date? Find Prior Art