Memory cell, memory device and method of manufacturing the same

Abstract

A memory device includes a plurality of memory cells, word lines, a plurality of bit lines, and a plurality of source lines. Each memory cell includes an once-programmable (OTP) element and a plurality of select transistors. Word lines are connected to the gate terminals of the select transistors of the memory cell. Bit lines are connected in parallel between a first node and a first OTP element terminal of the OTP element of the memory cell. Source lines are connected in parallel and connect a second source / drain terminal of the select transistor of the memory cell to a second node. A method for manufacturing a memory device is also disclosed.

Description

Technical Field

[0001] none Prior Technology

[0002] Memory devices are responsible for storing and retrieving data. They come in various forms and can be programmable or non-programmable. Programmable memory devices, such as random access memory (RAM), allow data to be written and rewritten multiple times, making them suitable for applications that require frequent updates. On the other hand, non-programmable memory devices, such as one-time programmable (OTP) memory, can only be written to once. These devices can be used in applications where data needs to be kept secure and immutable. Regardless of their programmability, memory devices facilitate the reading of the data stored within them, enabling electronic systems to access and utilize information as needed. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The nature of this disclosure is best understood when read in conjunction with the accompanying drawings, based on the following detailed description: Figure 1 is a schematic circuit diagram illustrating various embodiments of a memory device according to this disclosure; Figure 2A is a schematic circuit diagram illustrating exemplary memory cells according to various embodiments of this disclosure; Figure 2B is a schematic timing diagram illustrating the exemplary relationships between word line signals, bit line signals, and source line signals according to various embodiments of this disclosure; Figure 3 is a schematic circuit diagram illustrating another exemplary memory unit according to various embodiments of this disclosure; Figure 4 is a schematic layout diagram illustrating exemplary wires of a memory cell according to various embodiments of this disclosure; Figure 5 is a schematic layout diagram illustrating further exemplary wires according to various embodiments of this disclosure; Figure 6A is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present disclosure; Figure 6B is a schematic timing diagram illustrating the exemplary relationships between word line signals, bit line signals, and source line signals according to various embodiments of this disclosure; Figure 7 is a schematic layout diagram illustrating further exemplary wires according to various embodiments of the present disclosure; Figure 8 is a schematic layout diagram illustrating further exemplary wires according to various embodiments of the present disclosure; Figure 9 is a schematic layout diagram illustrating further exemplary wires according to various embodiments of the present disclosure; Figure 10 is a schematic layout diagram illustrating further exemplary wires according to various embodiments of the present disclosure; Figure 11 is a schematic layout diagram illustrating further exemplary wires according to various embodiments of the present disclosure; Figure 12 is a schematic layout diagram illustrating further exemplary wires of a memory cell according to various embodiments of the present disclosure; Figure 13 is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present disclosure; Figure 14 is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present disclosure; Figure 15 is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present disclosure; Figure 16 is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present disclosure; Figure 17 is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present disclosure; Figure 18 is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present disclosure; Figure 19 is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present disclosure; Figure 20 is a flowchart illustrating an exemplary method of manufacturing a memory device according to various embodiments of the present disclosure; and Figure 21 is a schematic cross-sectional view illustrating another exemplary memory device according to various embodiments of the present disclosure. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "below," "lower," "above," "on," "top," "bottom," and the like are used herein to describe the relationship between one element or feature and another element(s) shown in the diagrams. In addition to the orientations depicted in the diagrams, spatial relative terms are also intended to cover different orientations of the structure during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive symbols used herein will be interpreted accordingly.

[0007] Memory devices comprise, for example, a plurality of memory cells arranged in an array of columns and rows, facilitating data storage and retrieval. Memory devices can be programmable or non-programmable. Programmable memory devices, such as random access memory (RAM) devices, allow data to be written and rewritten multiple times, making them suitable for applications requiring frequent updates, such as those in RAM devices. Non-programmable memory devices, such as once-programmable (OTP) memory devices, can only be written to once, ensuring data permanence and security, preventing alteration. They are useful in applications where data needs to be kept secure and immutable.

[0008] However, OTP memory devices may sometimes fail to program. For example, during programming, a programming voltage is applied across the memory cells of the OTP memory device via bit lines. The bit lines may have higher than expected trace resistance (e.g., via a manufacturing defect), which limits the current flow required by the programming memory cells, thus causing programming failure.

[0009] In some instances described herein, the systems and methods include memory devices comprising memory cells connected to two or more bit lines. To reduce overall trace resistance, the bit lines are connected in parallel. This parallel configuration increases the likelihood of successfully programming the memory cells.

[0010] Figure 1 is a schematic circuit diagram illustrating an exemplary memory device according to various embodiments of the present disclosure. An exemplary memory device 100, such as an OTP memory device, includes a plurality of memory cells 110, a plurality of word lines (WL0~WLn), and a plurality of bit lines (BL0~BLn). An OTP memory device is a memory device that permanently stores data bits, which cannot be changed once written. For example, each memory cell 110 includes an OTP element. In this exemplary embodiment, the OTP element includes an antifuse that is initially non-conductive (e.g., antifuse 210 in Figure 2A), representing logic '0' (or '1'). During programming, the antifuse becomes conductive, for example, by applying a high voltage or current, representing a programmed bit, for example, logic '1' (or '0').

[0011] Memory cells 110 can be configured in an array of columns and rows. Memory cells 110 in each column are connected to their respective word lines (WL0~WLn). Similarly, memory cells 110 in each row are connected to their respective bit lines (BL0~BLn). For example, each bit line (BL0~BLn) is connected between a voltage node (e.g., the VDD node in Figure 3) and the memory cells 110 in the respective row. In this exemplary embodiment, the memory device 100 further includes a plurality of source lines (SL0~SLn), each source line connecting the memory cells 110 in the row to a ground (or VSS) node.

[0012] Memory cell 110 stores a single bit, logic '0' or '1', and undergoes a permanent and irreversible change during writing or programming. For example, this change occurs when a high voltage, i.e., a programming voltage, is applied to the corresponding bit line (BL0~BLn), thereby ensuring that memory cell 110 cannot be reprogrammed (i.e., the bit stored therein cannot be overwritten). Word lines (WL0~WLn) enable access to the corresponding memory cell 110 by activating them during read and write operations.

[0013] In some embodiments, memory cells 110 in each row are connected between two or more bit lines (e.g., two or more bit lines (BL[0])) connected in parallel and two or more source lines (e.g., two or more source lines (SL[0])) connected in parallel. This parallel configuration reduces the total trace resistance of the bit lines (BL[0]) and the total trace resistance of the source lines (SL[0]), thereby minimizing trace resistance that impedes current flow. Lower resistance in the traces helps ensure that sufficient programming voltage or current can be reliably delivered to the memory cells 110, thereby increasing the likelihood of successfully programming the antifuse to its conductive state.

[0014] To read memory cell 110, a word line is activated by applying a high word line (WL) signal to a word line (e.g., the word line corresponding to the word line to be listed (WL[0])). A bit line, such as bit line BL[0], is then used to detect the state of memory cell 110. If the antifuse is programmed, it will exhibit specific electrical characteristics, such as decreased resistance or increased current flow, indicating that a conductive path has been established. This characteristic corresponds to a programmed logic state, representing logic '1' (or '0'). The increase in current flow or decrease in resistance is due to the formation of a permanent and non-reprogrammable conductive path across the antifuse. Conversely, if the antifuse remains unprogrammed (i.e., complete), it remains in a high resistance state, and memory cell 110 exhibits a different electrical signal corresponding to logic '0' (or '1'). The absence of a conductive path results in higher resistance or lower current flow. Programmed data, reflecting the state of memory cell 110, is read by reading the voltage or current level on the bit line (BL[0]). By further processing these voltage or current levels, such as amplification, the bits stored in memory cell 110 can be accurately retrieved, thereby determining whether memory cell 110 holds logic '1' or '0'.

[0015] In an alternative embodiment, the OTP element includes a fuse. Unlike an antifuse, which creates a conductive path during programming, the fuse is initially conductive and becomes non-conductive when "blown" or programmed.

[0016] Figure 2A is a schematic circuit diagram illustrating an exemplary memory cell 200 according to various embodiments of the present disclosure. As illustrated in Figure 2A, the exemplary memory cell 200, such as memory cell 110, takes the form of a four-transistor, one-resistor (4T1R) memory cell and includes one OTP element 210 and four select transistors 220 (for simplicity, only one of the select transistors is labeled in Figure 2A). The OTP element 210 has a first OTP element terminal connected to two or more bit lines (BLs). For example, each bit line (BL) is connected to a voltage node, such as the VDD node in Figure 3. The memory cell 200 further includes interconnects 230 that connect the bit lines (BLs) in parallel. The first OTP element terminal of the OTP element 210 is connected to the interconnects 230.

[0017] In this exemplary embodiment, the OTP element 210 includes an antifuse in the form of a magnetic tunnel junction (MTJ), a dielectric breakdown antifuse, a phase change material-based antifuse, a resistive switching element, any other type of antifuse technology that transitions from a high resistance state to a low resistance state during programming or writing, or a combination thereof.

[0018] In this exemplary embodiment, the selected transistor 220 is a field-effect transistor (FET) and has a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminals are interconnected and connected to a word line (WL). The first source / drain terminals of the selected transistor 220 are interconnected and connected to a second OTP element terminal of the OTP element 210. For example, the memory cell 200 further includes an interconnect 240 connecting the first source / drain terminals to each other. The second OTP element terminal of the OTP element 210 is connected to the interconnect 240. The second source / drain terminals of the selected transistor 220 are interconnected and connected to two or more source lines (SL). For example, each source line (SL) is connected to a ground (or VSS) node. The memory cell 200 further includes an interconnect 250 connecting the source lines (SL) in parallel. The second source / drain terminals of the selected transistor 220 are interconnected and connected to the interconnect 250.

[0019] In some embodiments, each selected transistor 220 is an n-type metal-oxide-semiconductor (MOSFET). In other embodiments, at least one of the selected transistors 220 is a p-type MOSFET. In alternative embodiments, the memory cell 200 includes a planar transistor, a gate-all-around (GAA) transistor, a back-end MOSFET, any suitable transistor, or a combination thereof.

[0020] As described above, memory cell 200 uses a combination of OTP element 210 and select transistor 220 to permanently store bits therein by changing the state of OTP element 210. For example, before programming, OTP element 210 is intact, that is, there is no conductive path through it, resulting in high resistance. In this state, OTP element 210 behaves like an open circuit, thereby preventing a large amount of current from flowing. The absence of a conductive path indicates that logic '0' (or '1') is stored in memory cell 200. During write or programming operations, select transistor 220 is activated by a high (or low) word line (WL) signal ('1') at the word line (WL), thereby enabling access to memory cell 200. For example, Figure 2B is a schematic timing diagram illustrating the exemplary relationship between word line (WL) signals, bit line (BL) signals, and source line (SL) signals according to various embodiments of this disclosure. Memory cell 200 is then connected between bit line (BL) and source line (SL). A programming voltage, i.e., a higher voltage, is then applied between bit line (BL), memory cell 200, and source line (SL), causing current to flow. This current can permanently alter the structure of OTP element 210, for example, creating a conductive path and reducing its resistance to a low (or programmed) state. This programmed state indicates that logic '1' (or '0') is stored in memory cell 200. Because the bit line (BL) is connected in parallel, the total trace resistance of the bit line (BL) is reduced. Additionally, because the source line (SL) is connected in parallel, the total trace resistance of the source line (SL) is also reduced. This reduction in trace resistance improves the efficiency of current flow, thereby increasing the likelihood of successfully programming memory cell 200.

[0021] During a read operation, a high (or low) word line (WL) signal at the word line (WL) activates the select transistor 220 and connects the memory cell 200 between the bit line (BL) and the source line (SL). Instead of a higher programming voltage used for programming, a much lower read voltage is applied between the bit line (BL), the memory cell 200, and the source line (SL). If the OTP element 210 is programmed (i.e., it is in a low-resistance state), current flows through it, and the sense amplifier connected to the memory cell 200 interprets the bits stored in the memory cell 200 as logic '1' (or '0'). Otherwise, that is, the OTP element 210 is non-conductive, and there is essentially no current or no current flowing through it. In this state, the sense amplifier interprets the bits stored in the memory cell 200 as logic '0' (or '1').

[0022] In an alternative embodiment, the source line (SL) is connected to the VDD node, while the bit line (BL) is connected to the ground (or VSS) node. In some embodiments, the memory cell 200 is connected between a plurality of bit lines (BL) connected in parallel and a single source line (SL). In other embodiments, the memory cell 200 is connected between a single bit line (BL) and a plurality of source lines (SL) connected in parallel.

[0023] In some embodiments, memory cell 200 further includes one or more floating OTP elements 260-280. Each OTP element 260-280 has a first OTP element terminal connected to a bit line (BL) and a second floating OTP element terminal (i.e., the second OTP element terminal is not electrically connected to memory cell 200).

[0024] Although memory cell 200 is illustrated as a 4T1R memory cell, it should be understood that, upon reading this disclosure, memory cell 200 may include any number of OTP elements and selected transistors, such as 1T1R, 2T2R, one transistor, one capacitor (1T1C), one transistor, one magnetic tunnel junction (1T1MTJ), and the like.

[0025] In an alternative embodiment, the OTP element 210 includes a fuse. Unlike an antifuse, which creates a conductive path during programming, the fuse is initially conductive and becomes non-conductive when "blown" or programmed.

[0026] Figure 3 is a schematic circuit diagram illustrating another exemplary memory cell 300 according to various embodiments of the present disclosure. As illustrated in Figure 3, the exemplary memory cell 300, such as memory cell 200, includes an OTP element 310 and a select transistor 320. The OTP element 310 has a first OTP element terminal connected to two or more bit lines (BLs). For example, each bit line (BL) is connected to a voltage (VDD) node. The memory cell 300 further includes an interconnect 330 that connects the bit lines (BLs) in parallel. The first OTP element terminal of the OTP element 310 is connected to the interconnect 330. The select transistor 320 has a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminal is connected to a word line (WL). The first source / drain terminal of the select transistor 320 is connected to a second OTP element terminal of the OTP element 310. The second source / drain terminal of the select transistor 320 is connected to two or more source lines (SLs). For example, each source line (SL) is connected to a ground (or VSS) node. Memory cell 300 further includes interconnects 350 that connect the source lines (SL) in parallel. A second source / drain terminal of select transistor 320 is connected to interconnect 350. In this exemplary embodiment, OTP element 310 is an antifuse.

[0027] Based on the above description, and further referring to Figure 2B, during a write or program operation, the select transistor 320 is activated by a high (or low) word line (WL) signal at the word line (WL), enabling access to the memory cell 300. At this time, the memory cell 300 is connected between the bit line (BL) and the source line (SL). A program voltage is applied between the bit line (BL), the memory cell 300, and the source line (SL), causing current to flow. This current can permanently alter the structure of the OTP element 310, for example, creating a conductive path and reducing its resistance to a low (or programmed) state. This programmed state indicates that logic '1' (or '0') is stored in the memory cell 300. Because the bit lines (BL) are connected in parallel, the total trace resistance of the bit lines (BL), for example, the equivalent trace resistances 360 and 370, is reduced. Furthermore, since the source lines (SL) are connected in parallel, the total trace resistance of the source lines (SL), such as the equivalent trace resistances 380 and 390, is also reduced. This reduction in trace resistance improves the efficiency of current flow, thereby increasing the likelihood of successfully running the program memory unit 300.

[0028] Figure 4 is a schematic layout diagram illustrating exemplary wiring of a memory cell (e.g., memory cell 200) according to various embodiments of the present disclosure. As illustrated in Figure 4, the exemplary layout 400 includes two or more bit lines (BLs), word lines (WLs), and interconnect lines (ILs), as well as two or more vias (VIAs). The bit lines (BLs) are spaced apart along a first direction (x) and each extends in a second direction (y) transverse to the first direction (x). In some embodiments, the bit lines (BLs) are formed in the same metal layer, for example, a metal layer (M6).

[0029] The word lines (WL) and interconnects (IL) each extend in a first direction (x) and are spaced apart in a second direction (y). In some embodiments, the word lines (WL) and interconnects (IL) are formed in the same one or more metal layers, for example, metal layers (M1 and / or M7).

[0030] Each via (VIA) extends laterally in a third direction (z) beyond the first and second directions (x, y), and connects one of the bit lines (BL) to an interconnect (IL). Since the bit lines (BL) are connected to the same interconnect (IL), they are connected in parallel. This parallel connection reduces the total trace resistance of the bit lines (BL), thereby increasing the likelihood of successfully running the program memory unit 200.

[0031] In some embodiments, layout 400 further includes two or more source lines connected in parallel (e.g., SL in Figure 2A). The source lines (SL) are constructed similarly to those described above in conjunction with bit lines (BL). Therefore, for the sake of brevity, a detailed description of the source lines (SL) is omitted herein.

[0032] In this exemplary embodiment, bit lines (BL), source lines (SL), word lines (WL), interconnects (IL), and vias (VIA) are formed of conductive materials such as copper (Cu), aluminum (Al), other suitable metals, or alloys thereof, and are deposited over memory cell 200 to establish electrical connections.

[0033] In some embodiments, bit lines (BL) (and / or source lines SL) have substantially the same width (w) as word lines (WL). In some such embodiments, interconnects (IL) have substantially the same width (w) as word lines (WL). In other embodiments, bit lines (BL) (and / or source lines SL) may have a different width than word lines (WL). For example, Figure 5 is a schematic layout diagram illustrating further exemplary conductors of a memory cell (e.g., memory cell 200) according to various embodiments of this disclosure. As illustrated in Figure 5, bit lines (BL) (and / or source lines SL) have a width (w1) greater than the width (w2) of word lines (WL). This configuration further reduces the total trace resistance of bit lines (BL) and / or the total trace resistance of source lines (SL).

[0034] Figure 6A is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present disclosure. As illustrated in Figure 6A, an exemplary memory device 600, such as memory device 100, includes a plurality of memory cells, such as memory cells 610-640, arranged in an array of columns and rows. Memory cells 610-640 in each column are connected to individual word lines (WL[0], WL[1]). Similarly, memory cells 610-640 in each row are connected between individual bit lines (BL[0], BL[1]) and individual source lines (SL[0], SL[1]). Since memory cells 610-640 are similar in construction and operation, only memory cell 610 will be described. Memory cell 610, for example, memory cell 200, is in the form of a 4T1R memory cell and includes an OTP element 650 and four select transistors 660. For simplicity, only one of the selected transistors 660 is labeled in Figure 6A. The OTP element 650 has a first OTP element terminal connected to two or more bit lines (BL[0]). For example, each bit line (BL[0]) is connected to the VDD node. The memory cell 610 further includes an interconnect 670 that connects the bit lines (BL[0]) in parallel. The first OTP element terminal of the OTP element 650 is connected to the interconnect 670.

[0035] Select transistor 660 has a gate terminal, a first source / drain terminal, and a second source / drain terminal. The gate terminals are connected to each other and to a word line (WL[0]). The first source / drain terminals of select transistor 660 are connected to each other and to a second OTP element terminal of OTP element 650. For example, memory cell 610 further includes an interconnect 680 connecting the first source / drain terminals of select transistor 660 to each other. The second OTP element terminal of OTP element 650 is connected to interconnect 680. The second source / drain terminals of select transistor 660 are connected to each other and to two or more source lines (SL[0]). For example, each source line (SL[0]) is connected to a ground (or VSS) node. Memory cell 610 further includes an interconnect 690 connecting the source lines (SL) in parallel. The second source / drain terminals of select transistor 660 are connected to each other and to interconnect 690.

[0036] As described above, the total trace resistance of the bit lines (BL[0]) is reduced because they are connected in parallel. Furthermore, the total trace resistance of the source lines (SL[0]) is also reduced because they are connected in parallel. This reduction in trace resistance improves the efficiency of current flow, thereby increasing the likelihood of successfully running the program memory unit 610.

[0037] During write or program operation, the OTP element 650 is activated by a high word line (WL[0]) signal ('1') at the word line (WL[0]), enabling access to the memory cell 610. For example, Figure 6B is a schematic timing diagram illustrating the exemplary relationship between the word line (WL) signal, the bit line (BL) signal, and the source line (SL) signal according to various embodiments of the present disclosure. The memory cell 610 is then connected between the bit line (BL[0]) and the source line (SL[0]). A program voltage (Vprog), i.e., a higher voltage, is then applied between the bit line (BL[0]), the memory cell 610, and the source line (SL[0]), causing current to flow. This current can permanently alter the structure of the OTP element 650, for example, creating a conductive path and reducing its resistance to a low (or programmed) state. This programmed state indicates that logic '1' (or '0') is stored in the memory cell 610. Because the bit lines (BL[0]) are connected in parallel, the total trace resistance of the bit lines (BL[0]) is reduced. Additionally, because the source lines (SL[0]) are connected in parallel, the total trace resistance of the source lines (SL[0]) is also reduced. This reduction in trace resistance improves the efficiency of current flow, thereby increasing the likelihood of successfully running the program memory unit 610.

[0038] During a read operation, the high word line (WL[0]) signal at the word line (WL[0]) activates the select transistor 660 and connects the memory cell 610 between the bit line (BL[0]) and the source line (SL[0]). Instead of the higher programming voltage used for programming, a much lower read voltage is applied between the bit line (BL[0]), the memory cell 610, and the source line (SL[0]). If the OTP element 650 is programmed (i.e., it is in a low-resistance state), current flows through it, and the sense amplifier connected to the memory cell 610 interprets the bits stored in the memory cell 610 as logic '1' (or '0'). Otherwise, that is, the OTP element 650 is non-conductive, and there is essentially no current or no current flowing through it. In this state, the sense amplifier interprets the bits stored in the memory cell 610 as logic '0' (or '1').

[0039] Read and write operations on other memory cells are similar to those described above in conjunction with memory cell 610. For example, the next write operation on another memory cell 620-640 activates the word line (WL[1]) using the high word line (WL[1]) signal, while applying a program voltage (Vprog) between the bit line (BL[1]), memory cells 620-640 and the source line (SL[1]).

[0040] Figure 7 is a schematic layout diagram illustrating further exemplary wiring of a memory device (e.g., memory device 600) according to various embodiments of the present disclosure. As illustrated in Figure 7, the exemplary layout 700 includes two or more bit lines (BL[0]), two or more bit lines (BL[1]), a plurality of word lines (e.g., WL[0] and WL[1]), a plurality of interconnects (e.g., IL[0] and IL[1]), two or more vias (VIA[0]), and two or more vias (VIA[1]). The bit lines (BL[0], BL[1]) are alternately arranged along a first direction (x) and each extends in a second direction (y) transverse to the first direction (x).

[0041] The word lines (WL[0], WL[1]) and interconnects (IL[0], IL[1]) each extend in a first direction (x) and are alternately arranged along a second direction (y). In some embodiments, the word lines (WL[0], WL[1]) and interconnects (IL[0], IL[1]) are formed in the same one or more metal layers, for example, in metal layers (M1 and / or M7).

[0042] Each of the vias (VIA[0]) extends in a third direction (z) transverse to the first and second directions (x, y), and connects one of the bit lines (BL[0]) to an interconnect (IL[0]). Similarly, each of the vias (VIA[1]) extends in a third direction (z), and connects one of the bit lines (BL[1]) to an interconnect (IL[1]). Since the bit lines (BL[0], BL[1]) are connected to the same interconnect (IL[0], IL[1]), the bit lines (BL[0], BL[1]) are connected in parallel. This parallel connection reduces the total trace resistance of the bit lines (BL[0], BL[1]), thereby increasing the probability of successful program memory unit 200.

[0043] Furthermore, since the bit lines (BL[0], BL[1]) are alternately arranged along the first direction (x) and the word lines (WL[0], WL[1]) and interconnects (IL[0], IL[1]) are alternately arranged along the second direction (y), this type of construction increases the distance between vias (VIA[0], VIA[1]), thereby preventing violations of via spacing requirements.

[0044] In some embodiments, layout 700 further includes two or more source lines connected in parallel (e.g., SL[0] of Figure 6A) and two or more source lines also connected in parallel (e.g., SL[1] of Figure 6A). The source lines (SL[0], SL[1]) are constructed similarly to the construction described above in conjunction with the bit lines (BL[0], BL[1]). Therefore, for the sake of brevity, a detailed description of the source lines (SL[0], SL[1]) is omitted herein.

[0045] Figure 8 is a schematic layout diagram illustrating further exemplary wiring of a memory device (e.g., memory device 600) according to various embodiments of the present disclosure. As illustrated in Figure 8, the exemplary layout 800 includes two or more bit lines BL[0], two or more bit lines BL[1], a plurality of word lines (e.g., WL[0] and WL[1]), a plurality of interconnects (e.g., IL[0] and IL[1]), two or more vias VIA[0], and two or more vias VIA[1]. The bit lines (BL[0], BL[1]) are alternately arranged along a first direction (x) and each extends in a second direction (y) transverse to the first direction (x).

[0046] The word lines (WL[0], WL[1]) and interconnects (IL[0], IL[1]) each extend in a first direction (x) and are alternately arranged along a second direction (y). In some embodiments, the word lines (WL[0], WL[1]) and interconnects (IL[0], IL[1]) are formed in the same one or more metal layers, for example, in metal layers (M1 and / or M7).

[0047] Each of the vias (VIA[0]) extends in a third direction (z) transverse to the first and second directions (x, y), and connects one of the bit lines (BL[0]) to an interconnect (IL[0]). Similarly, each of the vias (VIA[1]) extends in a third direction (z), and connects one of the bit lines (BL[1]) to an interconnect (IL[1]). Since the bit lines (BL[0], BL[1]) are connected to the same interconnect (IL[0], IL[1]), the bit lines (BL[0], BL[1]) are connected in parallel. This parallel connection reduces the total trace resistance of the bit lines (BL[0], BL[1]), thereby increasing the probability of successful program memory unit 200.

[0048] Furthermore, since the word lines (WL[0], WL[1]) and interconnects (IL[0], IL[1]) are alternately arranged along the second direction (y), this configuration increases the distance between vias (VIA[0], VIA[1]). This increased spacing helps prevent violations of via spacing requirements.

[0049] In some embodiments, layout 800 further includes two or more source lines (e.g., SL[0], SL[1] in parallel connection). The source lines (e.g., SL[0] and SL[1]) are constructed similarly to those described in conjunction with the bit lines (BL[0], BL[1]). Therefore, for the sake of brevity, a detailed description of the source lines (SL[0], SL[1]) is omitted herein.

[0050] Figure 9 is a schematic layout diagram illustrating further exemplary wires of a memory cell according to various embodiments of the present disclosure. As illustrated in Figure 9, an exemplary layout 900 includes two or more bit lines (BL[0]~BL[3]), a plurality of word lines (e.g., word lines WL[0]~WL[3]), a plurality of interconnects (e.g., IL[0]~IL[3]), and two or more vias (VIA[0]~VIA[3]). The bit lines (BL[0]~BL[3]) are alternately arranged along a first direction (x) and each extends in a second direction (y) transverse to the first direction (x).

[0051] The word lines (WL[0]~WL[3]) and interconnects (IL[0]~IL[3]) each extend in a first direction (x) and are alternately arranged along a second direction (y). In some embodiments, the word lines (WL[0]~WL[3]) and interconnects (IL[0]~IL[3]) are formed in the same one or more metal layers, for example, in metal layers (M1 and / or M7).

[0052] Each of the vias (VIA[0]) extends in a third direction (z) transverse to the first and second directions (x, y), and connects one of the bit lines (BL[0]) to an interconnect (IL[0]). Similarly, each of the vias (VIA[1]~VIA[3]) extends in a third direction (z), and connects one of the bit lines (BL[1]~BL[3]) to an interconnect (IL[1]~IL[3]). Since the bit lines (BL[0]~BL[3]) are connected to the same interconnect (IL[0]~IL[3]), the bit lines (BL[0]~BL[3]) are connected in parallel. This parallel connection reduces the total trace resistance of the bit lines (BL[0]~BL[3]), thereby increasing the likelihood of successful program memory cell execution.

[0053] Furthermore, since the bit lines (BL[0]~BL[3]) are alternately arranged along the first direction (x) and the word lines (WL[0]~WL[3]) and interconnects (IL[0]~IL[3]) are alternately arranged along the second direction (y), this type of construction increases the distance between vias (VIA[0], VIA[1]). This increased spacing helps to prevent violations of via spacing requirements.

[0054] In some embodiments, layout 900 further includes two or more source lines (e.g., SL[0]~SL[3]) connected in parallel. The source lines (SL[0]~SL[3]) are constructed similarly to the construction described above in conjunction with the bit lines (BL[0]~BL[3]). Therefore, for the sake of brevity, a detailed description of the source lines (SL[0]~SL[3]) is omitted herein.

[0055] Figure 10 is a schematic layout diagram illustrating further exemplary wiring of a memory cell according to various embodiments of the present disclosure. As illustrated in Figure 10, exemplary layout 1000 includes two or more bit lines (BL), a plurality of word lines (e.g., word lines WL[0] to WL[3]), a plurality of interconnects (e.g., interconnects IL[0] to IL[3]), and two or more vias (VIA). For simplicity, only one of the vias (VIA) is labeled in Figure 10. The bit lines (BL) are arranged along a first direction (x) and each extends in a second direction (y) transverse to the first direction (x).

[0056] The word lines (WL[0]~WL[3]) and interconnects (IL[0]~IL[3]) each extend in a first direction (x) and are alternately arranged along a second direction (y). In some embodiments, the word lines (WL[0]~WL[3]) and interconnects (IL[0]~IL[3]) are formed in the same one or more metal layers, for example, in metal layers (M1 and / or M7).

[0057] Each via (VIA) extends laterally in a third direction (z) beyond the first and second directions (x, y), and connects one of the bit lines (BL) to an interconnect (IL[0]~IL[3]). Since the bit lines (BL) are connected to the same interconnect (IL[0]~IL[3]), the bit lines (BL) are connected in parallel. This parallel connection reduces the total trace resistance of the bit lines (BL), thereby increasing the likelihood of successfully running program memory cells.

[0058] Furthermore, since the word lines (WL[0]~WL[3]) and interconnects (IL[0]~IL[3]) are arranged alternately along the second direction (y), this configuration increases the distance between vias (VIA) along the second direction (y). This increased spacing helps prevent violations of via spacing requirements.

[0059] In some embodiments, layout 1000 further includes two or more source lines (e.g., SL) connected in parallel. The source lines (SL) are constructed similarly to those described above in conjunction with bit lines (BL). Therefore, for the sake of brevity, a detailed description of the source lines (SL) is omitted herein.

[0060] Figure 11 is a schematic layout diagram illustrating further exemplary wiring of a memory device according to various embodiments of the present disclosure. As illustrated in Figure 11, exemplary layout 1100 includes two or more bit lines (BL), a plurality of word lines (e.g., word lines WL[0] to WL[3]), a plurality of interconnects (e.g., interconnects IL[0] to IL[3]), and two or more vias (VIA). For simplicity, only one of the vias (VIA) is labeled in Figure 11. The bit lines (BL) are arranged along a first direction (x) and each extends in a second direction (y) transverse to the first direction (x).

[0061] The word lines (WL[0]~WL[3]) and interconnects (IL[0]~IL[3]) each extend in a first direction (x) and are alternately arranged along a second direction (y). In some embodiments, the word lines (WL[0]~WL[3]) and interconnects (IL[0]~IL[3]) are formed in the same one or more metal layers, for example, in metal layers (M1 and / or M7).

[0062] Each of the vias (VIA) extends laterally in a third direction (z) beyond the first and second directions (x, y), and connects one of the bit lines (BL) to an interconnect (IL[0]~IL[3]). Since the bit lines (BL) are connected to the same interconnect (IL[0]~IL[3]), the bit lines (BL) are connected in parallel. As described above, this parallel connection reduces the total trace resistance of the bit lines (BL), thereby increasing the likelihood of successfully running program memory cells.

[0063] Furthermore, since the alternating bit lines are connected to the interconnects (IL[0]~IL[3]) and the word lines (WL[0]~WL[3]) and interconnects (IL[0]~IL[3]) are alternately arranged along the second direction (y), this configuration increases the distance between vias (VIAs) along the first and second directions (x, y). This increased spacing helps prevent violations of via spacing requirements.

[0064] In some embodiments, layout 1100 further includes two or more source lines (e.g., SL) connected in parallel. The source lines (SL) are constructed similarly to those described above in conjunction with bit lines (BL). Therefore, for the sake of brevity, a detailed description of the source lines (SL) is omitted herein.

[0065] Figure 12 is a schematic layout diagram illustrating further exemplary wiring of a memory device according to various embodiments of the present disclosure. As illustrated in Figure 12, exemplary layout 1200 includes two or more bit lines (BL), a plurality of word lines (e.g., WL[0] to WL[3]), a plurality of interconnects (e.g., IL[0] to IL[3]), and two or more vias (VIA). For simplicity, only one of the vias (VIA) is labeled in Figure 12. The bit lines (BL) are arranged along a first direction (x) and each extends in a second direction (y) transverse to the first direction (x).

[0066] The word lines (WL[0]~WL[3]) and interconnects (IL[0]~IL[3]) each extend in a first direction (x) and are alternately arranged along a second direction (y). In some embodiments, the word lines (WL[0]~WL[3]) and interconnects (IL[0]~IL[3]) are formed in the same one or more metal layers, for example, in metal layers (M1 and / or M7).

[0067] Each via (VIA) extends laterally in a third direction (z) beyond the first and second directions (x, y), and connects one of the subsets of bit lines (BL) to an interconnect (IL[0]~IL[3]). Since the bit lines (BL) are connected to the same interconnect (IL[0]~IL[3]), the bit lines (BL) are connected in parallel. As described above, this parallel connection reduces the total trace resistance of the bit lines (BL), thereby increasing the likelihood of successful program memory cell execution.

[0068] Furthermore, since a subset of bit lines are connected to interconnects (IL[0]~IL[3]) and since word lines (WL[0]~WL[3]) and interconnects (IL[0]~IL[3]) are alternately arranged along the second direction (y), this configuration increases the distance between vias (VIAs) along the first and second directions (x, y). This increased spacing helps prevent violations of via spacing requirements.

[0069] In some embodiments, layout 1200 further includes two or more source lines (e.g., SL) connected in parallel. The source lines (SL) are constructed similarly to those described above in conjunction with bit lines (BL). Therefore, for the sake of brevity, a detailed description of the source lines (SL) is omitted herein.

[0070] Figure 13 is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present disclosure. As illustrated in Figure 13, the exemplary memory device 1300 includes a plurality of memory cells (e.g., memory cells 1310-1340), each memory cell including cell portions 1310a-1310d, 1320a-1320d, 1330a-1330d, and 1340a-1340d. In this exemplary embodiment, cell portions 1310a-1310d, 1320a-1320d, 1330a-1330d, and 1340a-1340d of a memory cell 1310-1340 are separated by cell portions 1310a-1310d, 1320a-1320d, 1330a-1330d, and 1340a-1340d of other memory cells 1310-1340. For example, cell portions 1310a-1310d, 1320a-1320d, 1330a-1330d, and 1340a-1340d are arranged in an array of columns and rows. Cell portions 1310a, 1310b, 1320a, and 1320b are arranged alternately along the first column and are each connected to a word line (WL[1]). Unit portions 1330a, 1330b, 1340a, and 1340b are arranged alternately along the second column and are each connected to a word line (WL[0]). Unit portions 1310c, 1310d, 1320c, and 1320d are arranged alternately along the third column and are each connected to a word line (WL[1]). Unit portions 1330c, 1330d, 1340c, and 1340d are arranged alternately along the fourth column and are each connected to a word line (WL[0]).

[0071] Similarly, cell portions 1310a, 1310c, 1330a, and 1330c are alternately arranged along the first row and each is connected between two or more bit lines (BL[1]) and two or more source lines (SL[1]). Cell portions 1320a, 1320c, 1340a, and 1340c are alternately arranged along the second row and each is connected between two or more bit lines (BL[0]) and two or more source lines (SL[0]). Cell portions 1310b, 1310d, 1330b, and 1330d are alternately arranged along the third row and each is connected between two or more bit lines (BL[1]) and two or more source lines (SL[1]). Cell portions 1320b, 1320d, 1340b, and 1340d are arranged alternately along the fourth row and are each connected between two or more bit lines (BL[0]) and two or more source lines (SL[0]). This configuration of memory cell 1330 simplifies the layout design of the wires (e.g., bit lines, source lines, and word lines) of memory cell 1330.

[0072] Figure 14 is a schematic circuit diagram of another exemplary memory device according to various embodiments of the present disclosure. As illustrated in Figure 14, the exemplary memory device 1400 includes a plurality of memory cells, such as memory cells 1410 to 1480, each memory cell constituting a plurality of memory cells combined into a single memory cell. Since memory cells 1410 to 1480 are structurally similar, only one (e.g., memory cell 1410) will be described. Memory cell 1410 includes a plurality of memory cells 1490. For simplicity, only one of memory cells 1490 is labeled in Figure 14. Each memory cell 1490 is connected to a plurality of word lines (WL) connected to each other and is connected between two or more bit lines (BL[0]) connected in parallel and two or more source lines (SL[0]) connected in parallel. This configuration of the memory device 1400 simplifies the layout design of its wires (e.g., bit lines, source lines, and word lines).

[0073] In some embodiments, memory cell 1410 is connected between a plurality of parallel-connected bit lines (BL[0]) and a single source line (SL[0]). In other embodiments, memory cell 1410 is connected between a plurality of parallel-connected source lines (SL[0]) and a single bit line (BL[0]).

[0074] Figure 15 is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present disclosure. As illustrated in Figure 15, the exemplary memory device 1500 includes a plurality of memory cells, such as memory cells 1510-1580, each memory cell constituting a plurality of memory cells combined into a single memory cell. Since memory cells 1510-1580 are structurally similar, only one (e.g., memory cell 1510) will be described. Memory cell 1510 includes a plurality of memory cells 1590. For simplicity, only one of memory cells 1590 is labeled in Figure 15. Each memory cell 1590 is connected to a byte line (WL[0]-WL[n]) and is connected between two or more bit lines (BL) connected in parallel and two or more source lines (SL) connected in parallel. This construction of the memory device 1500 simplifies the layout design of its wires (e.g., bit lines, source lines, and word lines).

[0075] Figure 16 is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present disclosure. As illustrated in Figure 16, the exemplary memory device 1600 includes a plurality of memory cells, such as memory cells 1610 and 1620, each memory cell constituting a plurality of memory cells combined into a single memory cell. Since memory cells 1610 and 1620 are structurally similar, only one (e.g., memory cell 1610) will be described. Memory cell 1610 includes a plurality of memory cells 1690. For simplicity, only one of the memory cells 1690 is labeled in Figure 16. Each memory cell 1690 is connected to a plurality of word lines (WL[0]) connected to each other and is connected between two or more bit lines (BL) connected in parallel and two or more source lines (SL) connected in parallel. This construction of the memory device 1600 simplifies the layout design of its wires (e.g., bit lines, source lines, and word lines).

[0076] Figure 17 is a schematic diagram illustrating another exemplary memory device according to various embodiments of the present disclosure. As illustrated in Figure 17, the exemplary memory device 1700 includes a plurality of memory cells, such as memory cells 1710 and 1720, each memory cell constituting a plurality of memory cells combined into a single memory cell. Since memory cells 1710 and 1720 are structurally similar, only one (e.g., memory cell 1710) will be described. Memory cell 1710 includes a plurality of memory cells 1790. For simplicity, only one of the memory cells 1790 is labeled in Figure 17. Each memory cell 1790 is connected to a plurality of word lines (WL) connected to each other and is connected between two or more bit lines (BL[0]) connected in parallel and two or more source lines (SL[0]) connected in parallel. This construction of the memory device 1700 simplifies the layout design of its wires (e.g., bit lines, source lines, and word lines).

[0077] In some embodiments, memory cell 1710 is connected between a plurality of parallel-connected bit lines (BL[0]) and a single source line (SL[0]). In other embodiments, memory cell 1710 is connected between a plurality of parallel-connected source lines (SL[0]) and a single bit line (BL[0]).

[0078] Figure 18 is a schematic circuit diagram illustrating another exemplary memory device according to various embodiments of the present disclosure. As illustrated in Figure 18, the exemplary memory device 1800 includes a plurality of memory cells, such as memory cells 1810 and 1820, each memory cell 1810 and 1820 being divided into a plurality of cell portions, such as cell portions 1810a, 1810b, 1820a, and 1820b. Cell portions 1810a and 1810b are separated by cell portion 1820a. Similarly, cell portions 1820a and 1820b are separated by cell portion 1810b.

[0079] Furthermore, each memory cell 1810, 1820 constitutes a plurality of memory cells merged into a single memory cell. Since memory cells 1810, 1820 are structurally similar, only one (e.g., memory cell 1810) will be described. Memory cell 1810 includes a plurality of memory cells 1890. For simplicity, only one of memory cells 1890 is labeled in Figure 18. Each memory cell 1890 is connected to a plurality of word lines (WL) connected to each other, and connected to two or more bit lines (BL[0]) connected in parallel and two or more source lines (SL[0]) connected in parallel. This configuration of memory device 1800 simplifies the layout design of its wires (e.g., bit lines, source lines, and word lines).

[0080] In some embodiments, memory cells 1810 and 1820 are connected between a plurality of parallel-connected bit lines (BL[0], BL[1]) and a single source line (SL[0], SL[1]). In other embodiments, memory cell 1810 is connected between a plurality of parallel-connected source lines (SL[0], SL[1]) and a single bit line (BL[0], BL[1]). In some embodiments, memory cell 1810 is connected between a plurality of parallel-connected bit lines (BL[0], BL[1]) and a single source line (SL[0], SL[1]). In other embodiments, memory cell 1810 is connected between a plurality of parallel-connected source lines (SL[0], SL[1]) and a single bit line (BL[0], BL[1]).

[0081] Figure 19 is a schematic diagram illustrating another exemplary memory device according to various embodiments of the present disclosure. As illustrated in Figure 19, the exemplary memory device 1900 includes a plurality of memory cells, such as memory cells 1910 and 1920. Each memory cell 1910 and 1920 is divided into a plurality of cell portions, such as cell portions 1910a, 1910b, 1920a, and 1920b. Cell portions 1910a and 1910b are separated by cell portion 1920a. Similarly, cell portions 1920a and 1920b are separated by cell portion 1910b.

[0082] Furthermore, each memory cell 1910, 1920 constitutes a plurality of memory cells merged into a single memory cell. Since memory cells 1910, 1920 are structurally similar, only one (e.g., memory cell 1910) will be described. Memory cell 1910 includes a plurality of memory cells 1990. For simplicity, only one of memory cells 1990 is labeled in Figure 19. Each memory cell 1990 is connected to a plurality of word lines (WL[0]) connected to each other, and is connected between two or more bit lines (BL) connected in parallel and two or more source lines (SL) connected in parallel. This configuration of memory device 1900 simplifies the layout design of its wires (e.g., bit lines, source lines, and word lines).

[0083] Figure 20 is a flowchart illustrating an exemplary method 2000 for manufacturing a memory device according to various embodiments of the present disclosure. For ease of understanding, the exemplary method 2000 will now be described with reference to Figures 1 through 19. It should be understood that method 2000 is applicable to structures other than those in Figures 1 through 19. Furthermore, it should be understood that in alternative embodiments of method 2000, additional operations may be provided before, during, and after method 2000, and some of the operations described below may be replaced or eliminated.

[0084] In operation 2010, a device fabrication tool fabricates memory cells (e.g., memory cells 110, 200, 300, 610) over a substrate. For example, Figure 21 is a schematic cross-sectional view illustrating another exemplary memory device 2100 according to various embodiments of the present disclosure. As illustrated in Figure 21, the exemplary memory device 2100 (e.g., memory devices 100-1900) includes a substrate 2110, a plurality of metal layers (M0-M7), and a plurality of vias (V0-V6). The substrate 2110 may be made of silicon, germanium, III-V semiconductors, other suitable substrate materials, and alloys thereof. In this case, the device fabrication tool dops the substrate 2110 to create source and drain regions (S, D) in the active portion of the substrate 2110. Then, a device fabrication tool deposits conductive material to form a metal deposit (MD) on the top surfaces of the source and drain regions (S, D), and a metal gate (MG) above the top surface of the gate region between the source and drain regions (S, D). The source and drain regions (S, D) and the metal gate (MG) constitute a selective transistor (e.g., selective transistors 220, 320, 660).

[0085] Next, in operation 2020, the device fabrication system deposits additional conductive material to form metal layers (e.g., metal layers M0-M7) stacked on top of each other. For example, each metal layer (M0, M2) includes at least one source line (SL) connecting a select transistor to a ground (or VSS) node. Metal layers (M1, M3, M5, M7) include a plurality of word lines (WL), each word line connected to a respective metal gate (MG). Metal layers (M4, M6) include a plurality of bit lines (BL) connecting the VDD node to OTP elements 2120 (e.g., OTP elements 260, 310, 650) of the memory cell. In this exemplary embodiment, metal layers (M1, M3, M5, M7) further include interconnects (e.g., interconnects 230, 330, 670) connecting the bit lines (BL) in parallel. Vias (V0-V6) interconnect the metal layers (M0-M7). Examples of conductive materials include copper (Cu), aluminum (Al), other suitable metals, or alloys thereof.

[0086] In one embodiment, a memory device includes a plurality of memory cells, word lines, a plurality of bit lines, and a plurality of source lines. Each memory cell includes an once-programmable (OTP) element and a plurality of select transistors. Word lines are connected to the gate terminal of the select transistor of the memory cell. Bit lines are connected in parallel between a first node and a first OTP element terminal of the OTP element of the memory cell. Source lines are connected in parallel and connect a second source / drain terminal of the select transistor of the memory cell to a second node.

[0087] In another embodiment, a memory cell includes an once-programmable (OTP) element and a plurality of select transistors. The OTP element has a first OTP element terminal connected to one or more bit lines. Each select transistor has a gate terminal connected to a word line, a first source / drain terminal connected to a second OTP element terminal of the OTP element, and second source / drain terminals connected to one or more source lines, wherein the bit lines are connected in parallel or the source lines are connected in parallel.

[0088] In another embodiment, a method of manufacturing a memory device includes: manufacturing a memory cell over a substrate; forming two or more bit lines connected in parallel between a first node and a first OTP element terminal of an OTP element of the memory cell by depositing conductive material in a first metal layer over the memory cell; depositing conductive material in at least one of a second metal layer below the first metal layer and a third metal layer above the first metal layer to form a word line connected to a gate terminal of a select transistor; and depositing conductive material to form at least one source line. The at least one source line connects a second source / drain terminal of the select transistor to a second node.

[0089] The foregoing summary outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0090] 100, 600, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2100: Memory devices 110, 200, 300, 610, 620, 630, 640, 1310, 1320, 1330, 1340, 1410, 1420, 1430, 1440, 1450, 1460, 1470, 1480, 1490, 1510, 1520, 1530, 1540, 1550, 1560, 1570, 1580, 1590, 1610, 1620, 1690, 1710, 1720, 1790, 1810, 1820, 1890, 1910, 1920, 1990: Memory Units 210, 260, 270, 280, 310, 650, 2120: OTP components 220, 320, 660: Select Transistor 230, 240, 250, 330, 350, 670, 680, 690: Interconnecting cables 360, 370, 380, 390: Equivalent trace resistance 400, 700, 800, 900, 1000, 1100, 1200: Layout 1310a, 1310b, 1310c, 1310d, 1320a, 1320b, 1320c, 1320d, 1330a, 1330b, 1330c, 1330d, 1340a, 1340b, 1340c, 1340d, 1810a, 1810b, 1820a, 1820b, 1910a, 1910b, 1920a, 1920b: Unit Part 2000: Method 2010, 2020: Operations 2110:Substrate BL, BL0, BL1, BL[0], BL[1], BL[2], BL[3], BLn: bit lines D: Duct region IL, IL[0], IL[1], IL[2], IL[3]: interconnection lines M0, M1, M2, M3, M4, M5, M6, M7: Metal layer MD: Metal Deposits MG: Metal Gate S: Source region SL, SL0, SL1, SL[0], SL[1], SLn: source lines VIA, VIA[0], VIA[1], VIA[2], VIA[3], V0, V1, V2, V3, V4, V5, V6: through holes Vprog: Program Voltage W, w1, w2: Width WL, WL0, WL1, WL[0], WL[1], WL[2], WL[3], WLn: word line VDD, VSS: Voltage x: First direction y: Second direction z: Third-party direction

[0091] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A memory device comprising: a plurality of memory cells, the memory cells including a single-programmable element and a plurality of select transistors; a word line connected to a plurality of gate terminals of the select transistors of a memory cell; a plurality of bit lines connected in parallel between a first node and a first single-programmable element terminal of the single-programmable element of the memory cell; a plurality of source lines connected in parallel and connecting second source / drain terminals of the select transistors of the memory cells to a second node; and a first interconnect, one end of the first interconnect being directly connected to one of the source lines, and the other end of the first interconnect being directly connected to the other of the source lines.

2. The memory device as described in claim 1, wherein: The bit lines are arranged along a first direction and each extends in a second direction transverse to the first direction; and the word line extends in the first direction. The memory device further includes: a second interconnect that is substantially parallel to the word line; and a plurality of vias that connect two or more bit lines to the second interconnect.

3. The memory device as described in claim 2, wherein the two or more bit lines are adjacent to each other.

4. The memory device as claimed in claim 2, wherein a distance between the vias is greater than a distance between the bit lines.

5. The memory device as described in claim 1, wherein: The single-programmable element includes an antifuse that is initially in a non-conductive state and is configured to become permanently conductive when a programming voltage is applied across the memory cell via the bit lines and the source lines; the antifuse is formed of a material that is designed to break down when a programming voltage is applied across the memory cell via the bit lines and the source lines form a conductive path.

6. The memory device as claimed in claim 1, wherein the memory cells include a first memory cell and a second memory cell, the memory device further comprising: a second word line connected to a plurality of gate terminals of the select transistors of the first memory cell and the second memory cell; a plurality of second bit lines connected in parallel, wherein the single-programmable element of the first memory cell and the single-programmable element of the second memory cell are connected between the second bit lines and a plurality of first source / drain terminals of the select transistors of the first memory cell and the second memory cell; and a plurality of second source lines connected in parallel and coupled to a plurality of second source / drain terminals of the select transistors of the first memory cell and the second memory cell to a ground node.

7. A memory cell comprising: a single-programmable element having a first single-programmable element terminal connected to one or more of a plurality of bit lines; and a plurality of select transistors having a gate terminal connected to a word line, a first source / drain terminal connected to a second single-programmable element terminal of the single-programmable element, and a second source / drain terminal connected to one or more source lines, wherein the bit lines or the one or more source lines are connected in parallel, wherein the select transistors include at least a first select transistor and a second select transistor, a first source / drain terminal of the first select transistor is connected to a first source / drain terminal of the second select transistor, and a second source / drain terminal of the first select transistor is connected to a second source / drain terminal of the second select transistor.

8. The memory cell as claimed in claim 7 further includes one or more dummy programmable elements, the one or more dummy programmable elements having a first programmable element terminal connected to the one or more bit lines and a second floating programmable element terminal.

9. The memory cell as claimed in claim 7 further comprises: a first interconnect line interconnecting the bit lines; a second interconnect line interconnecting the one or more source lines; and a third interconnect line interconnecting the first source / drain terminals of the selective transistors.

10. A method of manufacturing a memory device, the method comprising the steps of: manufacturing a memory cell on a substrate, the memory cell comprising: A single-programmable element; and one or more selectable transistors; The method involves depositing a conductive material to form a plurality of metal layers, one stacked on top of the other, wherein the metal layers include: a first metal layer including at least one source line connecting the one or more select transistors to a first node; a second metal layer including a word line connected to a plurality of gate terminals of the one or more select transistors; and a third metal layer including a plurality of first bit lines connected in parallel between a second node and the single-programmable element, wherein the second metal layer further includes a first interconnect and a second interconnect, the third metal layer further includes a plurality of second bit lines, the first interconnect being connected to each of the first bit lines, the second interconnect being connected to each of the second bit lines, one of the first bit lines being located between two of the second bit lines, and one of the second bit lines being located between two of the first bit lines.

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