Semiconductor device and method for making semiconductor device

Abstract

A deep trench capacitor (DTC) structure and a method of forming the same, comprising forming a transistor on electrodes within a trench of the deep trench capacitor, the trench comprising alternating layers of a high-k dielectric material and a metal electrode material functionally serving as capacitors. The electrode transistor structure is formed to control the conductivity of the metal electrode layers connecting the transistor gate to the deep trench capacitor trench by applying a gate voltage to switch the capacitance provided by a first capacitor (i.e., a pair of first electrodes and a high-k dielectric) within the deep trench capacitor trench. A deep trench capacitor stack structure provides a stacked and bonded arrangement of multiple DTC wafers and dies by bonding electrical contact pairs or groups of each deep trench capacitor wafer to provide a stacked DTC structure and / or device.

Claims

1. A method of manufacturing a semiconductor device, comprising: forming a first trench in a substrate, the first trench including a first trench bottom and a plurality of first trench sides; forming a first group of alternating layers in the first trench including alternating layers of electrodes and dielectric layers, the first group of alternating layers covering the first trench bottom and the plurality of first trench sides, and the first group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer to form a first capacitor, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; forming a filled dielectric region in a central region of the first trench, the filled dielectric region extending along a longitudinal length of the first trench, and the filled dielectric region forming a core dielectric region of the first trench, the core dielectric region being at least partially surrounded by the first group of alternating layers; A thin-film transistor structure is formed on the first longitudinal end of the first metal electrode layer. The thin-film transistor structure includes a gate region, a dielectric region, and a semiconductor region. The semiconductor region is operatively connected to the first metal electrode layer. The thin-film transistor structure is configured to control the conductivity from the gate region of the thin-film transistor structure to the first metal electrode layer by applying a gate voltage to switch on and off a capacitance provided by the first capacitor. A first metal contact is formed on the gate region of the thin-film transistor structure, and a second metal contact is formed on the first longitudinal end of the second metal electrode.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein forming the alternating plurality of layers of the first group in the first trench further comprises: forming a second dielectric layer and a third metal electrode, the second dielectric layer being disposed between the second metal electrode layer and the third metal electrode layer to form a second capacitor having a capacitance greater than that of the first capacitor, the third metal electrode layer including a first longitudinal end and a second longitudinal end; and forming a third metal contact on the first longitudinal end of the third metal electrode.

3. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising: operably connecting the first metal contact and the second metal contact to an integrated circuit (IC) voltage output, the IC voltage output including a first voltage operably applied to the first metal contact and a second voltage operably applied to the second metal contact, the first voltage being greater than the second voltage.

4. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising: forming a pad layer in the first trench before forming the alternating plurality of layers of the first group in the first trench.

5. A semiconductor device comprising: a semiconductor substrate; a first trench formed in the semiconductor substrate, the first trench including a first trench bottom and a plurality of first trench sides; a first group of alternating layers including alternating electrode layers and a plurality of dielectric layers formed in the first trench, the first group of alternating layers covering the first trench bottom and the plurality of first trench sides, and the first group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer to form a first capacitor, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; A filled dielectric region is formed in a central region of the first trench, the filled dielectric region extending along a longitudinal length of the first trench and forming a core dielectric region of the first trench, the core dielectric region being at least partially surrounded by alternating layers of the first group; and a thin-film transistor structure is formed on the first longitudinal end of the first metal electrode layer, the thin-film transistor structure including a gate region, a dielectric region, and a semiconductor region operatively connected to the first metal electrode layer, the thin-film transistor structure being configured to control the conductivity from the gate region of the thin-film transistor structure to the first metal electrode layer by applying a gate voltage to switch on and off a capacitance provided by the first capacitor.

6. The semiconductor device of claim 5, further comprising: a second trench formed in the semiconductor substrate, the second trench including a second trench bottom and a plurality of second trench sides, and the second trench being separated from the first trench via the semiconductor substrate; a second group of alternating layers including alternating electrode layers and dielectric layers formed in the second trench, the second group of alternating layers covering the second trench bottom and the plurality of second trench sides, and the second group of alternating layers including a first metal electrode layer, a second metal electrode layer, and a first dielectric layer disposed between the first metal electrode layer and the second metal electrode layer to form a first capacitor, each of the first metal electrode layer and the second metal electrode layer including a first longitudinal end and a second longitudinal end; A filled dielectric region is formed in a central region of the second trench, the filled dielectric region extending along a longitudinal length of the second trench and forming a core dielectric region of the second trench, the core dielectric region being at least partially surrounded by alternating layers of the second group; and a first metal contact and a second metal contact, the first metal contact being formed at a first longitudinal end of the first metal contact and the second metal contact being formed at a first longitudinal end of the second metal electrode.

7. The semiconductor device as claimed in claim 6 further includes: a metallization layer circuit electrically connecting the first metal contact of the first trench and the first metal contact of the second trench, and electrically connecting the second metal contact of the first trench and the second metal contact of the second trench.

8. The semiconductor device as described in claim 7, wherein, The first trench has a first trench depth, and the second trench has a second trench depth, the first trench depth being different from the second trench depth.

9. A method of manufacturing a semiconductor device, comprising: forming a first deep trench capacitor structure in a first semiconductor substrate, the first deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the first semiconductor substrate, and the plurality of planarized metal contacts extending into an intermetallic region formed on the first semiconductor substrate; and forming a second deep trench capacitor structure in a second semiconductor substrate, the second deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the second semiconductor substrate, and the plurality of planarized metal contacts extending into an intermetallic region formed on the second semiconductor substrate; The first deep trench capacitor structure is joined to the second deep trench capacitor structure by joining each of the plurality of planarized metal contacts of the first deep trench capacitor structure to a corresponding one of the plurality of planarized metal contacts of the second deep trench capacitor structure, thereby electrically connecting the first deep trench capacitor structure and the second deep trench capacitor structure; and a first integrated circuit interconnect structure is formed, the first integrated circuit interconnect structure including a plurality of metal contacts electrically connected to the plurality of electrodes within the first deep trench capacitor structure to provide an integrated circuit (IC) including a stacked deep trench capacitor (DTC) structure.

10. The method of manufacturing a semiconductor device as claimed in claim 9, further comprising: forming a first metallization layer circuit that provides multiple electrical connections to a plurality of other deep trench capacitor structures operatively connected to the first integrated circuit interconnect structure.

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