Composite semiconductor structure including fin transistors and planar transistors

Abstract

This invention provides a composite semiconductor structure comprising a finned transistor and a planar transistor, comprising a finned structure region comprising a plurality of first finned structures and at least one finned transistor located within the finned structure region, a planar region comprising at least one planar transistor, wherein the planar region is adjacent to the finned structure region, a transition region defined as the region between the finned structure region and the planar region, a first active region surrounding the finned structure region, wherein the first active region comprises a plurality of second finned structures or comprises a first diffusion region, and at least a portion of the first active region is located within the transition region, and a second active region surrounding the planar region, wherein the second active region comprises a second diffusion region, and at least a portion of the second active region is located within the transition region.

Claims

1. A composite semiconductor structure comprising a finned transistor and a planar transistor, comprising: a finned structure region comprising a plurality of first finned structures, wherein at least one finned transistor (FinFET) is located within the finned structure region; a planar region comprising at least one planar transistor, wherein the planar region is adjacent to the finned structure region; a transition region defined as the region between the finned structure region and the planar region; a first active region surrounding the finned structure region, wherein the first active region comprises a plurality of second finned structures or comprises a first diffusion region, and at least a portion of the first active region is located within the transition region; and a second active region surrounding the planar region, wherein the second active region comprises a second diffusion region, and at least a portion of the second active region is located within the transition region.

2. The semiconductor structure as described in claim 1 further includes a shallow trench isolation (STI) disposed between the fin structure region and the first active region, and between the planar region and the second active region.

3. The semiconductor structure as described in claim 2, wherein the shallow trench isolation (STI) is disposed between the first active region and the second active region.

4. The semiconductor structure as described in claim 1, wherein the first active region and the second active region are at least one of a guard ring, a pickup structure, or a tap structure.

5. The semiconductor structure as described in claim 1, wherein the second active region does not include a fin structure.

6. The semiconductor structure as described in claim 1, wherein the planar transistor in the planar region is a high-voltage device with an operating voltage between 5V and 40V.

7. The semiconductor structure as described in claim 1, wherein the finned transistor in the finned structure region is a low-voltage element with an operating voltage between 0V and 3V.

8. The semiconductor structure as described in claim 1, wherein the first active region and the second active region are electrically connected to a substrate to provide electrical isolation or stabilization.

9. The semiconductor structure as described in claim 1, wherein the distance between the planar region and the second active region is within an allowable spacing range, wherein the allowable spacing range is from 1 micrometer to 3 micrometers.

10. The semiconductor structure as described in claim 1, wherein the first active region includes a diffusion region and does not include a fin structure, and the first active region is interconnected with the second active region.

11. The semiconductor structure as described in claim 1, wherein the diffusion region in the second active region comprises a doped silicon layer.

12. A method for fabricating a composite semiconductor structure comprising a finned transistor and a planar transistor, comprising: providing a substrate, defining a finned structure region on the substrate, and forming a plurality of finned structures and at least one finned transistor (FinFET) located within the finned structure region; defining a planar region on the substrate, and forming at least one planar transistor located within the planar region, wherein the planar region is adjacent to the finned structure region; defining a region between the finned structure region and the planar region as a transition region; forming a first active region surrounding the finned structure region, wherein the first active region comprises at least one of a finned structure or a diffusion region, and at least a portion of the first active region is located within the transition region; and forming a second active region surrounding the planar region, wherein the second active region comprises a diffusion region, and at least a portion of the second active region is located within the transition region.

13. The method of fabricating a semiconductor structure as described in claim 12 further includes forming a shallow trench isolation (STI) disposed between the fin structure region and the first active region, and between the planar region and the second active region.

14. The method of fabricating a semiconductor structure as described in claim 13, wherein the shallow trench isolation (STI) is disposed between the first active region and the second active region.

15. The method for fabricating a semiconductor structure as described in claim 12, wherein the first active region and the second active region are at least one of a guard ring, a pickup structure, or a tap structure.

16. The method for fabricating a semiconductor structure as described in claim 12, wherein the second active region does not include a fin structure.

17. A method for fabricating a semiconductor structure as described in claim 12, wherein the first active region and the second active region are electrically connected to a substrate to provide electrical isolation or stabilization.

18. A method for fabricating a semiconductor structure as described in claim 12, wherein the semiconductor structure is configured for use in a system-on-a-chip (SoC) comprising a combination of a high-voltage component and a low-voltage component.

19. A method for fabricating a semiconductor structure as described in claim 12, wherein the distance between the planar region and the second active region is within an allowable spacing range, wherein the allowable spacing range is from 1 micrometer to 3 micrometers.

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