Charge pump device and method for operating a charge pump device

Abstract

A charge pump unit for a charge pump is disclosed, which exhibits improved latch-up immunity. Configurable circuitry at the charge pump unit applies a voltage to the body contacts of the charge transfer transistor of the charge pump unit in at least a partial response to a relationship between the voltage at a first terminal and the voltage at a second terminal of the charge transfer transistor. A charge pump including one or more such charge pump units may include a control loop configured to control pump signals in at least a partial response to the state of the charge pump's output voltage.

Description

Technical Field

[0001] [Cross Reference to Related Applications] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 026,435, filed May 18, 2020, pursuant to 35 USC §119(e), the disclosure of which is hereby incorporated herein by reference in its entirety.

[0002] One or more embodiments are generally related to charge transfer switches. One or more embodiments are generally related to multiple charge pump units for a charge pump and a charge pump including such charge pump units. CMOS devices including such charge transfer switches, charge pump units, or charge pumps can exhibit latch-up immunity to parasitic structures that are turned on during the power-on period of such CMOS devices. Prior Technology

[0003] Complementary metal-oxide-semiconductor (CMOS) charge pumps are used in a variety of operating scenarios, such as applications where the supply voltage is lower than the voltage used for the operation of integrated circuit (IC) devices. A CMOS charge pump can act as a voltage multiplier, providing a voltage at its output that represents a voltage level multiple of the voltage level represented by the voltage at its input (e.g., but not limited to, the supply voltage), thereby providing sufficient voltage to the IC device for operation when the supply voltage is otherwise too low.

[0004] As a non-limiting embodiment of a typical CMOS charge pump known to the inventors of this invention, the CMOS charge pump receives an input voltage and a pump signal (e.g., a pulsed signal such as, but not limited to, a clock or phase signal), transfers the input voltage to a node coupled to one side of a capacitor ("boost node") via a first charge transfer switch, increases the input voltage at the boost node by applying the pump signal to the other side of the capacitor, and transfers the increased voltage to an output terminal via a second charge transfer switch. Due to current consumption at an external load coupled to the output terminal, the CMOS charge pump may need to continuously supply the increased voltage. A typical CMOS charge pump may use NMOS or PMOS transistors as transfer switches. Summary of the Invention

[0005] The present invention provides an apparatus comprising: a CMOS structure; a first transistor disposed in the CMOS structure; and a circuit configured to apply a shielding voltage to a body contact of the first transistor in response at least in part to a relationship between a voltage at a first terminal of the first transistor and a voltage at a second terminal of the first transistor. Simple Explanation of the Diagram

[0006] Figure 1 is a diagram depicting a conventional charge pump known to the inventors of this disclosure as being susceptible to latch-up risks. Figure 2 is a diagram depicting an NMOS transistor (in this particular embodiment, an NMOS transistor having three terminals for the source, drain, and gate) of any of the charge pump units depicted in Figure 1. Figure 3 is a diagram depicting a charge pump unit that can exhibit improved latch-up immunity according to one or more embodiments. Figure 4 is a schematic diagram depicting a charge transfer switch according to one or more embodiments. Figure 5 is a diagram depicting a charge pump unit that can exhibit improved latch-up immunity according to one or more embodiments. Figure 6 is a schematic diagram depicting a charge transfer switch according to one or more embodiments, and the charge transfer switch is a non-limiting embodiment of the charge transfer switch depicted in Figure 5. Figure 7A is a flowchart depicting the process of operating a charge transfer transistor for a charge transfer switch according to one or more embodiments. Figure 7B is a flowchart depicting the process of applying voltage to the body contact of a charge transfer transistor of a charge transfer switch according to one or more embodiments. Figures 7C and 7D are flowcharts depicting the first and second relationships of the process described in Figure 7B, respectively, in the case of an NMOS or PMOS charge transfer transistor according to one or more embodiments. Figure 8 is a diagram depicting a charge pump unit circuit with an regulated output voltage according to one or more embodiments. Figure 9 is a topological diagram depicting an embodiment of adjusting the voltage output of a charge pump and a charge pump unit according to one or more embodiments. Figure 10 is a topological diagram depicting an embodiment of adjusting the voltage output of a charge pump and a charge pump unit according to one or more embodiments. Figure 11 is a block diagram depicting some or all of the circuit systems used to perform the features or elements disclosed in one or more embodiments. Implementation

[0007] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and specific examples in which the invention can be practiced are illustrated by means of description. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. However, other embodiments permitted herein and structural, material, and process changes may be made without departing from the scope of the invention.

[0008] The descriptions presented herein do not represent actual views of any particular method, system, apparatus, or structure, but are merely idealized representations used to depict embodiments of the invention. In some cases, for the reader's convenience, similar structures or components in various figures may retain the same or similar designations; however, similarity in designations does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0009] The following description may include embodiments to assist those skilled in the art in practicing the disclosed embodiments. The use of the terms "illustrative," "by way of an embodiment," and "for example" is intended to mean that the related description is explanatory, and although the scope of the invention is intended to cover the embodiments and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of the invention to the specified components, steps, features, functions, or the like.

[0010] It is readily understood that the components of the embodiments typically depicted herein and illustrated in the drawings can be configured and designed in a wide variety of different ways. Therefore, the following description of various embodiments is not intended to limit the scope of the invention, but merely to illustrate various embodiments. Although various forms of embodiments may be presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0011] Furthermore, the specific embodiments shown and depicted are merely illustrative and should not be considered the only way to practice the invention unless otherwise specified herein. Components, circuits, and functions may be shown in block diagram form so as not to obscure the invention with unnecessary details. Conversely, the specific embodiments shown and depicted are merely exemplary and should not be considered the only way to practice the invention unless otherwise specified herein.

[0012] Furthermore, the block definition and logical partitioning between various blocks demonstrate a specific implementation. It will be readily apparent to those skilled in the art that the invention can be practiced using numerous other partitioning solutions. To the greatest extent possible, details regarding timing considerations and the like have been omitted, as such details are unnecessary for obtaining a complete understanding of the invention and are within the capabilities of those generally skilled in the art.

[0013] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For clarity of presentation and depiction, some diagrams may exemplify a signal as a single signal. Those skilled in the art will understand that a signal can represent a bus of signals, wherein the bus can have various bit widths, and the present invention can be implemented on any number of data signals including a single data signal.

[0014] The various illustrative logic blocks, modules, and circuits depicted in conjunction with the embodiments disclosed herein can be implemented or executed by a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof (all of which are covered by the use of the term "processor"). A general-purpose processor may be a microprocessor, but in alternative examples, the processor may be any known processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer, and the general-purpose computer is configured to execute computational instructions (e.g., but not limited to, software code) related to embodiments of the invention.

[0015] The embodiments can be described as processes depicted as flowcharts, flow diagrams, or block diagrams. Although a flowchart can depict operations as sequential processes, many of these operations can be performed in another order, in parallel, or substantially simultaneously. Furthermore, the order of operations can be reconfigured. A process can correspond to a method, thread, function, procedure, subroutine, subprogram, other structure, or a combination thereof. Moreover, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, the functions can be stored as one or more instructions or program code on or transmitted via a computer-readable medium. Computer-readable media includes both computer storage media and communication media, and communication media includes any media that facilitates the transfer of computer programs from one place to another.

[0016] The use of names such as "first," "second," etc., to refer to any element herein does not limit the number or order of such elements, unless such limitation is expressly stated. In fact, such designations may be used herein as a known method of distinguishing two or more elements or instances of elements. Therefore, references to a first element and a second element do not imply that only two elements may be used herein, or that the first element must precede the second element in some way. Furthermore, unless otherwise stated, a group of elements may include one or more elements.

[0017] As used herein, the terms "substantially" or "about" with respect to a given parameter, characteristic, or condition mean and include what a person skilled in the art would understand to some extent as a small degree of variation in the given parameter, characteristic, or condition (such as within acceptable manufacturing or operational tolerances). As an example, depending on the specific parameter, characteristic, or condition that is substantially compliant, it may be at least 90%, at least 95%, or even at least 99% compliant.

[0018] As used herein, any relational terms such as, but not limited to, “above,” “below,” “on,” “under,” “upper,” or “lower” are used for clarity and convenience of understanding the invention and in conjunction with the accompanying drawings, and do not imply or depend on any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0019] In this description, the term "coupled" and its derivatives are used to indicate that two elements cooperate or interact with each other. When an element is described as "coupled" to another element, the elements may be in direct physical or electrical contact, or there may be an intermediary element or layer present. In contrast, when an element is described as "directly coupled" to another element, there is no intermediary element or layer present. Unless otherwise expressly indicated or the context would otherwise indicate to a person skilled in the art, the term "connected" is used interchangeably with the term "coupled" in this description and has the same meaning as "coupled." It should be understood that when an element is referred to as "connected" or "coupled" to both the first and second elements, it is coupled to the first element and coupled to the second element.

[0020] When an element is referred to herein as being “electrically coupled” to another element, one or more of the charge or signal may be transferred between the element and the other element directly or via an intermediary element (if present). It should be understood that when an element is referred to herein as being “electrically connected” or “electrically coupled” to a first element and a second element, one or more of the charge or signal may be transferred between the first element and the second element via that element, directly or via an intermediary element (if present).

[0021] In some applications, the operational requirements for application-specific integrated circuits (ASICs) and other ICs often vary depending on the specific application. As a non-limiting example, security is a concern in automotive applications, therefore the requirements for automotive intellectual property (IP) units (i.e., the requirements for integrated circuit designs used to implement electronic systems) typically differ from other business requirements where security is not a primary concern.

[0022] As a non-limiting embodiment, in the case of a touch ASIC (e.g., but not limited to, an ASIC for controlling a touch display (e.g., but not limited to, a control unit of a smartphone, tablet, home appliance, or automobile or other vehicle) or touch input (e.g., but not limited to, a touchpad or touch button), a charge pump can be used to provide a supply voltage that is better suited to the voltage level of the scanning screen (e.g., but not limited to, a higher voltage) than the originally available supply voltage.

[0023] As a non-limiting embodiment, during the energization of the charge pump, charge pumps and other devices implemented in CMOS technology known to the inventors of this invention may be susceptible to a "latch-up" phenomenon. Latch-up is a condition in which parasitic structures (such as, but not limited to, PNP bipolar junction transistors (BJTs) or PN diodes) conduct electricity at the CMOS structure, which may impair the proper or reliable operation of transistors or other CMOS devices disposed at the CMOS structure and including therein, and sometimes cause permanent damage to them. If latch-up occurs at a device, the device may not meet the quality requirements for applications where safety is a consideration (such as automotive, medical, and certain industrial controls).

[0024] Figure 1 is a diagram depicting a charge pump 100, an embodiment of the prior art known to the inventors of this disclosure. The charge pump 100 includes three charge pump units 102a, 102b, and 102c, arranged in series between an input node 104 and an output node 106. Each of the charge pump units 102a to 102c includes a designated P-side and an N-side, through which one of a pair of 180-degree out-of-phase pump signals CLKP or CLKN is supplied for application to each of the pump capacitors 108a to 108c and 110a to 110c. Using charge pump unit 102a as an example, the pump signal CLKP is applied to pump capacitor 108a, which is configured to inject charge at an internal node 112a in response to the pump signal CLKP. Charge transfer switches 114a to 114c, internal nodes 112a to 112c, and pump capacitors 108a to 108c are more generally referred to herein as being on the "P-side" of the respective charge pump units 102a to 102c and charge pump 100. Similarly, charge transfer switches 116a to 116c, internal nodes 118a to 118c, and pump capacitors 110a to 110c are more generally referred to herein as being on the "N-side" of the respective charge pump units 102a to 102c and charge pump 100.

[0025] When pump signals CLKP and CLKN are applied to charge pump units 102a to 102c and input voltage VIN is applied to input node 104 of charge pump 100 (in this particular embodiment, input voltage VIN is set to 3V), an output voltage VOUT (in this particular embodiment, 12V) is expected to be obtained at output node 106. As shown, approximately 6V is expected to be obtained at the output of charge pump unit 102a, which supplies the input of charge pump unit 102b, and approximately 9V is expected to be obtained at the output of charge pump unit 102b, which supplies the input of charge pump unit 102c. The output voltage VOUT is a multiple of VIN, wherein this relationship is based at least in part on the number of charge pump units 102a to 102c, the capacitance of pump capacitors 108a to 108c and 110a to 110c, and the frequencies of pump signals CLKN and CLKP.

[0026] Each of the charge pump units 102a to 102c is a CMOS device, including a cross-coupled PMOS (P-type metal-oxide-semiconductor) transistor and a cross-coupled NMOS (N-type metal-oxide-semiconductor) transistor, both of which are enhancement-mode. The body and source of each CMOS transistor in the charge pump units 102a to 102c are electrically coupled.

[0027] Figure 2 is a diagram illustrating an embodiment of an NMOS charge transfer switch 200 with a parasitic structure of any one of the charge pump units 102a to 102c of Figure 1, according to the prior art known to the inventors of this disclosure. The NMOS charge transfer switch 200 is an NMOS transistor built into a deep N-well 202 and a P-well 204 of a CMOS structure 214, electrically coupled to the source terminal S via a body contact B of the NMOS transistor and an electrical coupling 212. Notably, the NMOS transistor built into the deep N-well can, for design purposes, limit the body voltage and drain voltage within a predetermined voltage range during operation, for example, to attempt to avoid latch-up.

[0028] Regarding latch-up, during the energization of the NMOS charge transfer switch 200, the deep N-well 202 is electrically coupled to the highest voltage level (i.e., the most reliable available voltage level) in the charge pump or charge pump unit (e.g., but not limited to, charge pump 100 or charge pump units 102a to 102c) to suppress the conduction of the parasitic PNP bipolar junction transistor (BJT) 208, where the P-well 204 is the emitter, the deep N-well 202 is the base, and the P-substrate 206 is the collector. The parasitic PNP BJT 208 conducts when its emitter voltage (e.g., the voltage level at the P-well 204) is higher than its base voltage (e.g., the voltage level at the deep N-well 202) and its base voltage is higher than its collector voltage (e.g., the voltage level at the P-substrate 206). This forces the voltage at deep N-well 202 to reach the highest voltage level exhibited at the charge pump or charge pump unit, ensuring that the base voltage is greater than or equal to the emitter voltage of the parasitic PNP BJT 208.

[0029] In charge pump 100, it is reasonable to expect the highest voltage level (i.e., the highest usable voltage level reliably) to be represented by the output voltage VOUT of charge pump 100, and therefore in charge pump 100, each of the deep N-wells of charge transfer switches 116a to 116c is electrically coupled to output node 106 to receive the output voltage VOUT, as depicted in Figure 2, where deep N-well 202 is electrically coupled to output node 106 to receive the output voltage VOUT.

[0030] The inventors of this disclosure now understand that when charge pump 100 and charge pump units 102a, 102b and 102c are energized, the output voltage VOUT at output node 106 is initially 0 V and then ramps up (referred to herein as the "ramp cycle") to the highest voltage level at charge pump 100 for a short duration, and then finally reaches a fully elevated voltage level. During the initial duration of the ramp cycle, the output voltage VOUT is not the highest voltage level at charge pump 100, so the parasitic PNP BJT 208 can be turned on when its emitter voltage (e.g., the voltage level at P-well 204) is higher than its base voltage (e.g., the voltage level at deep N-well 202) and its base voltage is higher than its collector voltage (e.g., the voltage level at P-substrate 206). In the CMOS structure of the embodiment depicted in Figure 2, the conducting parasitic PNP BJT 208 can inject current into the P-substrate 206 (in other words, leakage current can flow from the P-well 204 to the P-substrate 206). In silicon-on-CMOS devices such as the NMOS charge transfer switch 200, leakage current flow to the P-substrate 206 can cause latch-up, which can reduce the reliability of such CMOS devices or products (e.g., the charge pump may generate voltages less than the full rise or even 0 volts, and there may be significant power losses due to current flowing to ground, but not limited to this), and increase the risk that such CMOS devices or products will fail (in some cases, irreversibly). Therefore, the conduction of the parasitic PNP BJT 208 increases the latch-up risk of the charge pump units (e.g., but not limited to, charge pump units 102a to 102c) and the charge pumps including them (e.g., but not limited to, charge pump 100).

[0031] In a typical charge pump, the P-well 204 of the NMOS charge transfer switch 200 is electrically coupled to the input voltage VIN, and the input voltage VIN at the input node 104 is typically the lowest voltage level exhibited at this charge pump during its operation.

[0032] The inventors of this invention now understand that during the energization of the NMOS charge transfer switch 200, the input voltage VIN will be at least temporarily (i.e., at least a portion of the ramp-up period) greater than the output voltage VOUT, and the parasitic PN diode 210 can be turned on (as a supplement to or alternative to the parasitic PNP BJT 208), wherein the P-well 204 is the anode and the drain (D)-N junction is the cathode. When the voltage at the anode of the parasitic PN diode 210 is greater than the voltage level at the cathode, such a parasitic PN diode 210 can inject current into the P-well 204. The increased leakage current flow into the P-well 204 of the CMOS device increases the risk of latch-up phenomena and related problems as discussed above. Although not depicted, the parasitic diode or BJT can similarly conduct from the drain-P junction, N-well, and P-substrate of the PMOS transistor.

[0033] One option for improving latch-up immunity known to the inventors of this disclosure is to precharge one or more nodes of the charge pump (e.g., but not limited to, input nodes, output nodes, boost nodes, or internal nodes not associated with the charge pump) to an appropriate high voltage before the charge pump begins operation (e.g., before energizing or after energizing but before applying the input voltage VIN). For example, this can be achieved by using an auxiliary charge pump to precharge one or more input, output, or internal nodes of the charge pump or charge pump unit. The inventors of this disclosure now understand that performing precharging adds to the duration of starting the charge pump or charge pump unit (e.g., the "precharge phase") and silicon footprint cost.

[0034] The inventors of this disclosure now understand from the reduced latch-up risk (i.e., latch-up immunity) the potential for charge transfer switches or charge pump units with improved latch-up immunity and improved performance, which maintain low area cost (e.g., silicon, as a non-limiting embodiment, compared to charge pumps utilizing the auxiliary charge pump described above), and additionally or alternatively exhibit short duration of energization (e.g., as a non-limiting embodiment, compared to charge pumps utilizing the auxiliary charge pump described above with added pre-charge phase).

[0035] One or more embodiments are generally related to a charge transfer switch exhibiting latch-up immunity. A unit including this charge transfer switch can exhibit increased latch-up immunity, as can multiple charge pumps including the charge transfer switch. In one or more embodiments, the charge pump unit may include a charge transfer switch comprising: a transistor disposed at a CMOS structure for electrically coupling an input node to a boost node (and also referred to herein as a "charge transfer transistor"); a first shielding circuit configured to provide a shielding voltage VSH to the body of the CMOS structure (e.g., but not limited to, a P-well or a P-substrate); and a second shielding circuit configured to provide the shielding voltage VSH to a deep N-well of the CMOS structure. In one or more embodiments, the shielding voltage VSH may more generally represent a voltage level representing the lowest available voltage level at the charge pump unit or charge pump. The first shielding circuit may include a voltage selector configured to select the lowest voltage level between the voltage at the source of the transistor (which may be electrically coupled to the input node of the charge pump unit) and the voltage at the drain of the transistor (which may be electrically coupled to an internal node of the charge pump unit, where a boosted voltage is generated in response to a pump signal (this internal node may also be referred to herein as the "boost node")).

[0036] It is noteworthy that, unless explicitly stated otherwise, this disclosure does not require a specific degree of latch-up immunity at the charge pump unit or charge pump. As a non-limiting embodiment, all or fewer of the disclosed charge pump units may be utilized, and all or fewer of the disclosed charge transfer switches may be utilized (in all cases, without departing from the scope of the invention).

[0037] Figure 3 is a diagram depicting a charge pump unit 300 that can exhibit improved latch-up immunity according to one or more embodiments. Typically, the charge pump unit 300 is configured to generate an output voltage VOUT at output node 308 in response to pump signals CLKP and CLKN and an input voltage VIN. The charge pump unit 300 includes cross-coupled NMOS charge transfer switches 302 and 304 (also referred to herein as "first NMOS charge transfer switch 302" and "second NMOS charge transfer switch 304") and cross-coupled PMOS charge transfer switches 316 and 318.

[0038] The NMOS charge transfer switches 302 and 304 of the charge pump unit 300 each include three NMOS transistors configured (i.e., electrically coupled via their respective terminals and body contacts, as depicted in FIG3) as a single NMOS transfer switch (i.e., the first charge transfer switch 302 and the second charge transfer switch 304). Charge transfer switches 302 and 304 each include an NMOS charge transfer transistor M1 (referred to herein as "charge transfer transistor M1" and more generally as "first transistor") assisted by circuitry 320, which is typically configured to apply a shielding voltage representing the lower of a voltage level represented by the voltage at the first terminal and a voltage level represented by the voltage at the second terminal. Circuitry 320 may include a configuration of two NMOS transistors M2 and M3 (referred herein as "transistor M2" and "transistor M3", and more generally as "second transistor" and "third transistor"). The gates of the respective charge transfer transistors of charge transfer switches 302 and 304 are electrically coupled to internal nodes 310 and 314, respectively. For ease of explanation, Figure 3 depicts transistors M1, M2, and M3 used only for the first charge transfer switch 302, but the discussion of the first charge transfer switch 302 also applies to the second charge transfer switch 304.

[0039] In one or more embodiments, during the energization of the charge pump unit 300, and more specifically during the energization of the charge transfer switch 302, a shielding voltage VSH is applied to the body contact 312 of the charge transfer transistor M1 (e.g., a conductive material directly coupled to the P-well of the CMOS structure, where the charge transfer transistor M1 is provided) to suppress leakage current generation in the P-well 404, as will be further described below with respect to FIG4, for example, but not limited to, during the energization period as discussed above.

[0040] In one or more embodiments, transistors M2 and M3 are configured as circuit 320, which is configured to select a voltage exhibiting the lowest voltage level (discussed below) and apply the selected voltage as a shielding voltage VSH to the body contact 312 of charge transfer transistor M1 to force the P-well 404 of charge transfer transistor M1 to reach the lowest voltage level in charge pump unit 300, and thus ensure that the voltage level at P-well 404 is not higher than the voltage level at deep N-well 402, as will be further described below with respect to FIG4. Such voltage selectors select between the voltage at the source S1 (also referred to herein as charge transfer transistor M1 and more generally as the "second terminal" of charge transfer switch 302) of charge transfer transistor M1, which is electrically coupled to the input node 306 of charge pump unit 300 to receive input voltage VIN, and the voltage at the drain D1 (also referred herein as charge transfer transistor M1 and more generally as the "first terminal" of charge transfer switch 302) of transistor charge transfer transistor M1, which is electrically coupled to the internal node 310 to receive boost voltage VBOOST, which exhibits a voltage level ranging from about 0 to about (S+1)*VIN (where S is the number of stages of charge pump unit to a given node).

[0041] Typically, during the energization of the charge pump unit 300, and more specifically during the energization of the charge transfer switch 302, a shielding voltage VSH is further applied to the deep N-well 402 of the charge transfer transistor M1 (as depicted in Figure 4). Therefore, the voltage levels exhibited at the P-well 404 and the deep N-well 402 of the CMOS structure where the charge transfer transistor M1 is located are substantially the same. The equal voltage levels exhibited at the emitter and base of the parasitic PNP BJT suppress PNP BJT conduction, and thus no current is injected into the P-substrate 406. Furthermore, the equal voltage levels exhibited at the anode and cathode of the parasitic diode suppress parasitic diode conduction, and thus no current is injected into the P-well.

[0042] Figure 4 is a schematic diagram depicting a charge transfer switch 400 according to one or more embodiments. The charge transfer switch 400 is a non-limiting embodiment of the charge transfer switch 302 or 304 of Figure 3.

[0043] The CMOS structure 414 includes a single P-well (P-well 404) and a single deep N-well (deep N-well 402) that substantially encapsulates the single P-well 404. Transistors M1, M2, and M3 are disposed in the CMOS structure 414, and more specifically, in the single P-well 404 and the single deep N-well 402 that substantially encapsulates the single P-well 404 and is supported by a common P-substrate 406. The deep N-well 402 is therefore disposed between the P-well 404 and the P-substrate 406.

[0044] The gate of transistor M2 is electrically coupled to the source S1 of charge transfer transistor M1, and the gate of transistor M3 is electrically coupled to the drain D1 of charge transfer transistor M1. The drain D2 of transistor M2 is electrically coupled to the body contact 408 of charge transfer transistor M1, and the drain D3 of transistor M3 is electrically coupled to the body contact 416 of charge transfer transistor M1. The body contact 416 is electrically coupled to P-well 404 and deep N-well 402. When the voltage level at the source S1 is greater than the voltage level at the drain D1 (for example, the voltage difference between S1 and D1 increases to above the threshold value), transistor M2 is turned on (transistor M3 is turned off), and the voltage at the body contact 408 is forced to reach the voltage level at the source S2 of transistor M2, which is also the drain D1 of charge transfer transistor M1 (collectively referred to as the first terminal 412 of charge transfer switch 400). When the voltage level at the drain D1 is greater than the voltage level at the source S1 (for example, the voltage difference between S1 and D1 decreases to below the threshold value), transistor M2 is turned off and transistor M3 is turned on, and transistor M3 forces the voltage at the main contact 408 to reach the voltage level at the source S3 of transistor M2, which is also the source S1 of charge transfer transistor M1 and is collectively referred to as the second terminal 410 of charge transfer switch 400.

[0045] In a particular non-limiting embodiment depicted by FIG3, the PMOS charge transfer switches 316 and 318 of the charge pump unit 300 do not include circuitry for increasing latch-up immunity. As discussed with respect to FIG5 and 6, in one or more embodiments, the charge pump unit may include PMOS charge transfer switches configured to increase latch-up immunity.

[0046] Figure 5 is a diagram depicting a charge pump unit 500 that can exhibit improved latch-up immunity according to one or more embodiments. The charge pump unit 500 includes cross-coupled charge transfer switches 506 and 508 (such as, but not limited to, charge transfer switches 302 and 304 of Figure 3) electrically coupled to an NMOS variant of the input node 510 of the charge pump unit 500, and cross-coupled charge transfer switches 502 and 504 electrically coupled to a PMOS variant of the output node 512 of the charge pump unit 500. Charge transfer switches 502 and 504 may be referred to herein as "first charge transfer switch 502" and "second charge transfer switch 504," respectively.

[0047] Pump signals CLKP and CLKN can be provided by digital circuitry configured to provide two oscillating signals with the same frequency but phase-shifted by 180° relative to each other. The operating frequencies (or frequency ranges) of the disclosed charge transfer switches, charge pump units, and charge pumps can be at least partially based on the capacitance of a pump capacitor to which a pump signal is applied (e.g., but not limited to, at charge pump unit 300 or charge pump unit 500). Typically, the magnitude of the frequency of the pump signal that sufficiently charges the pump capacitor has an inverse relationship with the magnitude of the capacitance of the pump capacitor. As a non-limiting embodiment, for a smaller capacitor (e.g., but not limited to, on-chip capacitors, the charge pump is typically about 1 pF to about 100 pF), charge transfer switches 502, 504, 506, and 508 (and charge transfer switches 302 and 304) can operate at least up to 40 MHz, and charge pump unit 500 (and charge pump unit 300) supports pump signals CLKP and CLKN frequencies of at least 40 MHz. Furthermore, the higher the frequency of the pump signal, the lower the voltage ripple exhibited by the output voltage VOUT, which may be desirable in some applications. Therefore, in one or more embodiments, the operating frequency (or frequency range) of the disclosed charge transfer switch, charge pump unit, and charge pump may be at least partially based on (as a supplement or replacement for) the desired value (or range) of the voltage ripple exhibited by the output voltage VOUT. For large-capacitance pump capacitors (e.g., capacitors that are not reasonably fitted onto the chip, typically greater than about 100 pF), the pump capacitor is typically located off-chip. The use of large-capacitance pump capacitors reduces the frequency at which the charge transfer switch can operate and the frequency of the supported pump signal compared to small-capacitance pump capacitors.

[0048] Charge transfer switches 502 and 504 each include three PMOS transistors configured (i.e., electrically coupled via their respective terminals, as depicted in Figure 5) as a single PMOS charge transfer switch. Both charge transfer switches 502 and 504 include a PMOS charge transfer transistor M4 (referred to herein as "charge transfer transistor M4", and more generally as "first transistor") assisted by circuit 518, which includes a configuration of two PMOS transistors M5 and M6 (referred herein as "transistor M5" and "transistor M6", and more generally as "second transistor" and "third transistor"). For simplicity, transistors M4, M5, and M6 are depicted only relative to charge transfer switch 502.

[0049] Typically, during the operation of the charge transfer switch 502, a shielding voltage VSH is applied to the main contact 516 of the charge transfer transistor M4 (e.g., a conductive structure comprising a conductive material electrically coupled to the N-well 602 of the CMOS structure 606 on which the charge transfer transistor M4 is disposed, as depicted in FIG6) to suppress the generation of leakage current (e.g., but not limited to, as discussed above by making a PN diode or BJT conductive to the N-well 602 or the P-substrate 604 during energization).

[0050] Figure 6 is a schematic diagram depicting a charge transfer switch 600 according to one or more embodiments, and the charge transfer switch is a non-limiting embodiment of the charge transfer switch 502 or 504 depicted in Figure 5.

[0051] More specifically, and turning back to Figure 5, circuit 518 is typically configured to apply the higher of the voltage level exhibited at the second terminal (e.g., the drain D4 of the charge transfer transistor M4 electrically coupled to the internal node 514 of the charge pump unit 500, which exhibits a voltage level ranging from about 0V to about (S+1)*VIN) and the voltage level exhibited at the first terminal (e.g., the source S4 of the charge transfer transistor M4 electrically coupled to the output node 512, which slopes from about 0V to about (S+1)*VIN) to force the body contact 608 and N-well 602 of the CMOS structure 606 to exhibit the highest voltage level at the charge pump unit (e.g., charge pump unit 500).

[0052] Transistor M5 is configured in circuit 518 to be turned on at least partially in response to a voltage level at the drain D4 ("second terminal 612", which is also the source S5 of transistor M5) of PMOS charge transfer transistor M4 being higher than the voltage level at the source S4 ("first terminal 610", which is electrically coupled to the gate of transistor M5), and to be turned off at least partially in response to a voltage level at the drain D4 of PMOS charge transfer transistor M4 being lower than the voltage level at the source S4 of PMOS charge transfer transistor M4. Transistor M6 is configured in circuit 518 to be turned on at least partially in response to a voltage level at the source S4 ("first terminal 610", which is also the source S6 of transistor M4) being higher than the voltage level at the drain D4 ("second terminal 612", which is electrically coupled to the gate of transistor M6) of PMOS charge transfer transistor M4, and to be turned off at least partially in response to a voltage level at the source S4 of PMOS charge transfer transistor M4 being lower than the voltage level at the drain D4 of PMOS charge transfer transistor M4.

[0053] The configuration of charge transfer switch 600, and more specifically circuit 518, will continuously apply the highest voltage level between the source S4 and drain D4 to the body contact 608 and N-well 602 of CMOS structure 606, provided that all three PMOS transistors M4, M5, and M6 are configured. The PN diode (where N-well 602 is the cathode and the P-S4 or P-D4 junction is the anode, as discussed above) has no opportunity to conduct (i.e., if it existed, it is discontinuous). Therefore, no leakage current (i.e., if it existed, it is discontinuous) flows to N-well 602, and thus the latch-up risk in the PMOS charge transfer transistors of charge transfer switches 502 and 504 of charge pump unit 500 is reduced.

[0054] Figure 7A is a flowchart depicting a process 700a of a first transistor (e.g., but not limited to, an NMOS or PMOS charge transfer transistor) for operating a charge transfer switch during energization of a charge pump unit or more generally a charge pump, according to one or more embodiments. As a non-limiting embodiment, the operation of Figure 7A may be performed by circuit 320 of Figure 3 or circuit 508 of Figure 5.

[0055] At operation 702, process 700a provides an input voltage to the input node of the charge pump unit. The charge pump unit may include a first transistor (e.g., but not limited to, an NMOS or PMOS charge transfer transistor) disposed at the CMOS structure.

[0056] At operation 704, process 700a applies a shielding voltage to the body contact of the first transistor in response to the relationship between the voltage at the first terminal of the first transistor (e.g., but not limited to, the drain of an NMOS charge transfer transistor or the source of a PMOS charge transfer transistor) and the voltage at the second terminal of the first transistor (e.g., but not limited to, the source of an NMOS charge transfer transistor or the drain of a PMOS charge transfer transistor). When the first transistor is an NMOS charge transfer transistor, the body contact is electrically coupled to the P-well of the NMOS transistor. When the first transistor is a PMOS charge transfer transistor, the body contact is electrically coupled to the N-well of the PMOS transistor.

[0057] Figure 7B is a flowchart depicting a process 700b for applying voltage to the body contact of a transistor of a charge transfer switch in a charge pump unit according to one or more embodiments. As a non-limiting embodiment, the operation of Figure 7A can be performed by circuit 320 of Figure 3 or circuit 508 of Figure 5.

[0058] At operation 706, process 700b responds to a first relationship between the voltage at the first terminal of the first transistor (e.g., but not limited to, the drain of an NMOS charge transfer transistor or the source of a PMOS charge transfer transistor) and the voltage at the second terminal of the first transistor (e.g., but not limited to, the source of an NMOS charge transfer transistor or the drain of a PMOS charge transfer transistor) by applying a shielding voltage exhibiting a first voltage level to the body contact of the first transistor (e.g., but not limited to, an NMOS or PMOS charge transfer transistor).

[0059] At operation 708, process 700b responds to a second relationship between the voltage at the first terminal of the first transistor (e.g., but not limited to, the drain of an NMOS charge-transfer transistor or the source of a PMOS charge-transfer transistor) and the voltage at the second terminal of the charge-transfer transistor (e.g., but not limited to, the source of an NMOS charge-transfer transistor or the drain of a PMOS charge-transfer transistor) by applying a shielding voltage exhibiting a second voltage level to the body contact of the first transistor (e.g., but not limited to, an NMOS or PMOS charge-transfer transistor). In one or more embodiments, the second relationship differs from the first relationship and may be the opposite of the first relationship.

[0060] In one or more embodiments, in an NMOS charge transfer transistor embodiment, the first terminal may be selectively electrically coupled to the interior of a charge pump unit or its output node (e.g., but not limited to, a boost node) or its output contact, and the second terminal may be selectively electrically coupled to the charge pump unit or its input node. In one or more embodiments, in a PMOS charge transfer transistor embodiment, the first terminal may be selectively electrically coupled to the charge pump unit or its output node, and the second terminal may be selectively electrically coupled to an internal node of the charge pump unit (e.g., but not limited to, a boost node).

[0061] Figures 7C and 7D are flowcharts depicting processes 700c and 700d, respectively, for observing the first and second relationships of process 700b in the case of an NMOS or PMOS charge transfer transistor according to one or more embodiments. The operation of Figure 7C can be performed by circuit 320 of Figure 3 as a non-limiting embodiment, and the operation of Figure 7D can be performed by circuit 508 of Figure 5 as a non-limiting embodiment.

[0062] In one or more embodiments where the first transistor in process 700b is an NMOS charge transfer transistor (e.g., but not limited to, the charge transfer transistor M1 of FIG3 or FIG4), process 700c is a process according to one or more embodiments for applying a shielding voltage that represents the lower of a voltage level represented by the voltage at the first terminal and a voltage level represented by the voltage at the second terminal.

[0063] At operation 710, process 700c observes a first relationship in response to the voltage level exhibited by the voltage at the first terminal of the NMOS charge transfer transistor (which may be selectively electrically coupled to an internal node of the charge pump unit (e.g., but not limited to, a boost node)) being lower than the voltage level exhibited by the voltage at the second terminal of the NMOS charge transfer transistor (which may be selectively electrically coupled to the input node of the charge pump unit). During at least the initial duration of energization of the charge pump unit (i.e., the ramp-up period discussed above), the lower of these voltages is the voltage at the internal node, and the higher voltage is at the input node, and process 700c applies the voltage level at the internal node to the body contact of the NMOS charge transfer transistor.

[0064] At operation 712, process 700c observes a second relationship in response to the voltage level exhibited by the voltage at the second terminal of the NMOS charge transfer transistor (which may be selectively electrically coupled to the input node of the charge pump unit) being lower than the voltage level exhibited by the voltage at the first terminal of the NMOS charge transfer transistor (which may be selectively electrically coupled to the internal nodes of the charge pump unit (e.g., but not limited to, boost nodes)). After a ramp-up cycle, the voltage level at such internal nodes increases (i.e., ramps up) in response to the application of the pump signal, and when the voltage level at the input node is lower than the voltage level at the internal nodes, process 700c applies the voltage level at the input node to the body contact of the NMOS charge transfer transistor.

[0065] In one or more embodiments where the first transistor in process 700b is a PMOS charge transfer transistor (e.g., but not limited to, the charge transfer transistor M4 of FIG5 or FIG6), process 700d is a process according to one or more embodiments for applying a shielding voltage that represents the higher of a voltage level represented by the voltage at the first terminal and a voltage level represented by the voltage at the second terminal.

[0066] At operation 714, process 700d observes a first relationship in response to the voltage level exhibited by the voltage at the second terminal of the PMOS charge transfer transistor (which may be selectively electrically coupled to an internal node of the charge pump unit (e.g., but not limited to, a boost node)) being higher than the voltage level exhibited by the voltage at the first terminal of the PMOS charge transfer transistor (which may be selectively electrically coupled to an output node of the charge pump unit). During at least the initial duration of energization of the charge pump unit (i.e., the ramp-up period as discussed above), the higher of these voltages is the voltage at the internal node of the charge pump unit, and process 700b applies the voltage level at the internal node to the body contact of the PMOS charge transfer transistor.

[0067] At operation 716, process 700d observes a second relationship in response to a voltage level represented by the voltage at the first terminal of the PMOS charge transfer transistor (selectively electrically coupled to the output node of the charge pump unit) being higher than the voltage level represented by the voltage at the second terminal of the PMOS charge transfer transistor (selectively electrically coupled to an internal node of the charge pump unit (e.g., but not limited to, a boost node)). When the voltage level represented by the voltage at the output node is higher than the voltage level represented by the voltage at the internal node of the charge pump unit, process 700b applies the voltage level at the output node to the body contact of the PMOS charge transfer transistor.

[0068] It is noteworthy that, in one or more embodiments, the operation of processes 700a to 700d can be performed at both the NMOS and PMOS charge transfer transistors of the charge pump unit (e.g., the NMOS charge transfer transistor M1 of Figures 3 and 4 and the PMOS charge transfer transistor M4 of Figures 5 and 6, respectively) during the energization of the charge pump unit, as discussed herein.

[0069] In some applications of the disclosed charge pump unit and the charge pumps therein, the load at the output node of the charge pump unit (e.g., a transient load current or a change in load current caused by the load) can cause the output voltage Vout to unreliably exhibit a voltage level of (S+1)*VIN. One or more embodiments are generally related to a charge pump unit having an regulated output voltage.

[0070] Figure 8 is a diagram depicting a charge pump unit circuit 800 with an regulated output voltage according to one or more embodiments. The charge pump unit circuit 800 includes a charge pump unit 802 (e.g., but not limited to, charge pump unit 300 or 500) and a control loop 816 configured to control the voltage level represented by the output voltage VOUT. In a particular non-limiting embodiment depicted in Figure 8, the control loop 816 includes a resistive voltage divider 808, a comparator 804, and a gate 806 (also referred to herein as "gate 806") configured in a negative feedback loop 814 between the output node 812 and the respective inputs (delay circuitry for phase shifting CLKP or CLKN, as applicable, not depicted) to the pump signals CLKP and CLKN at the charge pump unit 802.

[0071] Generally, the negative feedback loop 814 is configured to regulate the output voltage Vout to a reliably constant voltage level expressed as VREF*(R1+R2) / R2, where R1 and R2 represent the individual resistances of the resistors in the resistive voltage divider 808. Therefore, the relationship between the voltage level of the output voltage Vout and the input voltage Vin at input node 810 is at least partially based on a predetermined voltage level of the reference voltage VREF and predetermined individual resistances R1 and R2, and is unaffected by the load current at output node 812. By means of a non-limiting embodiment where resistors R1 and R2 are set to the same value, in response to 1 / 2 VOUT(N-1) (VOUT(N-1) is used herein to indicate that the voltage output VOUT provided to the control loop 816 is below VREF), comparator 804 is configured to output logic "1". Gate 806 is configured as a Boolean AND operator. When gate 806 receives logic "1" from comparator 804, the waveform at its output will substantially track the waveform of the oscillation signal CLK, which is the signal source of the pump signals CLKN and CLKP at charge pump unit 802. As a non-limiting embodiment, it is a square wave generated by the clock pulse source of the digital circuit. In one or more embodiments, the oscillation signal CLK may exhibit a frequency at least partially based on the desired frequencies of the pump signals CLKN and CLKP as discussed above. As a non-limiting embodiment, the oscillation signal CLK may exhibit a frequency substantially the same as or a multiple of the frequencies of CLKN and CLKP.

[0072] When 1 / 2 VOUT(N-1) is below VREF, the signal sources for pump signals CLKP and CLKN are effectively turned on, and the pump signals are supplied to the charge pump unit 802. In one or more embodiments, the waveforms of pump signals CLKP and CLKN track the waveform of CLK in terms of frequency, and the waveform of one of CLKP and CLKN may be substantially in phase with CLK, and the waveform of the other of CLKP and CLKN is substantially phase-shifted by 180° with the waveform of CLK.

[0073] The phase and frequency relationship between CLKP / CLKN and CLK can vary according to the embodiments discussed herein without departing from the scope of this invention. For example, in some implementations, the individual waveforms of CLKN and CLKP may exhibit frequencies derived from the frequency of CLK (e.g., but not limited to, via a frequency divider), or one waveform of CLKN or CLKP may be phase-shifted from the phase of CLK, and the other waveform of CLKN and CLKP may be substantially phase-shifted by 180° from it.

[0074] In response to 1 / 2 VOUT(N-1) exceeding VREF, comparator 804 is configured to output logic "0". When gate 806 receives logic "0" from comparator 805, its output waveform will be a non-oscillating logic "0". When 1 / 2 VOUT(N-1) is equal to or exceeds VREF, pump signals CLKP and CLKN are effectively disconnected, and no signal source is supplied to charge pump unit 802. When the pump signals are disconnected, charge pump unit 802 does not raise VIN to supply charge to output node 812, and the voltage level of output voltage VOUT decreases as VOUT is pulled down by load current (load current not depicted). When 1 / 2 VOUT(N-1) drops below VREF, comparator 804 generates an output "1" that effectively turns on pump signals CLKN and CLKP, and charge pump unit 802 supplies charge to output node 812, thus increasing the voltage level of output voltage VOUT. When operating periodically using an on / off switch, the average 1 / 2 VOUT(N-1) is substantially equal to VREF, and the output voltage VOUT is adjusted to the desired voltage level for the output voltage, thus achieving equilibrium.

[0075] Those skilled in the art will understand that many topologies are available for the charge pump unit and charge pump disclosed, which have regulated output.

[0076] Figures 9 and 10 are schematic diagrams depicting the topology of an embodiment for adjusting the voltage output of a charge pump and a charge pump unit according to one or more embodiments.

[0077] In the embodiment topology depicted in FIG9, one to N charge pump units 902, 904, and 906 of charge pump 900 (e.g., but not limited to, each charge pump unit 300 or 500) are controlled by negative feedback circuit 908 (e.g., but not limited to, negative feedback circuit 814) to regulate the voltage output VOUT of charge pump 900. Although FIG9 depicts the control actions performed at each of the one to N charge pump units 902, 904, and 906, in one or more embodiments, negative feedback circuit 908 may be configured or configured to perform control actions at any number (from 1 to a total of N) of charge pump units 902, 904, and 906 (e.g., but not limited to, at least one of the charge pump units).

[0078] In the embodiment topology depicted in FIG10, one to N charge pump units 1002, 1004, and 1006 of charge pump 1000 are individually controlled by one to N negative feedback loops 1008, 1010, and 1012 to regulate the individual voltage outputs of the one to N charge pump units 1002, 1004, and 1006. It is noteworthy that in the topology depicted in FIG10, multiple regulated output voltages can be obtained at the voltage outputs of the individual one to N charge pump units 1002, 1004, and 1006 at substantially the same time.

[0079] Figure 11 is a block diagram of circuit system 1100, which in some embodiments can be used to implement the various functions, operations, actions, processes, and / or methods disclosed herein. Circuit system 1100 includes one or more processors (sometimes referred to herein as "processor 1102") operatively coupled to one or more data storage devices (sometimes referred to herein as "memory 1104"). Memory 1104 includes machine-executable code 1106 stored thereon, and processor 1102 includes logic circuit system 1108. Machine-executable code 1106 includes information describing functional elements that can be implemented (e.g., executed) by logic circuit system 1108. Logic circuit system 1108 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 1106. Circuit system 1100, when executing the functional elements described by machine-executable code 1106, should be considered as special-purpose hardware configured to perform the functional elements disclosed herein. In some embodiments, the processor 1102 may be configured to execute functional elements described by machine executable code 1106 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel processing streams.

[0080] When implemented by the logic circuitry 1108 of processor 1102, machine-executable code 1106 is configured to adapt processor 1102 to perform the operations of the embodiments disclosed herein. For example, machine-executable code 1106 may be configured to adapt processor 1102 to perform at least some or all of the blocks and processes depicted in Figures 3 through 10. As another embodiment, machine-executable code 1106 may be configured to adapt processor 1102 to perform at least some or all of the operations discussed for the disclosed charge transfer switch, charge pump unit, or charge pump.

[0081] As a specific, non-limiting embodiment, machine-executable code 1106 may be configured to adapt processor 1102 to perform processes (including, but not limited to, processes 700a to 700d) for operating the disclosed charge transfer switch, charge pump unit, or charge pump.

[0082] Processor 1102 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer, and the general-purpose computer is configured to perform functional elements corresponding to machine-executable code 1106 (e.g., software code, firmware code, hardware description) associated with embodiments of the present invention. It should be noted that the general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in alternative embodiments, processor 1102 may be any known processor, controller, microcontroller, or state machine. The processor 1102 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0083] In some embodiments, memory 1104 includes volatile data storage (e.g., random access memory (RAM)) and non-volatile data storage (e.g., but not limited to, flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM)). In various embodiments, processor 1102 and memory 1104 may be implemented in a single device (e.g., but not limited to, a semiconductor device product, a system-on-a-chip (SOC), or a system base chip). In various embodiments, processor 1102 and memory 1104 may be implemented in a separate device.

[0084] In various embodiments, the machine-executable code 1106 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting embodiment, the computer-readable instructions may be stored in storage 1104, directly accessed by processor 1102, and executed by processor 1102 using at least logic circuitry system 1108. Also as a non-limiting embodiment, the computer-readable instructions may be stored in storage 1104, transferred to a memory device (not shown) for execution, and executed by processor 1102 using at least logic circuitry system 1108. Therefore, in various embodiments, logic circuitry system 1108 includes electrically configurable logic circuitry system 1108.

[0085] In various embodiments, machine-executable code 1106 may describe the hardware (e.g., circuitry) to be implemented in logic circuitry system 1108 to perform functional elements. This hardware may be described at any of a range of abstraction levels, from low-level transistor layout to high-level description languages. At high abstraction levels, a hardware description language (HDL) such as the IEEE Standard Hardware Description Language (HDL) may be used. As a non-limiting embodiment, Verilog™, SystemVerilog™, or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL™) may be used.

[0086] As needed, HDL descriptions can be converted into descriptions at any of many other levels of abstraction. As a non-limiting embodiment, a high-level description can be converted into a logic-level description, such as Register Transfer Language (RTL), Gate Level (GL) description, Placement Level description, or Mask Level description. As a non-limiting embodiment, micro-operations to be performed by the hardware logic circuitry (e.g., but not limited to, gates, flip-flops, registers) of logic circuitry system 1108 can be described in RTL and then converted into a GL description using a synthesis tool. The GL description can then be converted into a placement-level description corresponding to the physical layout of integrated circuitry of programmable logic devices, discrete gate or transistor logic, discrete hardware components, or combinations thereof using placement and routing tools. Therefore, in various embodiments, machine-executable code 1106 can include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0087] In embodiments where machine executable code 1106 includes a hardware description (at any level of abstraction), a system (not shown, but including memory 1104) can be configured to implement the hardware description described by machine executable code 1106. As a non-limiting embodiment, processor 1102 may include programmable logic devices (e.g., FPGA or PLC), and logic circuitry system 1108 may be electrically controlled to implement circuitry corresponding to the hardware description in logic circuitry system 1108. Also as a non-limiting embodiment, logic circuitry system 1108 may include hard-wired logic manufactured by a manufacturing system (not shown, but including memory 1104) according to the hardware description of machine executable code 1106.

[0088] Regardless of whether the machine executable code 1106 includes computer-readable instructions or a hardware description, the logic circuit 1108 is adapted to execute the functional elements described by the machine executable code 1106 when implementing the functional elements of the machine executable code 1106. It should be noted that although the hardware description may not directly describe the functional elements, it indirectly describes the functional elements that the hardware elements described by the hardware description can execute.

[0089] Those skilled in the art will appreciate the many advantages and benefits of the various embodiments of the charge pump unit disclosed herein. As a non-limiting embodiment: (1) When the emitter (P-well) and base (deep N-well) are coupled to exhibit the same voltage level, the parasitic PNP BJT never (i.e., if it exists, it is discontinuous) turns on at the charge transfer switch disclosed in the NMOS variant. Although it forces the deep N-well to exhibit the lowest voltage level of the charge pump unit, the parasitic PNP BJT has no chance of turning on when the voltage levels at its emitter and base are the same. Therefore, no leakage current is injected into the P-substrate of the disclosed charge transfer switch via the parasitic PNP BJT. (2) Well P is set to the lowest voltage level by voltage selector (configuration of M2 and M3). In Well P, the diode at the anode cannot conduct because the voltage at its anode is always lower than the voltage at its cathode (N region of drain D1). Therefore, no leakage current (i.e., discontinuous quantity (if present)) flows through Well P.

[0090] Any representation of something as "typical," "common," "known," etc., in this description does not necessarily mean that its manner of disclosure or discussion in the prior art is known in the prior art. Nor does it necessarily mean that the thing is generally known, readily understood, or routinely used in the relevant field. It only means that it is known or understood by the inventor of this invention.

[0091] As used in this invention, the term "combination" in relation to a plurality of elements can include any combination of all elements or any of a variety of different sub-combinations of some of those elements. For example, the phrase "A, B, C, D or a combination thereof" can refer to any one of A, B, C or D; a combination of each of A, B, C and D; and any sub-combination of A, B, C or D, such as A, B and C; A, B and D; A, C and D; B, C and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0092] The terminology used in this invention and particularly in the appended claims (e.g., but not limited to, the context of the appended claims) is generally intended to be "open-ended" (e.g., but not limited to, the term "including" should be interpreted as "including but not limited to", the term "having" should be interpreted as "at least having", and the term "includes" should be interpreted as "including but not limited to"). As used herein, the term "each" means some or a whole. As used herein, the term "each" means a whole.

[0093] Furthermore, if a specific number of introduced claim statements are intended, this intention will be explicitly stated in the claim statement, and this intention will not exist without such a statement. For example, to aid understanding, the appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce the description of a technical solution. However, the use of such phrases should not be construed as implying that the introduction of the indefinite article "a / an" into the description of a technical solution will limit any particular technical solution containing such introduced technical solution descriptions to an embodiment containing only one such description, even when the same technical solution includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" (e.g., but not limited to, "a" should be interpreted as meaning "at least one" or "one or more"); the same applies to the use of definite articles used to introduce the description of a technical solution. As used herein, the term "each" means some or a total, and the term "each" means a total.

[0094] Furthermore, even when a specific number of the introduced claims are explicitly stated, those skilled in the art will recognize that such statements should generally be interpreted as meaning at least the number stated (e.g., but not limited to, an unmodified statement without other modifiers, "two statements," means at least two statements or two or more statements). Moreover, when using rules such as "at least one of A, B, and C, but not limited to" or "one or more of A, B, and C, but not limited to," this construction is generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc.

[0095] Furthermore, any separate words or phrases presenting two or more alternative terms in this specification, the claims, or the drawings should be understood to encompass the possibility of including one of such terms, any one of such terms, or both of such terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0096] Various embodiments of the non-limiting embodiments of the present invention include: Example 1: An apparatus comprising: a CMOS structure; a first transistor disposed on the CMOS structure; and a circuit configured to apply a shielding voltage to a body contact of the first transistor in response at least partially to a relationship between a voltage at a first terminal of the first transistor and a voltage at a second terminal of the first transistor. Example 2: The device as in Example 1, wherein the circuit is configured to apply the shielding voltage, which is the lower of a voltage level represented by the voltage at the first terminal and a voltage level represented by the voltage at the second terminal. Example 3: The device as described in any one of Examples 1 and 2, wherein the circuit includes a second transistor disposed at the CMOS structure and a third transistor disposed at the CMOS structure. Example 4: The apparatus of any one of Examples 1 to 3, wherein the second transistor is configured to at least partially turn on in response to a voltage at the second terminal that presents a higher voltage level than the voltage at the first terminal, and to at least partially turn off in response to a voltage at the first terminal that presents a higher voltage level than the voltage at the second terminal. Example 5: The apparatus of any one of Examples 1 to 4, wherein the third transistor is configured to be turned on at least partially in response to the voltage at the first terminal, which presents a higher voltage level than the voltage at the second terminal, and to be turned off at least partially in response to the voltage at the second terminal, which presents a higher voltage level than the voltage at the first terminal. Example 6: The apparatus of any one of Examples 1 to 5, wherein the first terminal and the second terminal of the first transistor are respectively a drain and a source of the first transistor. Example 7: The device as described in any one of Examples 1 to 6, wherein one drain of the second transistor is electrically coupled to the body contact of the first transistor, and one gate of the second transistor is electrically coupled to the source of the first transistor. Example 8: The device as described in any one of Examples 1 to 7, wherein one drain of the third transistor is electrically coupled to the main contact of the first transistor, and one gate of the third transistor is electrically coupled to the drain of the first transistor. Example 9: An apparatus as described in any one of Examples 1 to 8, wherein the second transistor is configured to at least partially turn on in response to a voltage at the second terminal that presents a higher voltage level than the voltage at the first terminal, and to at least partially turn off in response to a voltage at the first terminal that presents a higher voltage level than the voltage at the second terminal. Example 10: An apparatus as described in any one of Examples 1 to 9, wherein the third transistor is configured to at least partially turn on in response to a voltage at the first terminal that presents a higher voltage level than the voltage at the second terminal, and to at least partially turn off in response to a voltage at the second terminal that presents a higher voltage level than the voltage at the first terminal. Example 11: The device of any one of Examples 1 to 10, wherein the CMOS structure includes an N-well and a P-substrate, and the body contact is electrically coupled to the N-well. Example 12: The device of any one of Examples 1 to 11, wherein the CMOS structure includes a P-well, a deep N-well and a P-substrate, and the main contact is electrically coupled to the P-well and the deep N-well. Example 13: An apparatus as described in any one of Examples 1 to 12, wherein the circuit is configured to apply the shielding voltage, the shielding voltage being the higher of a voltage level represented by the voltage at the first terminal and a voltage level represented by the voltage at the second terminal. Example 14: A method comprising: providing an input voltage to an input node of a charge pump unit; and applying a shielding voltage to a body contact of a charge transfer transistor in at least part of a relationship between a voltage at a first terminal of a charge transfer transistor and a voltage at a second terminal of the charge transfer transistor. Example 15: The method of Example 14 includes: applying a shielding voltage exhibiting a first voltage level to the body contact of the charge transfer transistor in at least part response to a first relationship between the voltage at the first terminal of the charge transfer transistor and the voltage at the second terminal of the charge transfer transistor; and applying a shielding voltage exhibiting a second voltage level to the body contact of the charge transfer transistor in at least part response to a second relationship between the voltage at the first terminal of the charge transfer transistor electrically coupled to the input node of the charge pump unit and the voltage at the second terminal of the charge transfer transistor electrically coupled to the internal node of the charge pump unit, wherein the first terminal of the charge transfer transistor is electrically coupled to an internal node of the charge pump unit, and wherein the second terminal of the charge transfer transistor is electrically coupled to the input node of the charge pump unit. Example 16: A method as described in any of Examples 14 and 15, comprising: observing the first relationship in at least a partial response to a voltage level represented by the voltage at the first terminal of the charge pump unit being lower than a voltage level represented by the voltage at the second terminal of the charge pump unit. Example 17: A method as described in any of Examples 14 to 16, comprising: observing the second relationship in at least a partial response to a voltage level represented by the voltage at the second terminal of the charge pump unit being lower than a voltage level represented by the voltage at the first terminal of the charge pump unit. Example 18: A method according to any one of Examples 14 to 17, the method comprising: applying a shielding voltage exhibiting a first voltage level to the body contact of the charge transfer transistor in at least part of a first relationship between a voltage at the first terminal of the charge transfer transistor and a voltage at the second terminal of the charge transfer transistor; and applying a shielding voltage exhibiting a second voltage level to the body contact of the charge transfer transistor in at least part of a second relationship between the voltage at the first terminal of the charge transfer transistor electrically coupled to the output node of the charge pump unit and the voltage at the second terminal of the charge transfer transistor electrically coupled to the internal node of the charge pump unit, wherein the first terminal of the charge transfer transistor is electrically coupled to an output node of the charge pump unit, and wherein the second terminal of the charge transfer transistor is electrically coupled to an internal node of the charge pump unit. Example 19: A method as described in any of Examples 14 to 18, comprising: observing the first relationship in at least a partial response to a voltage level represented by the voltage at the second terminal of the charge pump unit being higher than a voltage level represented by the voltage at the first terminal of the charge pump unit. Example 20: A method as described in any one of Examples 14 to 19, comprising: observing the second relationship in at least a partial response to a voltage level represented by the voltage at the first terminal of the charge pump unit being higher than a voltage level represented by the voltage at the second terminal of the charge pump unit. Example 21: An apparatus comprising: a charge pump; and a control loop configured to adjust an output voltage of the charge pump, wherein the charge pump includes at least one charge transfer switch, the at least one charge transfer switch comprising: a CMOS structure; a first transistor disposed at the CMOS structure; and a circuit configured to apply a voltage to a body contact of the first transistor in response to a relationship between a voltage at a first terminal of the first transistor and a voltage at a second terminal of the first transistor. Example 22: The apparatus of Example 21, wherein the control loop includes a negative feedback loop configured to adjust the output voltage of the charge pump by controlling a pump signal, and the charge pump is configured to operate in response to the pump signal. Example 23: An apparatus as described in any of Examples 21 and 22, wherein the charge pump includes at least one charge pump unit, and the control loop is configured to adjust the output voltage of the at least one charge pump unit by controlling a pump signal, the at least one charge pump unit being configured to operate in response to the pump signal. Example 24: An apparatus as described in any of Examples 21 to 23, wherein the control loop is configured to control the pump signal in at least a partial response to the output voltage observed by one of the at least one charge pump units. Example 25: An apparatus as described in any of Examples 21 to 24, wherein the control loop is configured to control the pump signal in at least a partial response to an observed output voltage of one of the charge pumps. Example 26: An apparatus as described in any one of Examples 21 to 25, wherein the charge pump comprises two or more charge pump units, and the control loop comprises two or more negative feedback loops, the negative feedback loops being individually configured to adjust the individual output voltage of the two or more charge pump units by means of a control pump signal, the two or more charge pump units being configured to operate in response to the pump signals. Example 27: An apparatus as described in any of Examples 21 to 26, wherein the control loop is configured to control the pump signal in at least a partial response to the state of the output voltage of each of the two or more charge pump units.

[0097] The features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and arrangements without departing from the scope of this invention, even if such combinations or arrangements are not explicitly described herein. In fact, variations, modifications, and other implementations of the content described herein will occur to those skilled in the art without departing from the scope of this invention. Therefore, this invention is defined not only by the foregoing illustrative description but also by the appended claims and their legal equivalents.

[0098] 100: Charge Pump 102a-102c: Charge pump unit 104: Input Node 106: Output Node 108a-108c: Pump capacitors 110a-110c: Pump capacitor 112a-112c: Internal nodes 114a-114c: Charge transfer switch 116a-116c: Charge transfer switch 118a-118c: Internal nodes 200: NMOS charge transfer switch 202: Deep N Well 204:P Well 206:P substrate 208: Parasitic PNP bipolar junction transistor (BJT) 210: Parasitic PN Diode 212: Electrical coupling connector 214: CMOS Structure 300: Charge Pump Unit 302: First charge transfer switch 304: Second charge transfer switch 306: Input Node 308: Output Node 310: Internal Node 312: Main Contact Point 314: Internal Node 316: PMOS charge transfer switch 318: PMOS charge transfer switch 320: Circuit 400: Charge Transfer Switch 402: Deep N Well 404: P Well 406:P substrate 408: Main Contact Point 410: Second terminal 412: First terminal 414: CMOS Structure 416: Main Contact Point 500: Charge Pump Unit 502: Charge Transfer Switch 504: Charge Transfer Switch 506: Cross-coupled charge transfer switch 508: Cross-coupled charge transfer switch (circuit) 510: Input Node 512: Output Node 514: Internal Node 516: Main Contact Point 518: Circuit 600: Charge Transfer Switch 602:N well 604:P substrate 606: CMOS Structure 608: Main Contact Point 610: First terminal 612: Second terminal 700a: Process 700b: Process 700c: Process 700d: Process 702: Operation 704: Operation 706: Operation 708: Operation 710: Operation 712: Operation 714: Operation 716: Operation 800: Charge Pump Unit Circuit 802: Charge Pump Unit 804: Comparator 806: Gate 808: Resistive Voltage Divider 810: Input Node 812: Output Node 814: Negative Feedback Circuit 816: Control Loop 900: Charge Pump 902:N charge pump unit 904:N charge pump unit 906:N charge pump unit 908: Negative Feedback Circuit 1000: Charge Pump 1002:N charge pump unit 1004:N charge pump unit 1006:N charge pump unit 1008:N Negative Feedback Circuit 1010:N negative feedback loop 1012:N negative feedback loop 1100: Circuit System 1102: Processor 1104: Storage 1106: Machine-executable code 1108: Logic Circuit System 1108: Configurable Logic Circuit System

Claims

1. A charge pump device, comprising: a first transistor; and an output node electrically coupled to a first terminal of the first transistor, wherein, The output node is not grounded; a boost node coupled to the second terminal of the first transistor for transferring charge from the boost node via the first transistor to the output node; a circuit configured to apply a shielding voltage to the body contacts of the first transistor in at least a partial response to the relationship between the voltage at the first terminal of the first transistor and the voltage at the second terminal of the first transistor; an additional first transistor, wherein the ungrounded output node is electrically coupled to the first terminal of the additional first transistor; an additional boost node coupled to the second terminal of the additional first transistor for transferring charge from the additional boost node via the additional first transistor to the ungrounded output node; and an additional circuit configured to apply a shielding voltage to the body contacts of the additional first transistor in at least a partial response to the relationship between the voltage at the first terminal of the additional first transistor and the voltage at the second terminal of the additional first transistor, wherein the first transistor is coupled to alternately turn on or off in at least a partial response to the voltage of the additional boost node. The additional first transistor is coupled to alternately turn on or off in response at least partially to the voltage of the boost node.

2. The apparatus as claimed in claim 1, wherein, The circuit is used to apply a shielding voltage, which is the lower of the voltage level presented by the voltage at the first terminal of the first transistor and the voltage level presented by the voltage at the second terminal of the first transistor.

3. The apparatus as claimed in claim 1, wherein, The circuit includes a second transistor and a third transistor; and the additional circuit includes an additional second transistor and an additional third transistor.

4. The apparatus as claimed in claim 3, wherein, The second transistor is configured to turn on at least partially in response to a higher voltage level at the second terminal of the first transistor relative to the voltage level at the first terminal of the first transistor, and to turn off at least partially in response to a higher voltage level at the first terminal of the first transistor relative to the voltage level at the second terminal of the first transistor.

5. The apparatus as claimed in claim 3, wherein, The third transistor is configured to turn on at least partially in response to a higher voltage level at the first terminal of the first transistor relative to the voltage level at the second terminal of the first transistor, and to turn off at least partially in response to a higher voltage level at the second terminal of the first transistor relative to the voltage level at the first terminal of the first transistor.

6. The apparatus as claimed in claim 3, wherein, The first terminal and the second terminal of the first transistor are the drain and source of the first transistor, respectively.

7. The apparatus as claimed in claim 6, wherein, The drain of the second transistor is electrically coupled to the body contact of the first transistor, and the gate of the second transistor is electrically coupled to the source of the first transistor.

8. The apparatus as claimed in claim 3, wherein, The drain of the third transistor is electrically coupled to the body contact of the first transistor, and the gate of the third transistor is electrically coupled to the drain of the first transistor.

9. The apparatus as claimed in claim 3, wherein, The additional second transistor is configured to be turned on at least partially in response to a higher voltage level presented by the voltage at the second terminal of the additional first transistor relative to the voltage at the first terminal of the additional first transistor, and to be turned off at least partially in response to a higher voltage level presented by the voltage at the first terminal of the additional first transistor relative to the voltage at the second terminal of the additional first transistor.

10. The apparatus as claimed in claim 3, wherein, The additional third transistor is configured to be turned on at least partially in response to a higher voltage level presented by the voltage at the first terminal of the additional first transistor relative to the voltage at the second terminal of the additional first transistor, and to be turned off at least partially in response to a higher voltage level presented by the voltage at the second terminal of the additional first transistor relative to the voltage at the first terminal of the additional first transistor.

11. The apparatus of claim 1, wherein, The first transistor and the additional first transistor are disposed in a CMOS structure, and the CMOS structure includes an N-type well and a P-type substrate, and the main contact is electrically coupled to the N-type well.

12. The apparatus of claim 1, wherein, The circuit is used to apply a shielding voltage, which is the higher of the voltage level presented by the voltage at the first terminal of the first transistor and the voltage level presented by the voltage at the second terminal of the first transistor; and wherein the shielding voltage applied by the additional circuit is the higher of the voltage level presented by the voltage at the first terminal of the additional first transistor and the voltage level presented by the voltage at the second terminal of the additional first transistor.

13. A method of operating a charge pump device, comprising: applying a shielding voltage to a body contact of the charge transfer transistor, at least partially in response to a relationship between a voltage at a first terminal of the charge transfer transistor and a voltage at a second terminal of the charge transfer transistor, wherein, The first terminal of the charge transfer transistor is electrically coupled to a first boost node of a charge pump unit, and the second terminal of the charge transfer transistor is electrically coupled to an output node of the charge pump unit, the output node being ungrounded; a first boost charge is provided at the first boost node of the charge pump unit; a shielding voltage is applied to the body contacts of the additional charge transfer transistor in at least a partial response to the relationship between the voltage of the first terminal of the additional charge transfer transistor and the voltage of the second terminal of the additional charge transfer transistor, wherein the first terminal of the additional charge transfer transistor is electrically coupled to a second boost node of the charge pump unit, and the second terminal of the additional charge transfer transistor is electrically coupled to the ungrounded output node of the charge pump unit; a second boost charge is provided at the second boost node of the charge pump unit; the charge transfer transistor is switched on or off in at least a partial response to the voltage at the first terminal of the additional charge transfer transistor; and the additional charge transfer transistor is switched on or off in at least a partial response to the voltage at the first terminal of the additional charge transfer transistor.

14. The method of claim 13, comprising: applying a shielding voltage of a first voltage level to a body contact of the charge transfer transistor in at least part of a first relationship between the voltage at a first terminal of the charge transfer transistor and the voltage at a second terminal of the charge transfer transistor; and applying a shielding voltage of a second voltage level to a body contact of the charge transfer transistor in at least part of a second relationship between the voltage at the first terminal of the charge transfer transistor and the voltage at a second terminal of the charge transfer transistor electrically coupled to an internal node of the charge pump unit.

15. The method of claim 14, comprising: observing the first relationship in at least part of a response to a voltage level presented by the voltage at the first terminal of the charge pump unit being lower than a voltage level presented by the voltage at the second terminal of the charge pump unit.

16. The method of claim 14, comprising: observing the second relationship in at least part of a response to a voltage level presented by the voltage at the second terminal of the charge pump unit being lower than the voltage level presented by the voltage at the first terminal of the charge pump unit.

17. A charge pump device, comprising: a charge pump; and a control loop configured to regulate an output voltage of the charge pump, wherein, The charge pump includes at least one charge transfer switch, the charge transfer switch comprising: a first transistor; a first boost node coupled to a first terminal of the first transistor; an output node electrically coupled to a second terminal of the first transistor, the output node being ungrounded; a circuit configured to apply a shielding voltage to the body contacts of the first transistor in response to a relationship between the voltage at the first terminal of the first transistor and the voltage at the second terminal of the first transistor; an additional first transistor, wherein a second boost node is coupled to the first terminal of the additional first transistor, and the ungrounded output node is electrically coupled to the second terminal of the additional first transistor; and an additional circuit configured to apply a shielding voltage to the body contacts of the additional first transistor, at least partially in response to a relationship between the voltage at the first terminal of the additional first transistor and the voltage at the second terminal of the additional first transistor. The first transistor is coupled to alternately turn on or off in response at least partially to the voltage at the second boost node, and the additional first transistor is coupled to alternately turn on or off in response at least partially to the voltage at the first boost node.

18. The apparatus of claim 17, wherein, The control loop includes a negative feedback loop for regulating the output voltage of the charge pump based at least in part on a reference voltage and a resistive voltage divider.

19. The apparatus of claim 17, wherein, The charge pump includes at least one charge pump unit, wherein the control loop adjusts the output voltage of the at least one charge pump unit by controlling the respective inputs of a first pump signal and a second pump signal, and the at least one charge pump unit operates in response to the first pump signal and the second pump signal.

20. The apparatus of claim 19, wherein, The control loop responds at least in part to an observed output voltage of the at least one charge pump unit to control the pump signal.

21. The apparatus of claim 19, wherein, The control loop responds at least in part to an observed output voltage of the charge pump to control the first pump signal and the second pump signal.

22. The apparatus of claim 17, wherein, The charge pump includes two or more charge pump units, and the control loop includes two or more negative feedback loops, which are individually configured to adjust the respective output voltage of the two or more charge pump units by means of a control pump signal, and the two or more charge pump units are configured to operate in response to the pump signal.

23. The apparatus of claim 22, wherein, The control loop controls the pump signal in response at least in part to the state of the respective output voltages of the two or more charge pump units.

24. A charge pump device, comprising: a first transistor; an output node coupled to a first terminal of the first transistor; and a boost node coupled to a second terminal of the first transistor for transferring charge from the boost node to the output node via the first transistor, wherein... The first and second terminals of the first transistor are respectively the drain and source of the first transistor; a circuit configured to apply a shielding voltage to the body contacts of the first transistor in at least a partial response to the relationship between the voltage at the first terminal and the voltage at the second terminal of the first transistor, wherein the circuit includes a second transistor and a third transistor, and wherein the drain of the second transistor is electrically coupled to the body contacts of the first transistor, and the gate of the second transistor is electrically coupled to the source of the first transistor; an additional first transistor, wherein the output node is coupled to the first terminal of the additional first transistor; an additional boost node, coupled to the second terminal of the additional first transistor, for transferring charge from the additional boost node through the additional first transistor to the output node; and an additional circuit configured to apply a shielding voltage to the body contacts of the additional first transistor in at least a partial response to the relationship between the voltage at the first terminal and the voltage at the second terminal of the additional first transistor. The first transistor is coupled to alternately turn on or off in at least a portion of response to the voltage of the additional boost node.

25. A charge pump device comprising: a first transistor; an output node coupled to a first terminal of the first transistor; a boost node coupled to a second terminal of the first transistor for transferring charge from the boost node via the first transistor to the output node; and a circuit configured to apply a shielding voltage to a body contact of the first transistor, at least partially in response to a relationship between a voltage at the first terminal of the first transistor and a voltage at the second terminal of the first transistor, wherein... The circuit includes a second transistor and a third transistor, wherein the drain of the third transistor is electrically coupled to the body contact of the first transistor, and the gate of the third transistor is electrically coupled to the drain of the first transistor; an additional first transistor, wherein the output node is coupled to a first terminal of the additional first transistor; an additional boost node, coupled to a second terminal of the additional first transistor, for transferring charge from the additional boost node to the output node via the additional first transistor; and an additional circuit configured to apply a shielding voltage to the body contact of the additional first transistor in at least a partial response to the relationship between the voltage at the first terminal of the additional first transistor and the voltage at the second terminal of the additional first transistor, wherein the first transistor is coupled to alternately turn on or off in at least a partial response to the voltage of the additional boost node, wherein the additional first transistor is coupled to alternately turn on or off in at least a partial response to the voltage of the boost node.

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