Ramp generator and image sensing device

Abstract

A ramp signal generator includes a digital-to-analog converter, a first capacitor, a second capacitor, and a noise cancellation circuit. The digital-to-analog converter generates a ramp-up voltage signal at a first output and a ramp-down voltage signal at a second output. The first capacitor is coupled between the first output and an intermediate node. The second capacitor is coupled between the second output and the intermediate node. The noise cancellation circuit is coupled to the intermediate node. The noise cancellation circuit provides compensation feedback based on the intermediate voltage at the intermediate node.

Claims

1. A ramp signal generator, comprising: a digital-to-analog converter having a first output terminal and a second output terminal, and for generating a ramp-up voltage signal at the first output terminal and a ramp-down voltage signal at the second output terminal; a first capacitor coupled between the first output terminal and an intermediate node; a second capacitor coupled between the second output terminal and the intermediate node; and a noise cancellation circuit coupled to the intermediate node and for providing a compensation feedback based on an intermediate voltage at the intermediate node.

2. The ramp signal generator as claimed in claim 1, wherein the compensation feedback is correlated with an AC component of the intermediate voltage, the compensation feedback being used to compensate for an inherent noise of the digital-to-analog converter.

3. The ramp signal generator as claimed in claim 1, wherein the digital-to-analog converter includes a plurality of digital-to-analog conversion units, each of the plurality of digital-to-analog conversion units including a first current source, a first transistor, and a second transistor, wherein the first transistor of each of the plurality of digital-to-analog conversion units is controlled by a single bit code in a first digital code to generate the ramp-up voltage signal, and the second transistor of each of the plurality of digital-to-analog conversion units is controlled by a single bit code in a second digital code to generate the ramp-down voltage signal.

4. The ramp signal generator as claimed in claim 3, wherein the noise cancellation circuit comprises: a third transistor, wherein a drain terminal and a gate terminal of the third transistor are connected to a second current source to form a bias voltage; a switch coupled between the third transistor and the intermediate node; and a plurality of fourth transistors, wherein a plurality of gate terminals of the plurality of fourth transistors are commonly connected to the intermediate node, and a drain terminal of each of the plurality of fourth transistors is connected to the first current source of each of the plurality of digital-to-analog converters.

5. The ramp signal generator as claimed in claim 4, wherein the switch is configured to reset the DC level of the intermediate voltage at the intermediate node according to the bias voltage, and each of the plurality of fourth transistors is configured to form a shunt current to suppress an operating current of the digital-to-analog converter.

6. The ramp signal generator as claimed in claim 3, wherein the noise cancellation circuit comprises: a low-dropout regulator; a fifth transistor, wherein a drain terminal and a gate terminal of the fifth transistor are connected to a third current source to form a bias voltage, and a source terminal of the fifth transistor is connected to the low-dropout regulator; a switch coupled between the fifth transistor and the intermediate node; and a plurality of sixth transistors, wherein a plurality of gate terminals of the plurality of sixth transistors are commonly connected to the intermediate node, and a drain terminal of each of the plurality of sixth transistors is respectively connected to the first current source of each of the plurality of digital-to-analog converters.

7. The ramp signal generator as claimed in claim 6, wherein the switch is configured to reset the DC level of the intermediate voltage at the intermediate node according to the bias voltage, and the plurality of sixth transistors are each configured to form a supplementary current to the digital-to-analog converter, wherein a current value of the supplementary current is negatively correlated with an AC component of the intermediate voltage.

8. The ramp signal generator of claim 1, wherein the ramp signal generator is configured to generate a ramp output signal to an image readout circuit, the image readout circuit comprising: a buffer stage coupled to the ramp signal generator and configured to generate a ramp buffer signal based on the ramp output signal; a readout comparator coupled to the buffer stage and a photodetector pixel and configured to compare a pixel sensing voltage from the photodetector pixel with the ramp buffer signal to generate a comparison result; and a counter coupled to the readout comparator and configured to generate a digital output signal based on the comparison result, the digital output signal representing a grayscale or a luminance level of the pixel sensing voltage.

9. The ramp signal generator as claimed in claim 8, wherein the noise cancellation circuit comprises: a low-dropout regulator; a seventh transistor, wherein a drain terminal and a gate terminal of the seventh transistor are connected to a fourth current source to form a bias voltage, and a source terminal of the seventh transistor is connected to the low-dropout regulator; a switch coupled between the seventh transistor and the intermediate node; and an eighth transistor, wherein a gate terminal of the eighth transistor is connected to the intermediate node, and a drain terminal of the eighth transistor is connected to the buffer stage.

10. The ramp signal generator of claim 9, wherein the buffer stage includes a ninth transistor, wherein a gate terminal of the ninth transistor is configured to receive the ramp output signal, a drain terminal of the ninth transistor is configured to generate the ramp buffer signal, wherein the switch is configured to reset the DC level of the intermediate voltage at the intermediate node according to the bias voltage, and the eighth transistor is configured to form a supplementary voltage to the drain terminal of the ninth transistor, wherein a voltage level of the supplementary voltage is negatively correlated with an AC component of the intermediate voltage.

11. The ramp signal generator as claimed in claim 8, wherein the readout comparator includes a first comparator, a second comparator, and an inverter, wherein the noise cancellation circuit includes: a third capacitor coupled between a negative input of the first comparator and the intermediate node; a fourth capacitor coupled between a positive input of the first comparator and a biased signal source; and a switch coupled between the biased signal source and the intermediate node.

12. The ramp signal generator as claimed in claim 11, wherein the switch is configured to reset the DC level of the intermediate voltage at the intermediate node according to the bias voltage, and the third capacitor is configured to form a supplementary voltage to the negative input of the first comparator, wherein a voltage level of the supplementary voltage is positively correlated with an AC component of the intermediate voltage.

13. An image sensing device, comprising: a ramp signal generator for generating a ramp output signal, wherein the ramp signal generator comprises: a digital-to-analog converter having a first output terminal and a second output terminal, and for generating a ramp-up voltage signal at the first output terminal and a ramp-down voltage signal at the second output terminal, wherein the ramp output signal is generated based on the ramp-up voltage signal or the ramp-down voltage signal; and a first capacitor coupled between the first output terminal and an intermediate node; A second capacitor is coupled between the second output terminal and the intermediate node; a noise cancellation circuit is coupled to the intermediate node and is used to provide a compensation feedback based on an intermediate voltage on the intermediate node; and an image readout circuit is coupled to the ramp signal generator and a photodetector pixel, the image readout circuit being used to sample a pixel sensing voltage from the photodetector pixel with reference to the ramp output signal from the ramp signal generator to generate a digital output signal.

14. The image sensing apparatus of claim 13, wherein the image readout circuitry comprises: a buffer stage coupled to the ramp signal generator and configured to generate a ramp buffer signal based on the ramp output signal; a readout comparator coupled to the buffer stage and the photosensitive pixel and configured to compare the pixel sensing voltage from the photosensitive pixel with the ramp buffer signal to generate a comparison result; and a counter coupled to the readout comparator and configured to generate the digital output signal based on the comparison result, the digital output signal representing a grayscale or a luminance level of the pixel sensing voltage.

15. The image sensing apparatus of claim 14, wherein the digital-to-analog converter includes a plurality of digital-to-analog conversion units, each of the plurality of digital-to-analog conversion units including a first current source, a first transistor, and a second transistor, wherein the first transistor of each of the plurality of digital-to-analog conversion units is controlled by a single bit code in a first digital code to generate the ramp-up voltage signal, and the second transistor of each of the plurality of digital-to-analog conversion units is controlled by a single bit code in a second digital code to generate the ramp-down voltage signal.

16. The image sensing apparatus of claim 15, wherein the noise cancellation circuit comprises: a third transistor, wherein a drain terminal and a gate terminal of the third transistor are connected to a second current source to form a bias voltage; a switch coupled between the third transistor and the intermediate node; and a plurality of fourth transistors, wherein a plurality of gate terminals of the plurality of fourth transistors are commonly connected to the intermediate node, and a drain terminal of each of the plurality of fourth transistors is connected to the first current source of each of the plurality of digital-to-analog conversion units.

17. The image sensing apparatus of claim 15, wherein the noise cancellation circuit comprises: a low-dropout regulator; a fifth transistor, wherein a drain terminal and a gate terminal of the fifth transistor are connected to a third current source to form a bias voltage, and a source terminal of the fifth transistor is connected to the low-dropout regulator; a switch coupled between the fifth transistor and the intermediate node; and a plurality of sixth transistors, wherein a plurality of gate terminals of the plurality of sixth transistors are commonly connected to the intermediate node, and a drain terminal of each of the plurality of sixth transistors is respectively connected to the first current source of each of the plurality of digital-to-analog conversion units.

18. The image sensing apparatus of claim 15, wherein the noise cancellation circuit comprises: a low-dropout regulator; a fifth transistor, wherein a drain terminal and a gate terminal of the fifth transistor are connected to a third current source to form a bias voltage, and a source terminal of the fifth transistor is connected to the low-dropout regulator; a switch coupled between the fifth transistor and the intermediate node; and a plurality of sixth transistors, wherein a plurality of gate terminals of the plurality of sixth transistors are commonly connected to the intermediate node, and a drain terminal of each of the plurality of sixth transistors is respectively connected to the first current source of each of the plurality of digital-to-analog conversion units.

19. The image sensing apparatus of claim 14, wherein the readout comparator includes a first comparator, a second comparator, and an inverter, wherein the noise cancellation circuit includes: a third capacitor coupled between a negative input terminal of the first comparator and the intermediate node; a fourth capacitor coupled between a positive input terminal of the first comparator and a biased signal source; and a switch coupled between the biased signal source and the intermediate node.

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