Double-layer stacked semiconductor light-emitting element and its manufacturing method

Abstract

This invention provides a double-layer stacked semiconductor light-emitting element with good output characteristics and improved reverse voltage characteristics (reduced leakage current). A double-layer stacked semiconductor light-emitting element 100 comprises, in sequence: a first n-type semiconductor layer 140; an undoped first active layer 144; a p-type pseudo-tunnel junction layer 1471 having a p-type dopant; an n-type pseudo-tunnel junction layer 1472 grounded on the p-type pseudo-tunnel junction layer 1471 and having an n-type dopant; an undoped second active layer 149; and a second p-type semiconductor layer 150, wherein the maximum impurity concentration of the n-type dopant contained on the n-type pseudo-tunnel junction layer 1472 side of the second active layer 149 is less than 1.0 × 10¹⁶ atoms / cubic centimeter.

Description

Technical Field

[0001] This invention relates to a double-layer stacked semiconductor light-emitting element and a method for manufacturing the double-layer stacked semiconductor light-emitting element. Prior Technology

[0002] Previously, it was known that to increase the output power of a semiconductor light-emitting element, a double-layer stacked semiconductor light-emitting element was constructed by fabricating two or more light-emitting layers and arranging them perpendicularly to each other. In this type of double-layer stacked semiconductor light-emitting element, a tunnel junction layer with a high concentration of dopant is present between each of the two or more light-emitting layers arranged perpendicularly.

[0003] For example, Patent Document 1 discloses a light-emitting diode (LED) semiconductor in which a first active layer and a second active layer are arranged perpendicularly to each other and a tunnel junction is formed between the first active layer and the second active layer. [Existing Technical Documents] [Patent Literature]

[0004] Patent Document 1: Japanese Patent Publication No. 2009-522755 Summary of the Invention

[0005] [Problems to be Solved by the Invention] However, the double-layer stacked LED semiconductor described in Patent Document 1 is practically not commercially available. The inventors conducted research and found that, in reality, even with two light-emitting layers, the luminous output power at a current of 100 mA is only about 1.3 to 1.45 times that of a single-layer stacked LED with multiple light-emitting layers is actually more efficient than a double-layer stacked LED. Furthermore, as a component characteristic, further reductions in leakage current and increases in reverse voltage are required.

[0006] Therefore, the purpose of this invention is to provide a double-layer stacked semiconductor light-emitting element with good output characteristics and the ability to reduce leakage current and increase reverse voltage, and a method for manufacturing the same. [Methods for solving problems]

[0007] The inventors have diligently researched methods to solve the aforementioned problems. Furthermore, the inventors believe that, as mentioned above, the reason why the luminous output power in a double-layer stacked LED is only about 1.3 to 1.45 times higher is due to the unintended adverse effects of the dopant contained in the layer used to form the tunnel junction (the highly doped layer). Measurements of dopant diffusion behavior show that the dopant in the n-type tunnel junction layer diffuses into the second active layer, causing a decrease in output power. The inventors have focused on the n-type dopant concentration in the active layer on the side where the n-type tunnel layer is located, and experimentally confirmed the conditions that can improve output characteristics and reverse voltage characteristics. Therefore, the main structure of the present invention is as follows.

[0008] (1) A double-layer stacked semiconductor light-emitting element, characterized in that it comprises, in sequence: First n-type semiconductor layer; Undoped first active layer; p-type pseudo-tunneling layer, containing p-type dopants; An n-type pseudo-tunneling layer is grounded on the p-type pseudo-tunneling layer and has an n-type dopant. Undoped second active layer; and Second p-type semiconductor layer, The maximum impurity concentration of the n-type dopant contained in the n-type pseudo-tunnel junction layer of the second active layer is less than 1.0 × 10¹⁶ atoms / cubic centimeter.

[0009] (2) The double-layer stacked semiconductor light-emitting element as described in (1), wherein, Between the n-type pseudo-tunnel junction layer and the second active layer, there is a second n-type semiconductor layer with a Si impurity concentration of 5.0 × 10¹⁷ atoms / cm³ or higher and 5.0 × 10¹⁸ atoms / cm³ or lower.

[0010] (3) The double-layer stacked semiconductor light-emitting element as described in (1) or (2), wherein, The average impurity concentration of the n-type dopant contained in the first active layer and the second active layer is less than 5.0 × 10¹⁵ atoms / cubic centimeter.

[0011] (4) A double-layer stacked semiconductor light-emitting element as described in any one of (1) to (3), wherein, The n-type dopant in the n-type pseudo-tunnel junction is Si.

[0012] (5) A double-layer stacked semiconductor light-emitting element as described in any one of (1) to (4), wherein, The p-type dopant in the p-type pseudo-tunnel junction is C.

[0013] (6) The double-layer stacked semiconductor light-emitting element as described in any one of (1) to (5), wherein, The impurity concentration of the n-type dopant in the n-type pseudo-tunnel junction is above 1.5 × 10¹⁹ atoms / cubic centimeter.

[0014] (7) A double-layer stacked semiconductor light-emitting element as described in any one of (1) to (6), wherein, The impurity concentration of the p-type dopant in the p-type pseudo-tunnel junction is above 1.0 × 10¹⁹ atoms / cubic centimeter.

[0015] (8) A double-layer stacked semiconductor light-emitting element as described in any one of (1) to (7), wherein, The first active layer, the second active layer, the p-type pseudo-tunneling layer, and the n-type pseudo-tunneling layer contain AlGaInAs or InGaAsP.

[0016] (9) A double-layer stacked semiconductor light-emitting element as described in any one of (1) to (8), wherein, In the current-voltage curves when the p-type pseudo-tunneling layer and the n-type pseudo-tunneling layer are energized without separating the first active layer and the second active layer, the points where the current becomes extremely large are in the range of above 0.02 V and below 0.2 V.

[0017] (10) A double-layer stacked semiconductor light-emitting element as described in any one of (1) to (9), wherein, In the current-voltage curves when the p-type pseudo-tunneling layer and the n-type pseudo-tunneling layer are energized without separating the first active layer and the second active layer, the maximum value of the current is less than 7 mA.

[0018] (11) A method for manufacturing a double-layer stacked semiconductor light-emitting element, comprising: The step of forming a first n-type semiconductor layer on a substrate; The step of forming an undoped first active layer on the first n-type semiconductor layer; The step of forming a p-type pseudo-tunnel junction layer with p-type dopant on the first active layer; The step of directly forming an n-type pseudo-tunnel layer with n-type dopant on the p-type pseudo-tunnel layer; The step of forming an undoped second active layer on the n-type pseudo-tunnel junction layer; and The step of forming a second p-type semiconductor layer on the second active layer, The maximum value of the impurity concentration of the n-type dopant contained in the n-type pseudo-tunnel junction layer of the second active layer is set to below 1.0 × 10¹⁶ atoms / cubic centimeter.

[0019] (12) A double-layer stacked semiconductor light-emitting element, comprising: Support substrate; A bonding layer is disposed on the supporting substrate; The intermediate electrode layer is formed by arranging the dielectric portion and the electrode portion side by side on the bonding layer; A second p-type semiconductor layer is disposed on the intermediate electrode layer; An undoped second active layer is disposed on the second p-type semiconductor layer; An n-type pseudo-tunnel junction layer is disposed on the second active layer and has an n-type dopant; A p-type pseudo-tunnel layer is grounded on the n-type pseudo-tunnel junction layer and contains a p-type dopant. An undoped first active layer is disposed on the p-type pseudo-tunnel layer; A first n-type semiconductor layer is disposed on the first active layer; and The upper electrode is disposed on the first n-type semiconductor layer. The maximum impurity concentration of the n-type dopant contained in the n-type pseudo-tunnel junction layer of the second active layer is less than 1.0 × 10¹⁶ atoms / cubic centimeter. [The effects of the invention]

[0020] The present invention provides a double-layer stacked semiconductor light-emitting element with good output characteristics, which can reduce leakage current and increase reverse voltage, and a method for manufacturing the same. Simple Explanation of the Diagram

[0021] Figure 1 is a schematic cross-sectional view illustrating a double-layer stacked semiconductor light-emitting element according to a first embodiment of the present invention. Figure 2 is a schematic cross-sectional view illustrating a double-layer stacked semiconductor light-emitting element according to a second embodiment of the present invention. Figure 3 is a schematic cross-sectional view illustrating a portion of the manufacturing steps of a double-layer stacked semiconductor light-emitting element according to a second embodiment of the present invention. Figure 4 is a schematic cross-sectional view illustrating a portion of the manufacturing steps of a double-layer stacked semiconductor light-emitting element according to a second embodiment of the present invention, following Figure 3. Figure 5 is a schematic cross-sectional view illustrating a portion of the manufacturing steps of a double-layer stacked semiconductor light-emitting element according to a second embodiment of the present invention, following Figure 4. Figure 6 is a schematic cross-sectional view illustrating a portion of the manufacturing steps of a double-layer stacked semiconductor light-emitting element according to a second embodiment of the present invention, following Figure 5. Figure 7 is a schematic cross-sectional view illustrating a portion of the manufacturing steps of a double-layer stacked semiconductor light-emitting element according to a second embodiment of the present invention, following Figure 6. Figure 8 is a schematic cross-sectional view illustrating the components used to perform performance verification in Test 1. Figure 9 is a graph showing the power-on results of Test 1 of Examples 1 to 3 and Comparative Example 1. Figure 10 is a graph showing the current-light output characteristics of the double-layer stacked semiconductor light-emitting elements of Examples 1 to 3 and Comparative Example 1. Figure 11 is a graph showing the results of measuring the Si diffusion state of the double-layer stacked semiconductor light-emitting element of Example 1 by SIMS. Figure 12 is a graph showing the results of measuring the Si diffusion state of the double-layer stacked semiconductor light-emitting element of Example 2 by SIMS. Figure 13 is a graph showing the results of measuring the Si diffusion state of the double-layer stacked semiconductor light-emitting element of Example 3 by SIMS. Figure 14 is a graph showing the results of measuring the Te diffusion state of the double-layer stacked semiconductor light-emitting element of Comparative Example 1 by SIMS. Implementation

[0022] In this specification, a layer that functions electrically as a p-type layer is referred to as a p-type semiconductor layer (sometimes simply called a "p-type layer"), and a layer that functions electrically as an n-type layer is referred to as an n-type semiconductor layer (sometimes simply called an "n-type layer"). On the other hand, without the intentional addition of specific impurities such as Si, Te, Zn, S, and C, it is referred to as "i-type" or "undoped". In the III-V compound semiconductor layer, unavoidable impurities may be introduced during the manufacturing process. In this invention, at least an undoped first active layer and an undoped second active layer are formed. Each active layer is formed without the flow of dopant gas and is therefore undoped. However, the effect of dopant diffusion from other layers (e.g., tunnel junction layers or pseudo-tunnel junction layers) can sometimes be observed. In this invention, impurities are not intentionally added during the growth of the layer. However, if the diffusion of impurities contained in other layers is observed during the manufacturing process, and no impurity concentration exceeding the minimum concentration of 1 × 10¹⁶ atoms / cubic centimeter is observed in a typical n-type or p-type cladding, the active layer is treated as "undoped".

[0023] Generally, a "tunnel junction" refers to a layer having a current-voltage curve as shown in Comparative Example 1 of FIG9, where the current-voltage curve exhibits a negative resistance region where the positive current decreases as the positive voltage increases from 0 V, and then increases with the positive voltage. The positive current flowing before the negative resistance region is called the tunnel current. In this specification, a "pseudo-tunnel junction" refers to a layer having a negative resistance region in the current-voltage curve as shown in Examples 1 to 3 of FIG9, but with a tunnel current close to zero (e.g., less than 10 mA). Although it has a region that shows negative resistance in terms of numerical value, at first glance, it appears to have the same current-voltage curve and negative resistance region as a typical pn junction diode, except that it is the same curve. It is generally believed that in components using tunnel junction structures, a large tunnel current is required as in Comparative Example 1 of FIG9. Therefore, the inventors also believed that in the behavior of the embodiments of FIG9, the tunnel current was too weak to be used as a tunnel junction. However, in actual use in the double-layer stacked semiconductor light-emitting element of the present invention, although the reason is unclear, it has been confirmed that it causes a higher light output power, lower leakage current, and higher reverse voltage than the tunnel junction layer in Comparative Example 1, which results in a higher luminous output power. For example, the "pseudo-tunnel junction layer" preferably has a starting point (current maximum) of the negative resistance region in the range of 0.02 V or more and 0.2 V, and preferably the maximum tunnel current (current maximum value) at the current maximum point is 7 mA or less. Moreover, the p-type layer and n-type layer connected within the "pseudo-tunnel junction layer" are respectively referred to as "p-type pseudo-tunnel junction layer" and "n-type pseudo-tunnel junction layer".

[0024] In this specification, the impurity concentrations of n-type and p-type dopants were determined using secondary mass spectrometry (SIMS) using a CAMECA IMS-4f manufactured by AMTEC. The analytical conditions were: primary seed Cs+, primary energy 14.5 keV, and negative secondary polarity. For SIMS values ​​of each layer, the average value excluding the end (5 nm width) was used for films thicker than 40 nm, and the maximum SIMS value (peak value) for the corresponding layer was used for films thicker than 40 nm.

[0025] In this specification, the term "n-type pseudo-tunnel junction side" of the second active layer refers to the region extending from the center of the second active layer in the thickness direction to the boundary of other layers adjacent to the n-type pseudo-tunnel junction side of the second active layer, such as the barrier layer located at the end of the n-type pseudo-tunnel junction side of the second active layer. Within this region, the maximum impurity concentration of the n-type dopant typically occurs at the boundary between the second active layer and other layers adjacent to the n-type pseudo-tunnel junction side of the second active layer.

[0026] Each semiconductor layer can be formed by epitaxial growth, such as by known thin film growth methods like metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). For example, by using trimethylindium (TMIn) as the In source, trimethylgallium (TMGa) or triethylgallium (TEGa) as the Ga source, trimethylaluminium (TMAl) as the Al source, arsine (AsH3) or tertiarybutylarsine (TBAs) as the As source, and phosphine (PH3) or tertiary-butylphosphine (TBP) as the P source, and using a carrier gas to grow these raw material gases in the gas phase, the desired thickness can be formed according to the growth time. When doping each layer into p-type or n-type, it is sufficient to use a gas as the dopant source that corresponds to the desired type. For example, when doping Si, Si₂H₆ gas can be used, and when doping C, CBr₄ gas can be used.

[0027] (First Implementation Form) Referring to FIG1, a double-layer stacked semiconductor light-emitting element according to a first embodiment and a method for manufacturing a double-layer stacked semiconductor light-emitting element will be described. The double-layer stacked semiconductor light-emitting element 100 has multiple active layers stacked in the vertical direction. Between these active layers are pseudo-tunneling layers, where current flows in the opposite direction (e.g., from n-type to p-type) relative to the conductivity type direction (e.g., from p-type to n-type) before and after the active layers due to the pseudo-tunneling effect, thus functioning as a so-called double-layer stacked light-emitting diode. For example, in the embodiment with two active layers as the minimum structure, the first active layer and the second active layer are arranged to overlap each other in the vertical direction. Furthermore, the active layer closest to the p-type pseudo-tunneling layer 1471 included in the pseudo-tunneling layer 147 is designated as the first active layer 144, and the active layer closest to the n-type pseudo-tunneling layer 1472 included in the pseudo-tunneling layer 147 is designated as the second active layer 149. Furthermore, the semiconductor light-emitting element is preferably a light-emitting diode (LED), and the first active layer and the second active layer preferably perform incoherent emission in each layer. Each active layer can be formed as a single quantum well (SQW) structure, a multi-quantum well (MQW) structure, or a quantum wire structure or a quantum dot structure. When the number of active layers is set to three or more, the active layers are also arranged to overlap each other in the vertical direction. Any two active layers that are close to each other are regarded as the first active layer 144 and the second active layer 149. If the first active layer 144, the pseudo-tunnel junction layer 147, and the second active layer 149 satisfy the requirements of the present invention, then it is the double-layer stacked semiconductor light-emitting element 100 of the present invention.

[0028] The manufacturing method of the double-layer stacked semiconductor light-emitting element 100 according to the first embodiment includes at least the following steps: forming a first n-type semiconductor layer 140; forming an undoped first active layer 144 on the first n-type semiconductor layer 140; forming a p-type pseudo-tunnel junction layer 1471 with p-type dopant on the first active layer 144; directly forming an n-type pseudo-tunnel junction layer 1472 with n-type dopant on the p-type pseudo-tunnel junction layer 1471; forming a second active layer 149 on the n-type pseudo-tunnel junction layer 1472; and forming a second p-type semiconductor layer 150 on the second active layer 149. All semiconductor layers constituting the first n-type semiconductor layer 140 to the second p-type semiconductor layer 150 are collectively referred to as semiconductor stack 120. Furthermore, the maximum impurity concentration of the n-type dopant originating from the n-type pseudo-tunnel junction layer 1472 on the n-type pseudo-tunnel junction layer 1472 side of the second active layer 149 is 1.0 × 10¹⁶ atoms / cubic centimeter or less. The impurity concentration of the n-type dopant is preferably below 7.0 × 10¹⁵ atoms / cm³, and more preferably below 5.0 × 10¹⁵ atoms / cm³.

[0029] A first electron blocking layer 145 and / or a first p-type semiconductor layer 146 may also exist between the first active layer 144 and the p-type pseudo-tunnel junction layer 1471. A second n-type semiconductor layer 148 may also exist between the n-type pseudo-tunnel junction layer 1472 and the second active layer 149. Furthermore, a second electron blocking layer 151 may also exist between the second active layer 149 and the second p-type semiconductor layer 150. In addition, an undoped spacer layer may also be provided between an undoped layer and a p-type or n-type layer formed by doping. The details of each step will be explained below.

[0030] First, a growth substrate 105 is prepared. The growth substrate 105 can be a compound semiconductor substrate such as GaAs, InP, InAs, GaSb, or InSb. In terms of cost, a GaAs substrate is preferred. The growth substrate 105 is preferably on which the initially grown layer is aligned with the conductivity type. For example, the growth substrate is preferably an S-doped n-type InP substrate, and the first n-type semiconductor layer 140 is preferably deposited on the (100) surface of the n-type InP substrate. Furthermore, the thickness of the growth substrate 105 is preferably 200 μm or more and 900 μm or less.

[0031] <Steps for forming the first n-type semiconductor layer> A first n-type semiconductor layer 140 is formed on the growth substrate 105. The first n-type semiconductor layer 140 can be a single layer or composed of multiple different layers. In FIG1, an n-type contact layer 141 and a first n-type cladding layer 142 are shown as the layers constituting the first n-type semiconductor layer 140. The n-type contact layer 141 can be, for example, an n-type InGaAs layer, with a thickness preferably of 2 nm or more and 200 nm or less, more preferably 5 nm or more and 20 nm or less. The first n-type cladding layer can be, for example, an n-type InP layer, with a thickness preferably of 500 nm or more and 8000 nm or less, more preferably 3150 nm or more and 3750 nm or less. Examples of n-type dopants used in the n-type contact layer 141 and the first n-type cladding layer 142 include Si and S. In addition, a buffer layer can also be provided between the growth substrate 105 and the n-type semiconductor layer 140.

[0032] Although not illustrated, a spacer layer may be provided between the first n-type semiconductor layer 140 and the undoped first active layer 144 formed thereon. When in contact with a layer containing an n-type dopant, the thickness of the spacer layer is preferably 10 nm or more and 200 nm or less, more preferably 70 nm or more and 130 nm or less. The spacer layer is preferably configured to have the same composition as the adjacent layer and is undoped. The spacer layer reduces the amount of impurity diffusion from the doped layer to the undoped layer, for example, reducing the amount of n-type dopant diffusion from the first n-type cladding layer 142 to the first active layer 144.

[0033] <Steps for forming the first active layer> An undoped first active layer 144 is formed on the first n-type semiconductor layer 140. The first active layer 144 is preferably composed of AlGaInAs or InGaAsP. Figure 1 illustrates, exemplarily, a quantum well structure with a well layer 144w as the well layer and a barrier layer 144b as the barrier layer, but the first active layer 144 can also be a single-layer structure. The well layer 144w and the barrier layer 144b can be different layers, and strain can be applied to the well layer 144w by adjusting the compositional difference. Alternatively, the first active layer 144 can also be formed using InGaAlAs layers with different compositional ratios. To improve optical output power by suppressing crystal defects, the first active layer 144 is preferably a multiple quantum well (MQW) structure as shown in Figure 1. The multiple quantum well structure can be formed by alternately repeating the well layer 144w and the barrier layer 144b. When using a multi-quantum-well structure, the combination of well layers 144w and barrier layers 144b is preferably 3 or more and 40 or less. That is, including the initial barrier layer, it is preferably 3.5 or more and 40.5 or less. Furthermore, the film thickness of each well layer is preferably 5 nm or more and 40 nm or less, and the film thickness of each barrier layer is preferably 10 nm or more and 50 nm or less. In addition, the first active layer 144 may also have a wavelength region with a light emission center wavelength of 1200 nm or more.

[0034] A first electron blocking layer 145 may also be disposed on the first active layer 144. The first electron blocking layer 145 may be undoped or p-type, but is preferably undoped. The first electron blocking layer may be a single layer or composed of multiple layers. The thickness of the first electron blocking layer 145 is preferably 2 nm or more and 200 nm or less, more preferably 5 nm or more and 30 nm or less. The first electron blocking layer 145 is a layer for implanting and confining carriers into the first active layer 144. In addition, the first electron blocking layer 145 also has the effect of reducing the diffusion of p-type dopants from the pseudo-tunnel junction layer 147 (described later) into the first active layer 144.

[0035] Although not shown, a spacer layer may be provided between the undoped first electron blocking layer 145 and the first p-type semiconductor layer 146 formed thereon. The thickness of the spacer layer, when in contact with the layer containing the p-type dopant, is preferably 40 nm or more and 400 nm or less, and more preferably 170 nm or more and 330 nm or less.

[0036] <Steps for forming the first p-type semiconductor layer> Preferably, a first p-type semiconductor layer 146 is provided between the first active layer 144 and the p-type pseudo tunnel junction layer 1471. As the first p-type semiconductor layer 146, for example, it may also have a first p-type cladding layer. The composition of the first p-type cladding layer preferably has a smaller bandgap than that of the first electron blocking layer 145. Examples include InGaAsP or InP. The p-type dopant concentration of the first p-type semiconductor layer 146 is preferably 5.0×10^17 atoms / cm^3 or more and 5.0×10^18 atoms / cm^3 or less. The first p-type semiconductor layer 146 may include layers other than the first p-type cladding layer. For example, it may also have an InAlAs layer or an AlInGaAs layer in which the group V element is different from that of the first p-type cladding layer.

[0037] <Formation steps of p-type pseudo tunnel junction layer and n-type pseudo tunnel junction layer> On the first p-type semiconductor layer 146, a pseudo tunnel junction layer 147 is formed in which an n-type pseudo tunnel junction layer 1472 is directly laminated on a p-type pseudo tunnel junction layer 147%. The p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 are preferably AlGaInAs or InGaAsP. Examples of the dopant that can be used in the p-type pseudo tunnel junction layer 1471 include Mg, Zn, C, Be, etc., but C is preferably used. By setting the dopant of the p-type pseudo tunnel junction layer 1471 to C, compared with other dopants, the dopant diffusion phenomenon to the adjacent epitaxial layer during growth can be suppressed. Examples of the dopant that can be used in the n-type pseudo tunnel junction layer 1472 include Si, Te, S, Ge, Sn, Se, etc., but Si is preferably used. By setting the dopant of the n-type pseudo tunnel junction layer 1472 to Si, the amount of the dopant doped in the n-type pseudo tunnel junction layer 1472 diffusing into the second active layer 149 described later can be suppressed. The impurity concentration of the p-type dopant in the p-type pseudo tunnel junction layer 1471 is preferably 1.0×10^19 atoms / cm^3 or more, more preferably 1.02×^19 atoms / cm^3 or more, and even more preferably 1.05×10^19 atoms / cm^3 or more. In addition, the impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer 1472 is preferably 1.5×10^19 atoms / cm^3 or more, more preferably 1.55×10^19 atoms / cm^3 or more, and even more preferably 1.6×10^19 atoms / cm^3 or more. The thickness and impurity concentration of the p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 may be the same or different. In addition, the impurity concentration of the p-type pseudo tunnel junction layer 1471 and the n-type pseudo tunnel junction layer 1472 does not need to be uniform within the layer and may have a concentration gradient. The impurity concentration of the n-type dopant in the n-type pseudo tunnel junction layer 1472 is even more preferably 5×10^19 atoms / cm^3 or less.

[0038] Alternatively, a p-type intermediate layer may be provided between the first p-type semiconductor layer 146 and the p-type pseudo-tunnel junction layer 1471. The p-type intermediate layer is a layer containing group V elements that differ from those in the p-type pseudo-tunnel junction layer 1471. For example, if the p-type pseudo-tunnel junction layer 1471 contains AlInGaAs, then the p-type intermediate layer contains InGaAsP. Preferably, the p-type intermediate layer has a higher impurity concentration than the first p-type cladding layer and an impurity concentration equal to or lower than that in the p-type pseudo-tunnel junction layer 1471. Similarly, an n-type intermediate layer may also be provided between the n-type pseudo-tunnel junction layer 1472 and the second n-type semiconductor layer 148. The n-type intermediate layer is a layer containing group V elements that differ from those in the n-type pseudo-tunnel junction layer 1472. For example, if the n-type pseudo-tunnel junction layer 1472 contains AlInGaAs, then the n-type intermediate layer contains InGaAsP. The n-type intermediate layer preferably has a higher impurity concentration than the second n-type cladding layer, and an impurity concentration that is equal to or lower than that of the n-type pseudo-tunneling layer 1472.

[0039] Typically, to form a tunnel junction, the doping rate of the semiconductor needs to be greatly increased to thin the depletion layer formed at the junction of the p-type pseudo-tunnel junction 1471 and the n-type pseudo-tunnel junction 1472 to the extent that quantum tunneling can be achieved. In this embodiment, the thickness of the p-type pseudo-tunnel junction 1471 is preferably 10 nm or more and 60 nm or less, more preferably 20 nm or more and 50 nm or less, and even more preferably 30 nm or more and 40 nm or less. Furthermore, the thickness of the n-type pseudo-tunnel junction 1472 is preferably 5 nm or more and 30 nm or less, more preferably 10 nm or more and 25 nm or less, and even more preferably 15 nm or more and 20 nm or less.

[0040] The inventors have focused specifically on the Si dopant concentration of the n-type pseudo-tunnel junction 1472. By optimizing various growth conditions, a high concentration of Si can be doped into the n-type pseudo-tunnel junction 1472. Compared with other dopants (such as Te), Si atoms are less likely to diffuse into the second active layer 149, thus improving the luminous efficiency of the second active layer 149. As a whole, the output characteristics of the double-layer stacked semiconductor light-emitting element 100 are also improved.

[0041] Alternatively, a Si-doped second n-type semiconductor layer 148 may be formed on the pseudo-tunnel junction layer 147. The Si impurity concentration of the second n-type semiconductor layer 148 is preferably 1.0 × 10¹⁷ atoms / cm³ or more and 5.0 × 10¹⁸ atoms / cm³ or less, more preferably 3.0 × 10¹⁷ atoms / cm³ or more and 3.0 × 10¹⁸ atoms / cm³ or less, and even more preferably 5.0 × 10¹⁷ atoms / cm³ or more and 1.0 × 10¹⁸ atoms / cm³ or less. The thickness of the second n-type semiconductor layer 148 is preferably 100 nm or more and 2000 nm or less, more preferably 300 nm or more and 600 nm or less. Furthermore, a layer other than the second n-type semiconductor layer 148 may be included between the second active layer 149 and the pseudo-tunnel junction layer 147, and a spacer layer may be provided between the second n-type semiconductor layer 148 and the undoped second active layer 149.

[0042] The thickness of the spacer layer formed between the second n-type semiconductor layer 148 and the undoped second active layer 149 is preferably 10 nm or more and 200 nm or less, more preferably 70 nm or more and 130 nm or less. The spacer layer reduces the amount of impurity diffusion from the doped layer to the undoped layer, for example, reducing the amount of Si diffusion from the second n-type semiconductor layer 148 to the second active layer 149.

[0043] <Steps for forming the second active layer> An undoped second active layer 149 is formed on the second n-type semiconductor layer 148. The second active layer 149 preferably comprises AlGaInAs or InGaAsP. Here, for the double-layer stacked semiconductor light-emitting element 100 having a first active layer 144 and a second active layer 149, the light-emitting center wavelength of the first active layer 144 and the light-emitting center wavelength of the second active layer 149 can be set to the same wavelength or to similar wavelengths. When the wavelengths are the same, the second active layer 149 preferably adopts the same structure as the first active layer 144. For example, in FIG1, a quantum well structure is illustrated using InGaAlAs layers with different composition ratios and including a barrier layer 144b and a well layer 144w of the first active layer 144, but preferably, the barrier layer 149b and the well layer 149w of the second active layer 149 are also configured to have common structures. In this case, the first active layer 144 and the second active layer 149 have the same emission wavelength, and the emission center wavelength of the synthesized emission spectrum from each active layer is 1200 nm or higher. If the luminous efficiency and power consumption between the active layers do not deviate due to impurity diffusion into the second active layer 149 as described above, the synthesized luminous intensity increases by nearly twice compared to the case where there is only one active layer. Furthermore, even when the wavelengths are not the same, if the materials used in the active layers have the same structure, and the emission center wavelengths are close to the degree of overlap between the two emission spectra, the same effect as the present invention is achieved, and the synthesized luminous intensity increases by nearly twice compared to the case where there is only one active layer.

[0044] A second electron blocking layer 151 may also be disposed on the second active layer 149. The second electron blocking layer 151 may be undoped or p-type, but is preferably undoped. The second electron blocking layer 151 may be a single layer or composed of multiple layers. The thickness of the second electron blocking layer 151 is preferably 2 nm or more and 200 nm or less, more preferably 5 nm or more and 30 nm or less. The second electron blocking layer 151 is a layer for implanting and confining carriers into the second active layer 149. In addition, the second electron blocking layer 151 also has the effect of reducing the diffusion of dopant from the second p-type cladding layer 152 (described later) into the second active layer 149. When the second electron blocking layer 151 is undoped, a spacer layer may also be disposed between the second electron blocking layer 151 and the second p-type semiconductor layer 150 thereon.

[0045] <Steps for forming the second p-type semiconductor layer> A second p-type semiconductor layer 150 is formed on the second active layer 149. The second p-type semiconductor layer 150 can be a single layer or composed of multiple different layers. In Figure 1, the p-type semiconductor layer 150 composed of a second p-type cladding layer 152 and a p-type contact layer 153 is shown.

[0046] The thickness of the second p-type cladding 152 is preferably 1000 nm or more and 8000 nm or less. If the second p-type cladding 152 is thicker, the light emitted from the second active layer 149 will be more significantly absorbed within the second p-type cladding 152, resulting in decreased light extraction, which is undesirable. Furthermore, current extends to the ends of the LED chip, increasing surface recombination; additionally, the ohmic resistance of the device increases, thereby reducing luminous efficiency, which is also undesirable. On the other hand, if the second p-type cladding 152 is thinner, light will be emitted directly below the electrode, hindering light extraction, which is also undesirable. Examples of dopants that can be used here include Mg, Zn, C, and Be. The dopant concentration of the second p-type cladding 152 is preferably 5.0 × 10¹⁷ atoms / cm³ or more and 3.0 × 10¹⁸ atoms / cm³ or less.

[0047] A p-type contact layer 153 may also be formed on the second p-type cladding 152. The thickness of the p-type contact layer 153 is preferably 30 nm or more and 200 nm or less. Furthermore, the p-type contact layer 153 is preferably formed from multiple layers of different group V elements, so that it can be partially etched away by patterning. A portion of the p-type contact layer 153 other than the p-type contact portion 163 used for connection with the upper electrode 191 can also be etched away. The dopant concentration of the p-type contact layer 153 is preferably higher than that of the second p-type cladding 152, and is 1.0 × 10¹⁸ atoms / cm³ or more and 8.0 × 10¹⁹ atoms / cm³ or less. Alternatively, the dopant concentration can be tilted to increase the dopant concentration on the surface side in contact with the electrode.

[0048] In this embodiment, a back electrode 195 can be provided on the back side of the growth substrate 105, and an upper electrode 191 can be provided on a portion of the p-type contact layer 153. The upper electrode 191 may include a wiring portion of an ohmic electrode and a pad portion. Although not shown, the pad portion may also have a bonding metal layer or solder. The metal materials and forming methods used in the upper electrode 191 and the back electrode 195 can be those known. As metal materials, Ti, Pt, Au, Ag, Al, Zn, Ni, etc. can be used.

[0049] The double-layer stacked semiconductor light-emitting element 100 obtained through the above steps has good output characteristics and can reduce leakage current and increase reverse voltage.

[0050] The double-layer stacked semiconductor light-emitting element 100 obtained by the manufacturing method described above will be described. An example of the double-layer stacked semiconductor light-emitting element 100 is shown in FIG1.

[0051] The double-layer stacked semiconductor light-emitting element 100 includes at least: a first n-type semiconductor layer 140, an undoped first active layer 144 on the first n-type semiconductor layer 140, a p-type pseudo-tunnel junction layer 1471 with p-type dopant on the first active layer 144, an n-type pseudo-tunnel junction layer 1472 connected to the p-type pseudo-tunnel junction layer 1471 and having n-type dopant, an undoped second active layer 149 on the n-type pseudo-tunnel junction layer 1472, and a second p-type semiconductor layer 150 on the second active layer 149. Furthermore, the maximum impurity concentration of the n-type dopant caused by the n-type pseudo-tunnel junction layer 1472 included in the second active layer 149 is 1.0 × 10¹⁶ atoms / cm³ or less, more preferably 7.0 × 10¹⁵ atoms / cm³ or less, and even more preferably 5.0 × 10¹⁵ atoms / cm³ or less.

[0052] <First n-type semiconductor layer> The thickness of the first n-type semiconductor layer 140 is preferably 500 nm or more and 8000 nm or less, more preferably 3150 nm or more and 3750 nm or less. The first n-type semiconductor layer 140 may also include an n-type contact layer 141 and a first n-type cladding layer 142. Additionally, although not shown, a spacer layer may be provided between the first n-type semiconductor layer 140 and the first active layer 144. Examples of dopants for the first n-type semiconductor layer 140 include S or Si.

[0053] <First active layer and second active layer> The impurity concentrations of the n-type dopants contained in the first active layer 144 and the second active layer 149 are preferably 1.0×10^16 atoms / cm³ or less, more preferably 7.0×10^15 atoms / cm³ or less, and still more preferably 5.0×10^15 atoms / cm³ or less. In addition, in principle, the impurity concentrations of the n-type dopants contained in the first active layer 144 and the second active layer 149 are 2.0×10^14 atoms / cm³ or more. Furthermore, the first active layer 144 and the second active layer 149 preferably contain AlGaInAs or InGaAsP, respectively. The first active layer 144 may also have a wavelength region with a luminescence center wavelength of 1200 nm or more. In addition, for the double-layer stacked semiconductor light-emitting element 100 having the first active layer 144 and the second active layer 149, the luminescence center wavelength of the first active layer 144 and the luminescence center wavelength of the second active layer 149 may be set to the same wavelength or to similar wavelengths.

[0054] A first electron blocking layer 145 may also be provided on the first active layer 144. The first electron blocking layer 145 may be undoped or p-type, but is preferably undoped. The first electron blocking layer 145 is a layer that injects and confines carriers into the first active layer 144. In addition, the first electron blocking layer 145 also has the effect of reducing the diffusion of the p-type dopant from the pseudo tunnel junction layer 147 described later into the first active layer 144.

[0055] On the first electron blocking layer 145, for example, a first p-type cladding layer may be provided as the first p-type semiconductor layer 146. The composition of the first p-type cladding layer preferably has a smaller bandgap than the composition of the first electron blocking layer 145, and examples include InGaAsP or InP. Although not shown, a spacer layer may also be provided between the undoped first electron blocking layer 145 and the first p-type semiconductor layer 146 formed thereon.

[0056] <p-type pseudo tunnel junction layer and n-type pseudo tunnel junction layer> Examples of dopants that can be used in the p-type pseudo-tunnel layer 1471 include Mg, Zn, C, and Be, but C is preferred. The impurity concentration of the p-type dopant in the p-type pseudo-tunnel layer 1471 is preferably 1.0 × 10¹⁹ atoms / cm³ or higher, more preferably 1.02 × 10¹⁹ atoms / cm³ or higher, and even more preferably 1.05 × 10¹⁹ atoms / cm³ or higher. Examples of dopants that can be used in the n-type pseudo-tunnel layer 1472 include Si, Te, S, Ge, Sn, and Se, but Si is preferred. The impurity concentration of the n-type dopant in the n-type pseudo-tunnel layer 1472 is preferably 1.0 × 10¹⁹ atoms / cm³ or higher, more preferably 1.55 × 10¹⁹ atoms / cm³ or higher, and even more preferably 1.6 × 10¹⁹ atoms / cm³ or higher. The p-type pseudo-tunnel layer 1471 and the n-type pseudo-tunnel layer 1472 are preferably composed of AlGaInAs or InGaAsP. The impurity concentration of the n-type dopant in the n-type pseudo-tunnel layer 1472 is preferably below 5 × 10¹⁹ atoms / cubic centimeter.

[0057] <Second n-type semiconductor layer> Preferably, a Si-doped second n-type semiconductor layer 148 is disposed between the n-type pseudo-tunnel junction layer 1472 and the second active layer 149. The Si impurity concentration of the second n-type semiconductor layer 148 is preferably 1.0 × 10¹⁷ atoms / cm³ or more and 5.0 × 10¹⁸ atoms / cm³ or less, more preferably 3.0 × 10¹⁷ atoms / cm³ or more and 3.0 × 10¹⁸ atoms / cm³ or less, and even more preferably 5.0 × 10¹⁷ atoms / cm³ or more and 1.0 × 10¹⁸ atoms / cm³ or less. The thickness of the second n-type semiconductor layer 148 is preferably 100 nm or more and 2000 nm or less, more preferably 300 nm or more and 600 nm or less. Alternatively, the spacer layer may be disposed between the second n-type semiconductor layer 148 and the undoped second active layer 149.

[0058] <Second p-type semiconductor layer> The thickness of the second p-type semiconductor layer 150 is preferably 1000 nm or more and 8400 nm or less, more preferably 2000 nm or more and 5000 nm or less. The second p-type semiconductor layer 150 may also include a second p-type cladding layer 152 or a p-type contact layer 153. Examples of dopants for the second p-type semiconductor layer 150 include Zn or C. In addition, a second electron blocking layer 151 may be provided between the second active layer 149 and the second p-type semiconductor layer 150. Furthermore, although not shown, a spacer layer may be provided on the second electron blocking layer 151. Moreover, a portion of the p-type contact layer 153 may be removed to provide a p-type contact portion 163 for connection with the upper electrode 191.

[0059] Characteristics of pseudo-tunnel layers In the current-voltage curves when the p-type pseudo-tunneling layer 1471 and the n-type pseudo-tunneling layer 1472 are energized without separating the first active layer 144 and the second active layer 149, the voltage when the current reaches its maximum value is preferably above 0.02 V and below 0.2 V.

[0060] In addition, in the current-voltage curves when the p-type pseudo-tunnel junction 1471 and the n-type pseudo-tunnel junction 1472 are energized without separating the first active layer 144 and the second active layer 149, the maximum value of the current is preferably below 7 mA.

[0061] The double-layer stacked semiconductor light-emitting element 100, as described above in detail, has excellent output characteristics, reducing leakage current and increasing reverse voltage characteristics. Furthermore, in the double-layer stacked semiconductor light-emitting element 100 of Figure 1, a first n-type semiconductor layer 140, a first active layer 144, a p-type pseudo-tunnel junction layer 1471, an n-type pseudo-tunnel junction layer 1472, a second active layer 149, and a second p-type semiconductor layer 150 are sequentially arranged from below the plane of the paper. However, this is just one example; the stacking order can also be reversed.

[0062] (Second Implementation Form) Referring to FIG2, a double-layer stacked semiconductor light-emitting element 200 according to a second embodiment of the present invention will be described. The double-layer stacked semiconductor light-emitting element 200 is a bonding type semiconductor light-emitting element obtained by bonding a support substrate to the opposite side of the growth substrate of the semiconductor laminate, and then removing the growth substrate. For components that are the same as those in the double-layer stacked semiconductor light-emitting element 100, the last two digits of the three-digit reference number are generally marked with the same reference number, and repeated descriptions are omitted.

[0063] The double-layer stacked semiconductor light-emitting element 200 includes at least: a support substrate 280, a bonding layer 270 disposed on the support substrate 280, an intermediate electrode layer 260 formed by a dielectric portion 261 and an electrode portion 265 disposed side by side on the bonding layer 270, a second p-type semiconductor layer 250 disposed on the intermediate electrode layer 260, an undoped second active layer 249 disposed on the second p-type semiconductor layer 250, an n-type pseudo-tunnel junction layer 2472 disposed on the second active layer 249 and having an n-type dopant, a p-type pseudo-tunnel junction layer 2471 disposed on the n-type pseudo-tunnel junction layer 2472 and having a p-type dopant, an undoped first active layer 244 disposed on the p-type pseudo-tunnel junction layer 2471, a first n-type semiconductor layer 240 disposed on the first active layer 244, and an upper electrode 291 disposed on the first n-type semiconductor layer 240. Furthermore, the feature is that the maximum impurity concentration of the n-type dopant originating from the n-type pseudo-tunnel junction 2472 contained in the second active layer 249 is 1.0 × 10¹⁶ atoms / cm³ or less. More preferably, the impurity concentration of the n-type dopant is 7.0 × 10¹⁵ atoms / cm³ or less, and even more preferably 5.0 × 10¹⁵ atoms / cm³ or less. In principle, the impurity concentration of the n-type dopant caused by the n-type pseudo-tunnel junction 2472 contained in the second active layer 249 is 2.0 × 10¹⁴ atoms / cm³ or more.

[0064] The double-layer stacked semiconductor light-emitting element 200 shown in Figure 2 has, from the side opposite to the supporting substrate 280, a first n-type semiconductor layer 240 (n-type contact layer 241 and first n-type cladding layer 242), a first active layer 244, a first electron blocking layer 245, a first p-type semiconductor layer 246, a p-type pseudo-tunnel junction layer 2471, an n-type pseudo-tunnel junction layer 2472, a second n-type semiconductor layer 248, a second active layer 249, a second electron blocking layer 251, and a second p-type semiconductor layer 250 (second p-type cladding layer 252 and p-type contact layer 253).

[0065] As a support substrate 280, which differs from the growth substrate, it is preferably cheaper and has higher thermal conductivity compared to the growth substrate. For example, compound substrates such as Si, Ge, and GaAs can be used. In addition, metal substrates using metals that can suppress the coefficient of thermal expansion, such as copper alloys, molybdenum, tungsten, and Kova iron nickel cobalt alloys, or sub-mount substrates with metal attached to ceramic substrates such as AlN can also be used. In terms of processability and price, it is also preferable to use a Si substrate for the support substrate 280.

[0066] Hereinafter, an example of an embodiment of the double-layer stacked semiconductor light-emitting element 200 and its manufacturing method will be described in more detail with reference to FIGS. 3 to 7. First, a growth substrate 205 is prepared. Then, referring to FIG. 3, a semiconductor stack 220 is formed. At this time, an etch stop layer (not shown) may be formed on the growth substrate 205. The semiconductor stack 220 is the same as the semiconductor stack 120 described above.

[0067] <<Formation of the Intermediate Electrode Layer>> An intermediate electrode layer 260 can be formed on the p-type contact layer 253. The intermediate electrode layer 260 includes a dielectric portion 261 with a through hole, an electrode portion 265 disposed within the through hole, and a p-type contact portion 263 as part of the p-type contact layer 253. The dielectric portion 261 and the electrode portion 265 (and the p-type contact portion 263) can be arranged side by side, or the electrode portion 265 and the p-type contact portion 263 can be arranged in series. The specific method for forming the intermediate electrode layer 260 is arbitrary. An example of a specific configuration for forming the intermediate electrode layer 260 will be described below with reference to Figures 4 and 5. Furthermore, two locations including the electrode portion 265 and the p-type contact portion 263 within the intermediate electrode layer 260 are simply illustrated in the figures. However, there can be one location or three or more locations. Preferably, the locations are arranged in a dispersed island or stripe pattern to avoid being directly below the upper electrode 291 and to facilitate the uniform in-plane propagation of the current between the upper electrode 291 and the upper electrode 291.

[0068] First, a mask is formed on the p-type contact layer 253. Electrode portions 265 are formed on the p-type contact portion 263, which is part of the p-type contact layer 253, using a sputtering method or the like. The resist is removed, and the electrode portions 265 other than those on the p-type contact portion 263 are removed. Then, a mask is formed on the p-type contact layer 253, and a portion of the p-type contact layer 253 other than the area where the electrode portions 265 are formed is removed, forming a p-type contact portion 263 that becomes a protrusion. Next, a dielectric portion 261 is formed on the semiconductor stack 220. As a film formation method, known methods such as chemical vapor deposition (CVD) or sputtering can be used. Then, a resist pattern on the intermediate electrode layer 260 is formed on the dielectric portion 261 using a photomask, and the dielectric portion 261 on the electrode portion 265 is removed by etching until the electrode portion 265 is exposed. The thickness of the intermediate electrode layer 260 is preferably 500 nm or more and 1000 nm or less, and more preferably 600 nm or more and 800 nm or less.

[0069] <<Form of Metal Reflective Layer>> As shown in Figure 4, it is also preferable to form a metal reflective layer 271 on the intermediate electrode layer 260. The metal reflective layer 271 may include multiple metal layers. Besides Au, Al, Pt, Ti, Ag, etc., may also be used as the metal constituting the metal reflective layer 271. Here, the metal reflective layer 271 preferably has 50% by mass or more Au in its composition. Furthermore, in order to reliably bond with the metal bonding layer 279 in subsequent steps, it is preferable to set the outermost layer of the metal reflective layer 271 (the side opposite to the semiconductor stack 220) as an Au metal layer. The thickness of the metal reflective layer 271 is preferably 400 nm or more and 2200 nm or less, and more preferably 1500 nm or more and 2000 nm or less.

[0070] <<Jointing with the support substrate>> The semiconductor stack 220 and the intermediate electrode layer 260 are bonded to the support substrate 280 at least via the metal bonding layer 279. The metal reflective layer 271 can be bonded to the metal bonding layer 279 by providing the metal reflective layer 271. The bonding between the two can be achieved by arranging the metal bonding layer 279 and the metal reflective layer 271 facing each other and bonding them together, and then performing heat compression bonding at a temperature of about 250°C to 500°C.

[0071] <<Formation of Metallic Bonding Layers>> The metal bonding layer 279 can be formed using metals such as Ti, Pt, and Au, or metals that form a eutectic alloy with Au (such as Sn), or solder. Preferably, these layers are stacked to form the metal bonding layer 279. The thickness of the metal bonding layer 279 is preferably 1000 nm or more and 2000 nm or less, and more preferably 1200 nm or more and 1800 nm or less. The outermost layer of the metal bonding layer 279 can be Au metal, and the outermost layer of the metal reflective layer 271 can also be Au, thereby achieving Au-Au diffusion-based bonding between Au layers. The metal reflective layer 271 and the metal bonding layer 279 are bonded together and referred to as the bonding layer 270.

[0072] The support substrate 280 can be any type of substrate different from the growth substrate 205, such as a semiconductor substrate, metal substrate, or ceramic substrate as described previously. Due to the bonding method used, the support substrate 280 can be lattice-mismatched with the semiconductor layers formed in this embodiment. Furthermore, while the support substrate 280 can be insulating depending on the application, it is preferably a conductive substrate. In terms of processability and cost, it is preferable to use a Si substrate for the support substrate 280. By using a Si substrate, the thickness of the support substrate 280 can be significantly reduced compared to the previous method, and it is also suitable for mounting with various semiconductor devices. In addition, compared to InAs substrates, Si substrates have advantages in heat dissipation.

[0073] <<Removal of substrate for growth>> After the support substrate 280 is bonded, the growth substrate 205 is removed. If the growth substrate 205 is a GaAs substrate, a wet etching process can be performed on the growth substrate 205, for example, using a mixture of ammonia and hydrogen peroxide. If the growth substrate 205 is an InP substrate, wet etching can be performed, for example, using diluted hydrochloric acid.

[0074] As shown in Figure 5, after removing the growth substrate 205, ohmic electrodes and pad electrodes can be formed as upper electrodes 291 on the upper surface of the semiconductor laminate 220 (the side opposite to the support substrate 280). The ohmic electrodes can be formed using metals such as Au, Ge, Ni, Ti, or metals that form a eutectic alloy with Au (such as Sn), or solder. The ohmic electrodes can be formed by conventional methods such as vapor deposition. The thickness of the ohmic electrodes is not limited; for example, it can be set to 300 nm or more and 1300 nm or less. Preferably, heat treatment for ohmic contacts is performed after the ohmic electrodes are formed.

[0075] After the ohmic electrode is formed, it is preferable to form a pad electrode on the ohmic electrode. The pad electrode can be formed using metals such as Ti or Au, metals that form a eutectic alloy with Au (such as Sn), or solder. The pad electrode can be formed using conventional methods such as vapor deposition. Furthermore, if the n-type contact layer 241 is a layer with low transmittance of light of the emission wavelength, it is preferable to remove the n-type contact layer 241 except for the area where the upper electrode 291 is formed, thus exposing the surface of the first n-type cladding layer 242.

[0076] After the pad electrode is formed, the upper surface of the semiconductor stack 220 (e.g., the surface of the first n-type cladding 242) surrounding the upper electrode 291 can also be roughened. This is because roughening improves light extraction efficiency. The roughening of the surface of the first n-type cladding 242 can be performed using conventional methods such as selective etching with a mask or wet etching. Preferably, the upper electrode 291 and the electrode portion 265 are separated when viewed from above.

[0077] <> As shown in Figure 6, a portion of the semiconductor stack 220 can also be removed by dry etching, thereby forming a mesa shape in the semiconductor stack 220. Reactive ion etching (RIE) is preferred as the dry etching method, and inductively coupled plasma (ICP) can be used as the plasma source. Dry etching is performed on a dicing street region of a certain width along a predetermined wafer dicing line viewed from above. The width of the dicing street region (dicing width) is the width required for wafer dicing without adversely affecting the active layer, for example, 40 μm to 100 μm. The dicing street region can be configured in a grid pattern, and the pad electrodes or electrode portions 265 of the intermediate electrode layer 260 formed herein are disposed in areas that are not part of the dicing street region viewed from above. After forming a mask (e.g., a SiO2 mask) with a thickness that is smaller than the semiconductor stack 220 during dry etching on the first n-type cladding layer 242 and will not disappear before the etching of the dicing region is completed, dry etching of the dicing region is performed to expose the first n-type cladding layer 242 in the dicing region. During dry etching, etching continues until the intermediate electrode layer 260 is exposed on the outer side of the mesa shape. The angle θ between the intermediate electrode layer 260 and the second p-type semiconductor layer 250 is preferably 70° or more and 85° or less. Furthermore, it is preferable that the two active layers and the space between them form perpendicular sides, so that the areas of the first and second active layers are the same when viewed from above.

[0078] <<The Formation of a Protective Film>> As shown in Figure 7, preferably, a protective film 230 is formed using plasma CVD or the like after the mesa is formed. The protective film 230 used at this time can include, for example, SiO2 or SiN. Alternatively, the SiO2 used as a mask in the mesa formation step can be part of the protective film 230. Furthermore, it is preferable that the protective film 230 does not cover the upper surface of the upper electrode 291. The thickness of the protective film 230 is preferably 50 nm or more and 500 nm or less.

[0079] Furthermore, a back electrode 295 can also be formed on the back side of the support substrate 280.

[0080] By using the above manufacturing method, the double-layer stacked semiconductor light-emitting element 200 shown in Figure 2 can be obtained. [Example]

[0081] (Example 1) First, using MOCVD, a Si-doped n-type InP buffer layer (thickness: 120 nm, carrier concentration: 5.0 × 10¹⁷ / cm³) is formed on the (100) surface of an n-type InP growth substrate 205 (thickness: 600 μm, S-doped, dopant concentration: 2.0 × 10¹⁸ / cm³). On this buffer layer, a Si-doped n-type In₀.₅₃₂Ga₀.₄₆₈As contact layer 241 (thickness: 24 nm, carrier concentration: 5.0 × 10¹⁷ / cm³) and a Si-doped first n-type InP cladding layer 242 (thickness: 3.5 μm, carrier concentration: 5.0 × 10¹⁷ / cm³) are formed as the first n-type semiconductor layer 240. An undoped InP spacer layer (thickness: 100 nm) is then formed on this buffer layer. Next, a first active layer 244 (total film thickness: 165 nm) with a quantum well structure having a light-emitting center wavelength of 1500 nm is formed. The first active layer 244 consists of an undoped In0.419Ga0.297Al0.284As well layer 244w (thickness: 10 nm) and an In0.765Ga0.125Al0.110As barrier layer 244b (thickness: 5 nm) stacked alternately in units of 10 layers, with the emission center wavelength set at 1500 nm. This process grows the In0.419Ga0.297Al0.284As well layer 244w, and includes the final barrier layer, there are 10.5 groups. An undoped In0.522Al0.478As first electron blocking layer 245 (thickness: 20 nm), an undoped InP spacer layer (thickness: 300 nm), a Zn-doped first p-type InP semiconductor layer 246 (thickness: 500 nm, carrier concentration: 7.0 × 10¹⁷ / cm³), a Zn-doped p-type Al0.478In0.522As layer (thickness: 200 nm, carrier concentration: 1.0 × 10¹⁸ / cm³), and a Zn-doped p-type Al0.122In0.529Ga0.349As layer (thickness: 20 nm, carrier concentration: 1.0 × 10¹⁸ / cm³) are formed on the first active layer 244. A Zn-doped p-type In0.763Ga0.237As0.512P0.488 intermediate layer (thickness: 20 nm, carrier concentration: 1.0×10¹⁸ / cm³) is formed on it.

[0082] Furthermore, a Si-doped n-type Al0.137In0.529Ga0.334As pseudo-tunnel junction 2472 (thickness: 36 nm, carrier concentration: 5.0 × 10¹⁹ / cm³) pseudo-tunnel junction 2472 was directly formed on the C-doped p-type Al0.137In0.529Ga0.334As pseudo-tunnel junction 2471. The p-type pseudo-tunnel junction 2471 was doped with C using CBr₄ as the doping gas. The n-type pseudo-tunnel junction 2472 was doped with Si using Si₂H₆ as the doping gas. Next, a Si-doped n-type In0.763Ga0.237As0.512P0.488 intermediate layer (thickness: 16 nm, carrier concentration: 1.5 × 10¹⁹ / cm³) was formed on the n-type pseudo-tunnel junction 2472.

[0083] On the pseudo-tunnel junction layer 247, a Si-doped second n-type InP semiconductor layer (thickness: 500 nm, carrier concentration: 1.5 × 10¹⁸ / cm³) is formed as a second n-type semiconductor layer 248, which serves as a spacer n-type intermediate layer. An undoped InP spacer layer (thickness: 100 nm) is then formed on top of this layer. Next, a second active layer 249 (total film thickness: 165 nm) having the same structure as the first active layer 244 is formed. Furthermore, an undoped In₀.₅²₂Al₀.₄₇₈As second electron blocking layer 251 (thickness: 20 nm) and an undoped InP spacer layer (thickness: 300 nm) are formed on the second active layer 249. Then, a Zn-doped second p-type InP cladding layer 252 (thickness: 2.4 μm, carrier concentration: 7.0 × 10¹⁷ / cm³) is formed as the second p-type semiconductor layer 250, and a p-type contact layer 253 is formed containing a Zn-doped p-type InP layer (thickness: 240 nm, carrier concentration: 1.5 × 10¹⁸ / cm³), a Zn-doped p-type In₀.749Ga₀.251As₀.543P₀.457 layer (thickness: 60 nm, carrier concentration: 5.0 × 10¹⁸ / cm³), and a Zn-doped p-type InGa₀.468As layer (thickness: 120 nm, carrier concentration: 1.5 × 10¹⁹ / cm³).

[0084] The composition, thickness, dopant type, and carrier concentration of each layer are recorded in Table 1 below. Furthermore, the carrier concentration refers to the designed impurity concentration during crystal growth. The impurity concentration values ​​used in the SIMS analysis described later are the impurity concentrations used in this invention.

[0085] [Table 1]

[0086] Next, using photoresist to cover the outermost p-type InGaAs layer of the p-type contact layer 253, excluding the area of ​​the p-type contact portion 263, a Ti (thickness: 10 nm) and Au (thickness: 530 nm) film is deposited as the electrode portion 265 using a vapor deposition method. The photoresist pattern outside the electrode portion 265 on the p-type contact portion 263 area is removed along with the metal film deposited thereon. After contact annealing, a photomask is formed on the electrode portion 265, leaving the p-type InGaAs layer in the area to be the p-type contact portion 263. This remaining p-type InGaAs layer is removed by wet etching using a tartaric acid-hydrogen peroxide water mixture. Using plasma CVD, a dielectric portion 261 (thickness: 700 nm) containing SiO2 is formed on the entire surface of the p-type contact layer 253. The dielectric portion 261 on the electrode portion 265 is removed by etching, forming an intermediate electrode layer 260 in which the dielectric portion 261 and the electrode portion 265 (and the p-type InGaAs contact portion 263) are arranged side by side. Next, a metal reflective layer 271 (Al (film thickness: 10 nm) / Au (film thickness: 650 nm) / Pt (film thickness: 100 nm) / Au (film thickness: 900 nm)) is formed on the intermediate electrode layer 260 by vapor deposition.

[0087] Then, a metal bonding layer 279 (Ti (film thickness: 650 nm) / Pt (film thickness: 20 nm) / Au (film thickness: 900 nm)) is formed on the support substrate (Si substrate) 280 by vapor deposition. Next, the metal reflective layer 271 and the metal bonding layer 279 are arranged facing each other and bonded by heat compression at 300°C to form the bonding layer 270. Then, the growth substrate 205 is wet-etched and removed using a diluted hydrochloric acid solution to expose the n-type InGaAs contact layer 241.

[0088] An Au (thickness: 10 nm) / Ge (thickness: 30 nm) / Au (thickness: 60 nm) / Ni (thickness: 30 nm) / Au (thickness: 800 nm) / Ti (thickness: 100 nm) / Au (thickness: 1000 nm) formation, designated as the upper surface ohmic electrode, is formed on the n-type InGaAs contact layer 241 using a vapor deposition method. A bonding pad electrode (Ti (thickness: 150 nm) / Pt (thickness: 100 nm) / Au (thickness: 2500 nm)) is then formed on the upper surface ohmic electrode using a vapor deposition method. The electrode pattern is formed using a resist stripping method. Finally, the n-type InGaAs contact layer 241, except for the area directly beneath the upper surface ohmic electrode, is removed by wet etching using a tartaric acid-hydrogen peroxide mixture.

[0089] Next, a photoresist mask based on photolithography is formed in a manner that covers the dicing area along the predetermined wafer dicing line and the ohmic electrode and pad electrode on the upper surface, and the upper surface roughening of the light extraction surface of the first n-type InP cladding 242 outside the masked area is performed based on wet etching.

[0090] Then, after SiO2 is formed over the entire surface by plasma CVD, a SiO2 mask is formed by resist-based mask patterning and etching, exposing the dicing area along the predetermined wafer dicing lines. The width of the dicing area exposed by the mask pattern is 55 μm. Mesa is formed by dry etching (ICP-RIE) to expose the outer periphery of the intermediate electrode layer 260 in the dicing area and the side surfaces of the semiconductor stack 220. The etching conditions are dry etching, stage temperature of 200°C, pressure of 0.2 Pa, bias power of 150 W, ICP power of 190 W, over-etching rate of 5%, and gas type ratio of SiCl4:Ar = 4:8.

[0091] After the mesa is formed, after removing the SiO2 mask present on the upper electrode 291, a SiN film (thickness: 190 μm) is deposited as a protective film 230 on the entire surface (including the upper surface of the remaining SiO2 mask and the exposed mesa side surface and cut-out area) using plasma CVD. Then, using a resist-based mask pattern, the SiN on the upper surface of the upper electrode 291 is removed by etching, and then the resist is removed. Next, the back side of the support substrate 280 is removed by grinding or etching, and the thickness of the double-layer stacked semiconductor light-emitting element 200 is set to 150 μm. Next, a back electrode 295 (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness: 200 nm)) is formed on the back side of the support substrate 280 by vapor deposition, and then subjected to rapid thermal annealing (RTA) at 300°C for 60 seconds. Finally, the individual components on a rectangle with a wafer size of 1080 μm × 1080 μm were separated by laser cutting to fabricate the double-layer stacked semiconductor light-emitting element 200 of Example 1.

[0092] (Example 2) The double-layer stacked semiconductor light-emitting element 200 of Example 2 is obtained in the same manner as in Example 1, except that the n-type InGaAsP intermediate layer (n-InGaAsP layer) and the p-type InGaAsP intermediate layer (p-InGaAsP layer) are not provided.

[0093] (Example 3) The flow rate of the doping gas (Si2H6) during the formation of the n-type pseudo-tunnel junction 2472 was set to 3200 sccm. Otherwise, the double-layer stacked semiconductor light-emitting element 200 of Example 3 was obtained in the same manner as in Example 1.

[0094] (Comparative Example 1) The growth temperature for forming the p-type pseudo-tunnel junction 2471 was set to 725°C instead of 750°C, and the layer was formed simultaneously by changing the temperature from 725°C to 630°C during growth. Furthermore, the dopant for the n-type pseudo-tunnel junction 2472 was Te, and DETe (diethyltellurium) was used as the dopant gas, formed simultaneously by changing the growth temperature from 725°C to 630°C at a flow rate of 10 sccm. Apart from these conditions, the double-layer stacked semiconductor light-emitting element 200 of Comparative Example 1 was obtained in the same manner as in Example 1. Hereinafter, the layer located in the pseudo-tunnel junction 247 of Comparative Example 1 will be simply referred to as the tunnel junction layer.

[0095] (Comparative Example 2) After forming the first p-type semiconductor layer 246 on the growth substrate 205 in the same manner as in Example 1, a p-type contact layer 253 is formed without forming a pseudo tunnel junction layer 247 or a second active layer 249. Otherwise, a single-layer stacked semiconductor light-emitting element of Comparative Example 2 is obtained in the same manner as in Example 1.

[0096] (Example 4) The composition of the first active layer 244 and the second active layer 249 is adjusted so that the light emission center wavelength is 1300 nm. Otherwise, the double-layer stacked semiconductor light-emitting element 200 of Example 4 is obtained in the same manner as in Example 1.

[0097] (Comparative Example 3) The composition of the first active layer 244 and the second active layer 249 was adjusted so that the light emission center wavelength was 1300 nm. Otherwise, the single-layer stacked semiconductor light-emitting element of Comparative Example 3 was obtained in the same manner as Comparative Example 2.

[0098] [Experiment 1] In Experiment 1, the performance of the pseudo-tunneling layer 247 of Examples 1 to 3 and the tunneling layer of Comparative Example 1 were evaluated. In order to conduct an evaluation related to the pure tunneling effect, the experiment was conducted in a manner in which the pseudo-tunneling layer 247 (or the tunneling layer) could be energized without separating the first active layer 244 and the second active layer 249, as follows.

[0099] Specifically, firstly, on a 2-inch p-type InP substrate, under the stated conditions, a first p-type semiconductor layer 246 (p-InP, 500 nm thick), a pseudo-tunnel junction layer 247 (or tunnel junction layer), and a second n-type semiconductor layer 248 (n-InP, 500 nm thick) are formed. Then, an n-type contact layer 241 (n-InGaAs, 24 nm thick) and an InP capping layer are grown sequentially (step A in Figure 8). The InP capping layer on the upper surface is etched using an etching solution of hydrochloric acid-acetic acid to expose the n-type contact layer 241 (step B in Figure 8). Next, after vapor deposition of the upper electrode except for the upper electrode pattern using photoresist, the photoresist and the metal film deposited on it are removed together to form the upper electrode (step C in Figure 8). Next, the area directly below and around the upper electrode of the n-type contact layer 241 is etched away to form a mesa covering the remaining n-type contact layer 241 and the upper electrode (step D in FIG. 8). Mesa etching is then performed by wet etching (etching solution: Br-MeOH) (step E in FIG. 8). After removing the mask, a back electrode is deposited on the back side of the p-type InP substrate (step F in FIG. 8). The fabricated device is used as device 10 for performance verification.

[0100] The performance verification component was placed on the stage of an LED tester (manufactured by YAC Garter, model: LX4730A), and the probe was brought into contact with the upper electrode and energized for 100 ms. Here, the upper electrode of the performance verification component 10 is circular with a diameter of 194.4 μm and an area of ​​29681 μm2. Furthermore, the stage is circular with a diameter of 235.2 μm and an area of ​​43447 μm2. The energizing results of each embodiment and Comparative Example 1 are shown in Figure 9. In addition, Table 2 shows the epitaxial structure, dopant, film thickness, and energizing results of the p-type pseudo-tunnel junction layer 2471 and n-type pseudo-tunnel junction layer 2472 of each embodiment. Moreover, the epitaxial structure, dopant, film thickness, and energizing results of the tunnel junction layer of Comparative Example 1 are also shown in Table 2. The SIMS impurity concentrations [cm⁻³] shown in Table 2 are not from the performance verification element 10, but rather a transcription of the impurity concentrations (peak values) measured by SIMS in Experiment 2, which will be described later.

[0101] [Table 2] Example 1 Example 2 Example 3 Comparative Example 1 p-type pseudo-tunneling layer p-type AlInGaAs p-type AlInGaAs p-type AlInGaAs p-type AlInGaAs p-type dopant CBr4 CBr4 CBr4 CBr4 Film thickness [nm] 36 36 36 36 SIMS impurity concentration [cm⁻³] 1.07×10¹⁹ 1.36×10¹⁹ 1.11×10¹⁹ 6.20×10¹⁹ n-type pseudo-tunneling layer n-type AlInGaAs n-type AlInGaAs n-type AlInGaAs n-type AlInGaAs n-type dopant Si2H6 Si2H6 Si2H6 DETe Film thickness [nm] 18 18 18 18 SIMS impurity concentration [cm⁻³] 1.65×10¹⁹ 1.83×10¹⁹ 1.80×10¹⁹ 1.48×10¹⁹ Resistance value [Ω]* 1.35 1.64 1.17 1.70 Current drop [mA] 1.29 0.68 0.82 0.81 Drop start voltage [V]** 0.10 0.12 0.12 0.28 Tunneling current (maximum) [mA] 2.48 1.56 4.94 67.63 The voltage at the end of the drop [V]** 0.30 0.30 0.26 0.38 The resistance value [Ω] is calculated by averaging the resistance values ​​when the voltage Vr is in the range of 0.2 V to 0.5 V. **The voltage at the start of the voltage drop [V] is the voltage at the beginning of the region where the current becomes extremely negative and the resistance becomes extremely small. The voltage at the end of the voltage drop [V] is the voltage at the end of the region where the current becomes extremely negative and the resistance becomes extremely small.

[0102] As can be seen from Figure 9 and Table 2, in Comparative Example 1, as in typical tunnel junctions, the maximum tunnel current (maximum current value) is as large as tens of mA, and tunnel junction characteristics with negative resistance can be obtained. In contrast, in Examples 1 to 3, the starting point of the negative resistance region (the point where the current becomes extremely large) in the IV curve is between 0.02 V and 0.2 V, and the maximum tunnel current (maximum current value) is less than 7 mA, confirming a phenomenon different from the previously thought behavior.

[0103] [Experiment 2] In Experiment 2, the output characteristics of the double-layer stacked semiconductor light-emitting elements 200 fabricated in Examples 1-4 and Comparative Example 1, and the single-layer stacked semiconductor light-emitting elements fabricated in Comparative Examples 2-3 were measured. Furthermore, SIMS analysis was performed on Examples 1-3 and Comparative Examples 1-2 to determine the impurity concentration. Table 3 shows the luminous output power Po [mW] and forward voltage Vf [V] of the double-layer stacked semiconductor light-emitting elements 200 fabricated in Examples 1-4 and Comparative Example 1, and the single-layer stacked semiconductor light-emitting elements fabricated in Comparative Examples 2-3, when a current of 30 mA, 100 mA, and 1 A is applied. Additionally, the leakage current Ir [A] and reverse voltage Vr [V] are also shown when a voltage of 5 V and 10 V is applied. Figure 10 is a graph showing the current-luminous output characteristics of Examples 1-3 and Comparative Examples 1-2 (elements with a target wavelength band of 1500 nm).

[0104] [Table 3] Target wavelength band Po (30 mA) Po(100 mA) Po(1 A) Vf (30 mA) Vf (100 mA) Ir(5 V) Ir(10 V) Vr(0.1 μA) Vr(1 μA) [nm band] [mW] [mW] [mW] [V] [V] [A] [A] [V] [V] Example 1 1500 10.3 35.0 194.4 1.53 1.68 1.0×10-10 1.3×10⁻⁹ 29.3 30.0 Example 2 1500 10.4 34.8 200.9 1.53 1.69 1.0×10-10 1.0×10-10 30.0 30.0 Example 3 1500 11.3 36.6 202.9 1.50 1.64 1.0×10-10 1.0×10-10 30.0 30.0 Example 4 1300 11.8 41.6 255.7 1.64 1.77 1.0×10-10 1.0×10-10 30.0 30.0 Comparative Example 1 1500 10.0 30.7 161.8 1.4 1.53 6.5×10⁻⁹ 4.8×10⁻⁸ 12.8 23.8 Comparative Example 2 1500 7.6 21.3 106.3 0.71 0.79 1.0×10-10 1.8×10⁻⁸ 15.6 17.8 Comparative Example 3 1300 8.9 27.6 - 0.84 0.89 1.0×10-10 1.0×10-8 19.8 25.3

[0105] As can be seen from Table 3 and Figure 10, when a current of 1 A flows, the luminous output power of Examples 1 to 3, where the dopant of the n-type pseudo-tunnel junction 2472 is Si, is 1.8 to 1.9 times that of Comparative Example 2, which is a single-layer stacked type, and 1.6 to 1.7 times that of Comparative Example 2, where the dopant of the n-type pseudo-tunnel junction 2472 is Te, when a current of 1 A flows, is approximately 1.5 times that of Comparative Example 2, which is a single-layer stacked type, and approximately 1.4 times that of Comparative Example 2, where the dopant of the n-type pseudo-tunnel junction 2472 is Te, and approximately 1.4 times that of Comparative Example 2, which is a single-layer stacked type, when the current flows, the greater the improvement in luminous output power of this embodiment. It is also believed that this embodiment has the effect of suppressing the power drop caused by heat generation when a large current flows. Compared with ordinary tunnel junctions, the pseudo-tunnel junction 247 of the present invention makes it easier for the current to diffuse in the in-plane direction, and can suppress the heat generation caused by current concentration. Furthermore, in Examples 1-3, the leakage current Ir when a reverse voltage of 5 V was flowing was 1.0 × 10⁻¹⁰ A, which was 1 / 65th of that in Comparative Example 1 (6.5 × 10⁻⁹ A), clearly demonstrating a reduction in leakage current. Compared to Comparative Example 1 and the single-layer stacked type Comparative Example 2, the leakage current Ir when a reverse voltage of 10 V was flowing in Examples 1-3 was also reduced. Additionally, in Examples 1-3, the reverse voltage Vr when a reverse voltage of 0.1 μA or 1 μA was flowing was approximately 30 V, clearly demonstrating an increase in reverse voltage compared to Comparative Example 1 or the single-layer stacked type Comparative Example 2. These effects of increased light output power, reduced leakage current, and increased reverse voltage were also confirmed in a comparison between Example 4 (with different wavelengths) and Comparative Example 3 (with a single-layer stacked type).

[0106] Figures 11-14 show the results of SIMS analysis for Examples 1-3 and Comparative Example 1, respectively. In these figures, the horizontal axis range is set to include the entire region of the second active layer 249 and the first active layer 244 to indicate the degree of n-type dopant diffusion. Table 4 also shows the average impurity concentrations of the second active layer 249, the first active layer 244, and the n-type InP layer of Examples 1-3, the maximum impurity concentration (peak value) of the pseudo-tunnel junction layer 247 (tunnel junction (TJ)), and the maximum impurity concentration (peak value) of the n-type dopant on the TJ side of the second active layer 249, as read from the SIMS analysis results. Table 4 also shows the average impurity concentrations of the second active layer 249, the first active layer 244, and the n-type InP layer of Comparative Example 1, the maximum impurity concentration (peak value) of the tunnel junction layer (TJ), and the maximum impurity concentration (peak value) of the n-type dopant on the TJ side of the second active layer 249.

[0107] In the SIMS profiles shown in Figures 11-14, the additional method for defining the boundary line between the second active layer 249 (i-InGaAlAs) and the spacer layer (i-InP), as illustrated by the dashed line, will be explained. The boundary line is located at the center of the difference in the variation of the As profile at a point where it drops sharply. Based on this As profile, the region from the center of the second active layer 249 in the thickness direction to the boundary of the other layer (spacer layer) adjacent to the n-type pseudo-tunnel junction layer 2472 side of the second active layer 249 is defined as the TJ side of the second active layer 249.

[0108] [Table 4] C Si Te p-type TJ (Peak) Second active layer (average value) n-InP(n) n-type TJ (Peak) First active layer (average value) Second active layer (average value) n-type TJ (Peak) First active layer (average value) TJ side of the second active layer (Peak) Example 1 1.07×10¹⁹ 8.61×10¹⁴ 9.8×10¹⁷ 1.65×10¹⁹ 4.86×10¹⁵ 1.37×10¹⁴ 1.11×10¹⁴ 2.30×10¹⁴ 6.34×10¹⁵ (Si) Example 2 1.36×10¹⁹ 1.10×10¹⁵ 9.7×10¹⁷ 1.83×10¹⁹ 2.31×10¹⁵ 1.28×10¹⁴ 1.12×10¹⁴ 1.24×10¹⁴ 5.80×10¹⁵ (Si) Example 3 1.11×10¹⁹ 1.03×10¹⁵ 8.9×10¹⁷ 1.80×10¹⁹ 3.69×10¹⁵ 2.46×10¹⁴ 1.43×10¹⁴ 1.32×10¹⁴ 6.40×10¹⁵ (Si) Comparative Example 1 6.20×10¹⁹ 1.74×10¹⁵ 1.3×10¹⁸ 6.39×10¹⁴ 1.23×10¹⁵ 2.51×10¹⁶ 1.48×10¹⁹ 2.53×10¹⁴ 3.30×10¹⁷ (Te)

[0109] The Si impurity concentration in the second active layer 249 of Examples 1 to 3, calculated as the maximum value (peak value) on the n-type pseudo-tunnel junction 2472 side, is 1.0 × 10¹⁶ atoms / cm³ or less, and the average value of the second active layer 249 as a whole is 5.0 × 10¹⁵ atoms / cm³ or less. On the other hand, the Te impurity concentration in the second active layer 249 of Comparative Example 1 exceeds 1.0 × 10¹⁶ atoms / cm³ in most of the second active layer 249. Furthermore, in Comparative Example 1, a large peak with a Te concentration of 3.3 × 10¹⁷ atoms / cm³ exists in the barrier layer on the TJ side of the second active layer 249. The peak values ​​of impurity concentration (Si) in the n-type pseudo-tunneling layer 2472 of Examples 1 to 3 were 1.65 × 10¹⁹ cm⁻³ to 1.83 × 10¹⁹ cm⁻³, while the peak value of impurity concentration (Te) in the n-type tunneling layer of Comparative Example 1 was 1.48 × 10¹⁹ cm⁻³. The fact that the peak value of impurity concentration in the n-type tunneling layer of Comparative Example 1 was less than that in the n-type pseudo-tunneling layer 2472 of Examples 1 to 3 can be presumably attributed to the shift of Te towards the second active layer in Comparative Example 1.

[0110] Based on the results of these SIMS analyses and the output characteristic measurements shown in Table 3, it is concluded that when Te is used as the n-type dopant in the tunnel junction layer, the diffusion of Te as an impurity into the second active layer 249 causes a decrease in output power. In contrast, when Si is used as the n-type dopant, although it becomes a pseudo-tunnel junction layer exhibiting behavior different from a typical tunnel junction according to the results of Experiment 1, it is less likely to cause a decrease in power because Si does not easily diffuse into the second active layer 249.

[0111] As described above, by satisfying the conditions of this invention, a double-layer stacked semiconductor light-emitting device with good output characteristics, reduced leakage current, and increased reverse voltage can be provided. The behavior of the pseudo-tunnel junction based on this invention is significantly different from that of previously thought tunnel junctions.

[0112] 10: Components for performance verification 100, 200: Double-layer stacked semiconductor light-emitting elements 105, 205: Substrates for growth 120, 220: Semiconductor stack 140, 240: First n-type semiconductor layer 141: n-type contact layer 142: First n-type cladding 144, 244: First active layer 144b: Barrier layer of the first active layer (barrier layer) 144w: The first active layer is the well layer (well layer) 145, 245: First electron blocking layer 146, 246: First p-type semiconductor layer 147, 247: Pseudo-tunnel layer 148, 248: Second n-type semiconductor layer 149, 249: Second active layer 149b, 249b: Barrier layer of the second active layer 149w, 249w: Trap layer of the second active layer 150, 250: Second p-type semiconductor layer 151, 251: Second electron blocking layer 152: Second p-type cladding 153, 253: p-type contact layer 163: P-type contact 191, 291: Upper electrode 195, 295: Back electrode 230: Protective film 241: n-type contact layer (n-type In0.532Ga0.468As contact layer, n-type InGaAs contact layer) 242: First n-type cladding (First n-type InP cladding) 244b: Barrier layer of the first active layer (In0.765Ga0.125Al0.110As barrier layer) 244w: The first active layer is a well layer (In0.419Ga0.297Al0.284As well layer). 252: Second p-type cladding (Second p-type InP cladding) 260: Intermediate electrode layer 261: Dielectric Section 263: p-type contact (p-type InGaAs contact) 265: Electrode section 270: Bonding layer 271: Metallic reflective layer 279: Metal bonding layer 280: Support substrate (Si substrate) 1471: P-type pseudo-tunneling layer 1472: n-type pseudo-tunneling layer 2471: p-type pseudo-tunneling layer (p-type Al0.137In0.529Ga0.334As pseudo-tunneling layer) 2472: n-type pseudo-tunneling layer (n-type Al0.137In0.529Ga0.334As pseudo-tunneling layer) If: Forward current Vf: Forward voltage

Claims

1. A double-layer stacked semiconductor light-emitting element, characterized in that it comprises, in sequence: First n-type semiconductor layer; The first active layer is undoped; A p-type pseudo-tunnel junction layer having a p-type dopant; an n-type pseudo-tunnel junction layer disposed on the p-type pseudo-tunnel junction layer having an n-type dopant; an undoped second active layer; and a second p-type semiconductor layer, wherein the maximum impurity concentration of the n-type dopant contained on the n-type pseudo-tunnel junction layer side of the second active layer is less than 1.0 × 10¹⁶ atoms / cubic centimeter.

2. The double-layer stacked semiconductor light-emitting element as described in claim 1, wherein, Between the n-type pseudo-tunnel junction layer and the second active layer, there is a second n-type semiconductor layer with a Si impurity concentration of 5.0 × 10¹⁷ atoms / cm³ or higher and 5.0 × 10¹⁸ atoms / cm³ or lower.

3. The double-layer stacked semiconductor light-emitting element as described in claim 1, wherein, The average impurity concentration of the n-type dopant contained in the first active layer and the second active layer is less than 5.0 × 10¹⁵ atoms / cubic centimeter.

4. The double-layer stacked semiconductor light-emitting element as described in claim 1, wherein, The n-type dopant in the n-type pseudo-tunnel junction is Si.

5. The double-layer stacked semiconductor light-emitting element as described in claim 1, wherein, The p-type dopant in the p-type pseudo-tunnel junction is C.

6. The double-layer stacked semiconductor light-emitting element as described in claim 1, wherein, The impurity concentration of the n-type dopant in the n-type pseudo-tunnel junction is above 1.5 × 10¹⁹ atoms / cubic centimeter.

7. The double-layer stacked semiconductor light-emitting element as claimed in claim 1, wherein, The impurity concentration of the p-type dopant in the p-type pseudo-tunnel junction is above 1.0 × 10¹⁹ atoms / cubic centimeter.

8. The double-layer stacked semiconductor light-emitting element as claimed in claim 1, wherein, The first active layer, the second active layer, the p-type pseudo-tunneling layer, and the n-type pseudo-tunneling layer contain AlGaInAs or InGaAsP.

9. The double-layer stacked semiconductor light-emitting element as claimed in claim 1, wherein, In the current-voltage curves when the p-type pseudo-tunneling layer and the n-type pseudo-tunneling layer are energized without passing through the first active layer and the second active layer, the points where the current becomes extremely large are in the range of above 0.02 V and below 0.2 V.

10. The double-layer stacked semiconductor light-emitting element as claimed in claim 1, wherein, In the current-voltage curves of the p-type pseudo-tunnel junction and the n-type pseudo-tunnel junction without passing through the first active layer and the second active layer, the maximum value of the current is less than 7 mA.

11. A method for manufacturing a double-layer stacked semiconductor light-emitting element, comprising: The step of forming a first n-type semiconductor layer on a substrate; The step of forming an undoped first active layer on the first n-type semiconductor layer; The steps include: forming a p-type pseudo-tunnel junction layer with p-type dopant on the first active layer; forming an n-type pseudo-tunnel junction layer with n-type dopant directly on the p-type pseudo-tunnel junction layer; forming an undoped second active layer on the n-type pseudo-tunnel junction layer; and forming a second p-type semiconductor layer on the second active layer, wherein the maximum value of the impurity concentration of the n-type dopant contained in the n-type pseudo-tunnel junction layer side of the second active layer is set to 1.0 × 10¹⁶ atoms / cubic centimeter or less.

12. A double-layer stacked semiconductor light-emitting element, comprising: Support substrate; A bonding layer is disposed on the supporting substrate; The intermediate electrode layer is formed by placing the dielectric portion and the electrode portion side by side on the bonding layer; A second p-type semiconductor layer is disposed on the intermediate electrode layer; an undoped second active layer is disposed on the second p-type semiconductor layer; an n-type pseudo-tunnel junction layer is disposed on the second active layer and has an n-type dopant; a p-type pseudo-tunnel junction layer is disposed on the n-type pseudo-tunnel junction layer and has a p-type dopant; an undoped first active layer is disposed on the p-type pseudo-tunnel junction layer; and a first n-type semiconductor layer is disposed on the first active layer. The upper electrode is disposed on the first n-type semiconductor layer, and the maximum impurity concentration of the n-type dopant contained in the n-type pseudo-tunnel junction layer side of the second active layer is less than 1.0 × 10¹⁶ atoms / cubic centimeter.

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