Semiconductor structure and method for forming the same

Abstract

A semiconductor structure is provided herein. The semiconductor structure includes a stack, a top dielectric layer, and an active structure. The stack includes a plurality of gate layers and a plurality of dielectric layers alternately disposed thereon. The top dielectric layer is disposed on the stack. The active structure extends vertically through the top dielectric layer and the stack. The active structure includes a memory layer, a channel layer, and at least one separator. The memory layer forms the outermost layer of the active structure. The channel layer is disposed inside the memory layer. The separator is embedded in the channel layer. The height of the separator falls between the upper and lower surfaces of the top dielectric layer.

Claims

1. A semiconductor structure, comprising: The stack comprises a plurality of gate layers and a plurality of dielectric layers alternately arranged on each other; a top dielectric layer is disposed on the stack; The active structure extends vertically through the top dielectric layer and the stack, and includes: a memory layer forming the outermost layer of the active structure; a channel layer disposed inside the memory layer; at least one partition embedded in the channel layer; and a dielectric material disposed inside the channel layer. A positioning post is disposed in the center portion of the dielectric material; and two conductive posts penetrate the dielectric material on both sides of the positioning post, wherein the height of the partition falls between the upper and lower surfaces of the top dielectric layer.

2. The semiconductor structure as described in claim 1, wherein, The separator extends laterally and is embedded in the memory layer.

3. The semiconductor structure as described in claim 2, wherein, The separator separates the memory layer and the channel layer into two or more cut sections between the upper and lower surfaces of the top dielectric layer, each separator having a rectangular or circular cross-section on the upper surface of the top dielectric layer.

4. The semiconductor structure as described in claim 2, wherein, A single dividing section spans the active structure, separating the memory layer and the channel layer into two cut-off portions between the upper and lower surfaces of the top dielectric layer, wherein the active structure has a substantially semi-circular cross-section on the upper surface of the top dielectric layer.

5. The semiconductor structure as described in claim 2, wherein, Two or more of the partitions, spaced apart from each other, separate the memory layer and the channel layer into a plurality of cut-off portions between the upper and lower surfaces of the top dielectric layer.

6. The semiconductor structure as described in claim 1, wherein, The distance between the upper and lower surfaces of the top dielectric layer is 1.5 to 3 times the total thickness of the dielectric layer and the gate layer.

7. The semiconductor structure as described in claim 1, wherein, The channel layer has a first region and a second region, the first region being in contact with the conductive pillar and the second region not being in contact with the conductive pillar, wherein the partition is disposed in the second region.

8. A method for forming a semiconductor structure, comprising: A starting structure is provided, the starting structure including a bottom structure, a stack, and a top dielectric layer, the stack being formed on the bottom structure, the stack including a plurality of first layers and a plurality of second layers alternately disposed thereon, and the top dielectric layer being formed on the stack; The method of forming an active structure that vertically penetrates the top dielectric layer and the stack includes: forming a first opening that vertically penetrates the top dielectric layer and the stack; forming a memory layer on the sidewall of the first opening; forming a channel layer on the memory layer; filling the first opening with a dielectric material; forming a positioning post in the center portion of the dielectric material; forming two conductive posts on both sides of the positioning post 170 that penetrate the dielectric material; and forming at least one partition embedded in the channel layer, wherein the height of the partition falls between the upper and lower surfaces of the top dielectric layer.

9. A method for forming a semiconductor structure as described in claim 8, wherein, The separator extends laterally and is embedded in the memory layer.

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