Memory device and memory system

Abstract

The memory device includes a plurality of memory blocks for storing first stored data and comparing the first stored data with first input data to generate a first current signal. The memory blocks include a plurality of memory strings coupled to each other for generating a plurality of string current signals. The memory blocks add the string current signals to generate the first current signal, and the current level of the first current signal is proportional to a difference between an input value of the first input data and a stored value of the first stored data.

Claims

1. A memory device comprising a plurality of memory blocks for storing first stored data and for comparing the first stored data with first input data to generate a first current signal, the memory blocks comprising: a plurality of memory strings coupled to each other for generating a plurality of string current signals, wherein the memory blocks are used to add the string current signals to generate the first current signal, the current level of the first current signal being proportional to a difference between an input value of the first input data and a stored value of the first stored data, each string current signal in a first portion of the string current signals having a first current level when there is a first difference between the input value of the first input data and the stored value of the first stored data, and the number of string current signals in the first portion being equal to the first difference.

2. The memory device as claimed in claim 1, wherein the memory strings are configured to receive a plurality of string select line signals, the string select line signals including a first string select line signal and a second string select line signal, each of the first string select line signal and the second string select line signal having a first voltage level when the first input data has a first input value, each of the first string select line signal and the second string select line signal having the first voltage level and a second voltage level respectively when the first input data has a second input value, and each of the first string select line signal and the second string select line signal having the second voltage level when the first input data has a third input value.

3. The memory device as claimed in claim 2, wherein the second voltage level is lower than the first voltage level, and the second input value is lower than the first input value and greater than the third input value.

4. The memory device as claimed in claim 1, wherein the first stored data includes at least a first stored data bit and a second stored data bit, the memory strings include a first switching element for storing the first stored data bit and a second switching element for storing the second stored data bit, each of the first switching element and the second switching element having a first threshold voltage level when the first stored data has a first stored value, each of the first switching element and the second switching element having the first threshold voltage level and a second threshold voltage level respectively when the first stored data has a second stored value, and each of the first switching element and the second switching element having the second threshold voltage level when the first stored data has a third stored value.

5. The memory device as claimed in claim 4, wherein the second threshold voltage level is lower than the first threshold voltage level, and the second stored value is lower than the first stored value and greater than the third stored value.

6. The memory device as claimed in claim 1, wherein when there is a second difference between the input value of the first input data and the stored value of the first stored data, each of the string current signals in a second portion of the string current signals has the first current level, the number of string current signals in the second portion is equal to the second difference, and the second difference is greater than the first difference.

7. The memory device as claimed in claim 1, wherein the memory strings are configured to receive a plurality of string select line signals, the string select line signals including a first string select line signal and a second string select line signal, wherein when the first input data has a first input value, the first string select line signal and the second string select line signal respectively have a first voltage level and a second voltage level, and when the first input data has a second input value, the first string select line signal and the second string select line signal respectively have the second voltage level and the first voltage level.

8. The memory device as claimed in claim 7, wherein the second voltage level is greater than the first voltage level, and the second input value is greater than the first input value.

9. The memory device as claimed in claim 7, wherein the memory strings comprise: a first switching element for receiving a first string select line signal; a second switching element for receiving a second string select line signal; a third switching element connected in series with the first switching element; and a fourth switching element connected in series with the second switching element, wherein the third switching element is turned off and the fourth switching element is turned on when the first stored data has a first stored value, and the third switching element is turned on and the fourth switching element is turned off when the first stored data has a second stored value.

10. The memory device as claimed in claim 9, wherein the memory strings further include: a fifth switching element for receiving a third string select line signal among the string select line signals; and a sixth switching element for receiving a fourth string select line signal among the string select line signals, wherein when the first input data has the first input value, the third string select line signal and the fourth string select line signal respectively have the second voltage level and the first voltage level.

11. The memory device as claimed in claim 10, wherein the memory strings further comprise: a seventh switching element coupled in series with the fifth switching element; and an eighth switching element coupled in series with the sixth switching element, wherein the seventh switching element is turned off and the eighth switching element is turned on when the first stored data has a third stored value, and the seventh switching element is turned on and the eighth switching element is turned off when the first stored data has the second stored value.

12. A memory device comprising: a plurality of memory strings coupled to each other, configured to generate a plurality of string current signals and to sum the string current signals to generate a first current signal, wherein the memory strings include a first switch element group and a second switch element group, the first switch element group being configured to receive a plurality of string select line signals, the string select line signals being configured to carry first input data, the second switch element group being configured to store first stored data, the current level of the first current signal being proportional to a difference between an input value of the first input data and a stored value of the first stored data, the first switch element group including a first switch element and a second switch element, the second switch element group including a third switch element and a fourth switch element, the first switch element and the second switch element being connected in series with the third switch element and the fourth switch element respectively, and each of the third switch element and the fourth switch element being turned off in response to the input value being equal to the stored value when each of the first switch element and the second switch element is turned on.

13. The memory device as claimed in claim 12, wherein when each of the first and second switching elements is turned on, the third switching element is turned on in response to the input value being greater than the stored value, and when each of the first and second switching elements is turned on, the fourth switching element is turned on in response to the input value being less than the stored value.

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