Semiconductor device and method of fabricating the same
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- UNITED MICROELECTRONICS CORP
- Filing Date
- 2025-06-13
- Publication Date
- 2026-08-01
Smart Images

Figure TWG2TB001904000_001 
Figure TWG2TB001904000_002 
Figure TWG2TB001904000_003
Abstract
Claims
1. A semiconductor device comprising: a substrate; a plurality of conductive pillars disposed on the substrate; a plurality of liquid crystal layers disposed alternately with the conductive pillars in a horizontal direction on the substrate; and a first dielectric barrier layer disposed on one sidewall of each of the conductive pillars, wherein... The first dielectric barrier layer is doped with titanium or tantalum ions.
2. The semiconductor device as described in claim 1, further comprising: A high dielectric constant dielectric layer covers the first dielectric barrier layer and the conductive pillars.
3. The semiconductor device as described in claim 2, wherein, The high dielectric constant dielectric layer is in direct contact with one of the top surfaces of the conductive pillars.
4. The semiconductor device as described in claim 2, wherein, The high dielectric constant dielectric layer comprises a stacked structure of zirconium oxide, aluminum oxide, or zirconium oxide-alumina-zirconia.
5. The semiconductor device as described in claim 1, further comprising: A first dielectric layer is disposed around a metal interconnect, the metal interconnect being disposed between the substrate and one of the conductive pillars; And a second dielectric barrier layer is disposed on one sidewall of the metal interconnect, wherein the second dielectric barrier layer is doped with titanium ions or tantalum ions.
6. The semiconductor device as described in claim 5, wherein, The doping concentration of the titanium ion or the tantalum ion in the second dielectric barrier layer or the first dielectric barrier layer is between 0.1 ppm and 1 ppm.
7. The semiconductor device as described in claim 5, further comprising: A second dielectric layer surrounds a plug, which is disposed between the metal interconnect and one of the conductive pillars, wherein the plug and the conductive pillar are integrally formed.
8. The semiconductor device as described in claim 7, wherein, The first dielectric barrier layer is also disposed on one side wall of the plug.
9. The semiconductor device as described in claim 5, further comprising: A reflective layer is disposed within the first dielectric layer, wherein a portion of the conductive pillars are disposed on the reflective layer.
10. The semiconductor device as described in claim 9, wherein, The second dielectric barrier layer is also disposed on one bottom surface and one side wall of the reflective layer.
11. The semiconductor device as described in claim 7, further comprising: A third dielectric layer is disposed on the second dielectric layer and located below the conductive pillars and the liquid crystal layers, wherein the third dielectric layer directly contacts the bottom surface of each conductive pillar.
12. The semiconductor device as described in claim 11, wherein, The third dielectric layer is in direct contact with the first dielectric barrier layer disposed on the sidewall of each conductive pillar.
13. A method for forming a semiconductor device, comprising: Provide a base; A plurality of conductive pillars are formed on the substrate; a plurality of liquid crystal layers are formed on the substrate, the liquid crystal layers being alternately arranged with the conductive pillars in a horizontal direction; and a first dielectric barrier layer is formed on one sidewall of each of the conductive pillars, wherein the first dielectric barrier layer is doped with titanium ions or tantalum ions.
14. The method for forming a semiconductor device as described in claim 13, wherein, Forming the first dielectric barrier layer includes: forming a plurality of first openings in a sacrificial layer above the substrate; performing a first chemical vapor deposition process in the first openings; and simultaneously doping the titanium ions or the tantalum ions during the first chemical vapor deposition process to form the first dielectric barrier layer in the first openings.
15. The method of forming a semiconductor device as described in claim 14, wherein, It also includes: after forming the first dielectric barrier layer, forming the conductive pillars within the first openings; removing the sacrificial layer to form a plurality of second openings; and forming the liquid crystal layers within the second openings respectively.
16. The method of forming a semiconductor device as described in claim 15, wherein, Before forming the liquid crystal layers, the method further includes: forming a high dielectric constant dielectric layer on the first dielectric barrier layer and the conductive pillars, wherein the high dielectric constant dielectric layer directly contacts a top surface of the conductive pillars.
17. The method for forming a semiconductor device as described in claim 14, wherein, Prior to forming the sacrificial layer, the process further includes: forming a first dielectric layer on the substrate; forming an interconnect opening within the first dielectric layer; performing a second chemical vapor deposition process on the first dielectric layer; simultaneously doping the titanium ions or the tantalum ions during the second chemical vapor deposition process to form a second dielectric barrier layer within the interconnect opening; and after forming the second dielectric barrier layer, forming a metal interconnect within the interconnect opening, located between the substrate and one of the conductive pillars.
18. The method of forming a semiconductor device as described in claim 17, wherein, During the first chemical vapor deposition process and the second chemical vapor deposition process, the doping concentration of the titanium ion or the tantalum ion is between 0.1 ppm and 1 ppm.
19. The method for forming a semiconductor device as described in claim 17, further comprising, prior to the formation of the sacrificial layer: A second dielectric layer is formed on the first dielectric layer; A contact hole is formed in the second dielectric layer, which is interconnected with one of the first openings, wherein the first chemical vapor deposition process is also performed simultaneously in the contact hole; and after the first dielectric barrier layer is formed, a plug is formed in the contact hole, located between the metal interconnect and one of the conductive pillars.
20. A method for forming a semiconductor device as described in claim 19, wherein, The first dielectric barrier layer also covers one sidewall of the plug, and the plug is integrally formed with one of the conductive pillars.