Semiconductor device and method for fabricating the same

Abstract

This invention discloses a method for manufacturing a semiconductor device, which mainly involves providing a first wafer and a second wafer, wherein the first wafer includes a metal-oxide-semiconductor transistor and the second wafer includes a first memory element, then bonding the second wafer to the first wafer, and then bonding a third wafer to the second wafer, wherein the third wafer includes a second memory element.

Claims

1. A method for fabricating a semiconductor device, characterized in that it comprises: providing a first wafer and a second wafer, wherein the first wafer includes a metal-oxide-semiconductor transistor and the second wafer includes a first memory device, the second wafer including a first NAND structure disposed on a second substrate, a second dielectric layer disposed on the first NAND structure, and a second hybrid bonding structure disposed on the second dielectric layer; bonding the second wafer to the first wafer; grinding the second substrate; forming a second silicon through-hole in the second substrate and the second dielectric layer; forming a third hybrid bonding structure on the second substrate; and bonding a third wafer to the third hybrid bonding structure of the second wafer, wherein the third wafer includes a second memory device.

2. The method as described in claim 1, wherein the first wafer comprises: a metal-oxide-semiconductor transistor disposed on a first substrate; a first dielectric layer disposed on the metal-oxide-semiconductor transistor; a metal interconnect disposed within the first dielectric layer; and a first hybrid bonding structure disposed on the first dielectric layer.

3. The method as described in claim 2 further includes forming a first silicon through-hole in the first substrate and a portion of the first dielectric layer.

4. The method as described in claim 1, wherein the third wafer comprises: a second NAND structure disposed on a third substrate; a third dielectric layer disposed on the second NAND structure; and a fourth hybrid bonding structure disposed on the third dielectric layer.

5. The method as described in claim 1 further includes bonding the second wafer and the first wafer using a hybrid bonding process.

6. The method as described in claim 1 further includes bonding the third wafer and the second wafer using a hybrid bonding process.

7. A semiconductor device, characterized in that it comprises: a second wafer bonded to a first wafer, wherein the first wafer includes a metal-oxide-semiconductor transistor and the second wafer includes a first memory element, the second wafer including a first NAND structure disposed on a second substrate, a second dielectric layer disposed on the first NAND structure, and a second hybrid bonding structure disposed on the second dielectric layer; a second silicon through-hole disposed in the second substrate and the second dielectric layer; a third hybrid bonding structure disposed on the second substrate; and a third wafer bonded to the third hybrid bonding structure of the second wafer, wherein the third wafer includes a second memory element.

8. The semiconductor device as described in claim 7, wherein the first wafer comprises: a metal-oxide-semiconductor transistor disposed on a first substrate; a first dielectric layer disposed on the metal-oxide-semiconductor transistor; a metal interconnect disposed within the first dielectric layer; and a first hybrid bonding structure disposed on the first dielectric layer.

9. The semiconductor device as described in claim 8 further includes a first silicon through-hole disposed in the first substrate and a portion of the first dielectric layer.

10. The semiconductor device as described in claim 7, wherein the first hybrid bonding structure is connected to the second hybrid bonding structure.

11. The semiconductor device as described in claim 7, wherein the third wafer comprises: a second NAND structure disposed on a third substrate; a third dielectric layer disposed on the second NAND structure; and a fourth hybrid bonding structure disposed on the third dielectric layer.

12. The semiconductor device as described in claim 11, wherein the third hybrid bonding structure is connected to the fourth hybrid bonding structure.

13. The semiconductor device as described in claim 7, wherein the front side of the second wafer faces the front side of the first wafer.

14. The semiconductor element as described in claim 7, wherein the front side of the third wafer faces the back side of the second wafer.

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