Multi-gate ferroelectric memory and memory array device
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- NATIONAL TSING HUA UNIVERSITY
- Filing Date
- 2025-06-27
- Publication Date
- 2026-08-01
Smart Images
Figure TWG2TB001904033_001 
Figure TWG2TB001904033_002 
Figure TWG2TB001904033_003
Abstract
Claims
1. A multi-gate ferroelectric memory, comprising: A fin-shaped channel layer; A front dielectric layer is disposed on one side of the fin-shaped channel layer; A back-side dielectric layer is disposed on the opposite side of the fin channel layer relative to one side of the fin channel layer; a front-side gate is attached to the front-side dielectric layer and located away from the fin channel layer; a back-side gate is attached to the back-side dielectric layer and located away from the fin channel layer, wherein the back-side gate is configured to be connected to a bit line; and a ferroelectric capacitor is connected to the front-side gate, wherein the ferroelectric capacitor is configured to be connected to a word line.
2. The multi-gate ferroelectric memory as claimed in claim 1, wherein the front dielectric layer and the back dielectric layer are made of a high dielectric constant material, wherein the dielectric constant of the high dielectric constant material is greater than 4.
3. The multi-gate ferroelectric memory as claimed in claim 2, wherein the high dielectric constant material comprises silicon nitride or nonferroelectric HfO2.
4. The multi-gate ferroelectric memory as claimed in claim 2, wherein the effective oxide thickness of the front dielectric layer and the effective oxide thickness of the back dielectric layer are between 1.0 and 1.5 nanometers.
5. The multi-gate ferroelectric memory as claimed in claim 1, wherein the front gate and the back gate comprise at least one of titanium nitride, tungsten, and polysilicon.
6. The multi-gate ferroelectric memory as claimed in claim 1, wherein the ferroelectric capacitor comprises: A first electrode, a second electrode, and a ferroelectric layer between the first electrode and the second electrode, wherein the first electrode is electrically connected to the front gate, and wherein the second electrode is electrically connected to the character line.
7. The multi-gate ferroelectric memory as claimed in claim 6, wherein the ferroelectric layer is a hafnium oxide doped layer.
8. The multi-gate ferroelectric memory as claimed in claim 6, wherein the ferroelectric layer is doped with at least one of zirconium and aluminum.
9. The multi-gate ferroelectric memory as claimed in claim 1, wherein the ferroelectric capacitor is disposed on the front gate.
10. The multi-gate ferroelectric memory as claimed in claim 1, wherein the ferroelectric capacitor is disposed adjacent to the front gate.
11. The multi-gate ferroelectric memory as claimed in claim 10, wherein the ferroelectric capacitor is connected to the front gate via an internal interconnect.
12. The multi-gate ferroelectric memory as claimed in claim 1, wherein the width of the ferroelectric capacitor is between 50% and 100% of the width of the front gate.
13. A memory array device, comprising: Multiple multi-gate ferroelectric memories as described in claim 1 are configured as an array; A plurality of word lines, wherein each word line is connected to a ferroelectric capacitor of a portion of the plurality of multi-gate ferroelectric memories, wherein the portions of multi-gate ferroelectric memories connected to the same word line are arranged along a first direction of the array; and a plurality of bit lines, wherein each bit line is connected to a back gate of a portion of the plurality of multi-gate ferroelectric memories, wherein the portions of multi-gate ferroelectric memories connected to the same bit line are arranged along a second direction of the array, wherein the second direction is different from the first direction.