3D dynamic random access memory and method of manufacturing the same

Abstract

A 3D dynamic random access memory (DRAM) includes a substrate, channel layers, gate layers, source-drain epitaxial layers, capacitors, capacitor isolation layers, oxide barrier layers, and horizontal bit lines. Multiple channel layers are stacked on the substrate along a first direction perpendicular to the surface direction of the substrate. Multiple gate layers are disposed between the channel layers. Multiple source-drain epitaxial layers are respectively located at first and second ends of the channel layers. Multiple capacitors extend along a second direction perpendicular to the first direction, and each capacitor is connected to a source-drain epitaxial layer located at the first end. Multiple capacitor isolation layers extend along the second direction and are disposed between two capacitors. An oxide barrier layer is disposed between the gate layer and the capacitor isolation layer. Multiple horizontal bit lines are respectively connected to source-drain epitaxial layers located at the second ends.

Claims

1. A 3D dynamic random access memory, comprising: substrate; Multiple channel layers are disposed on the substrate and stacked along a first direction perpendicular to the surface direction of the substrate; multiple gate layers are disposed between the multiple channel layers; multiple source-drain epitaxial layers are respectively disposed at a first end and a second end of the channel layers; multiple capacitors extend along a second direction and each capacitor is connected to each source-drain epitaxial layer located at the first end, the second direction being perpendicular to the first direction; multiple capacitor isolation layers extend along the second direction and are disposed between two capacitors; an oxide barrier layer is disposed between each gate layer and each capacitor isolation layer; and multiple horizontal bit lines are respectively connected to each source-drain epitaxial layer located at the second end.

2. The 3D dynamic random access memory as described in claim 1, wherein the gate length of each gate layer is less than the length of each channel layer.

3. The 3D dynamic random access memory as claimed in claim 1, wherein each capacitor includes: The first electrode layer is in contact with the plurality of capacitor isolation layers; The second electrode layer is located between the plurality of capacitor isolation layers; And a capacitor dielectric layer, located between the first electrode layer and the second electrode layer.

4. The 3D dynamic random access memory as described in claim 1, further comprising: The bit line isolation structure is set on the side of the plurality of horizontal bit lines away from the plurality of channel layers; And multiple isolation slot layers, located between the multiple gate layers and the bit line isolation structure and separating the multiple adjacent horizontal bit lines.

5. A method for manufacturing 3D dynamic random access memory, comprising: A stacked structure consisting of multiple sacrificial layers and multiple channel layers is formed on the substrate; A first opening is formed in the stacked structure; A portion of the sacrificial layer is etched through the first opening, exposing a first portion of the plurality of channel layers; an isolation trench layer is formed within the first opening and fills the spaces between the first portions of the plurality of channel layers; the plurality of sacrificial layers are replaced with a plurality of capacitor isolation layers; a second opening is formed in the stacked structure, the second opening being spaced a predetermined distance from the first opening; a portion of the plurality of capacitor isolation layers is etched through the second opening, exposing a second portion of the plurality of channel layers; an oxide barrier layer is formed within the second opening and fills the spaces between the second portions of the plurality of channel layers; a third opening is formed in the stacked structure, the third opening being located between the second opening and the first opening; the plurality of capacitor isolation layers are etched through the third opening, exposing a third portion of the plurality of channel layers; and a gate layer is formed within the third opening, the gate layer filling the spaces between the third portions of the plurality of channel layers and surrounding the plurality of channel layers.

6. The method for manufacturing a 3D dynamic random access memory as described in claim 5, further comprising, after forming the gate layer: Multiple capacitors are formed between the multiple capacitor isolation layers, and each capacitor is electrically connected to one end of each channel layer.

7. The method for manufacturing a 3D dynamic random access memory as described in claim 5, further comprising, after forming the gate layer: Multiple horizontal bit lines are formed, and each horizontal bit line is electrically connected to the other end of each channel layer.

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