Semiconductor package and manufacturing method thereof

Abstract

The semiconductor package of the present invention includes a substrate, a control chip, a first memory chip, a second memory chip, a redistribution layer, and a third memory chip. The substrate has a first surface and a second surface opposite to each other. The control chip is disposed on the first surface of the substrate and electrically connected to the substrate. The first memory chip is disposed on the first surface of the substrate and electrically connected to the substrate. The second memory chip is disposed on the first memory chip and electrically connected to the substrate. The redistribution layer is formed on the second memory chip. The third memory chip is disposed on the redistribution layer and electrically connected to the redistribution layer. The present invention further provides a method for manufacturing the above-described semiconductor package.

Claims

1. A semiconductor package comprising: a substrate having a first surface and a second surface opposite to each other; a control chip disposed on the first surface of the substrate and electrically connected to the substrate; a first memory chip disposed on the first surface of the substrate and electrically connected to the substrate; a second memory chip disposed on the first memory chip and electrically connected to the substrate; a redistribution layer formed on the second memory chip; and a third memory chip disposed on the redistribution layer and electrically connected to the redistribution layer.

2. The semiconductor package as claimed in claim 1 further comprises: a plurality of first conductive blocks sandwiched between the control chip and the substrate, and electrically connected to the control chip and the substrate.

3. The semiconductor package as claimed in claim 1 further comprises: a plurality of second conductive blocks sandwiched between the third memory chip and the redistribution layer, and electrically connected to the third memory chip and the redistribution layer.

4. The semiconductor package as claimed in claim 1, further comprising: a plurality of bonding wires disposed on the first surface of the substrate and electrically connected to the first memory chip and the substrate.

5. The semiconductor package as claimed in claim 1, further comprising: a plurality of bonding wires disposed on the first surface of the substrate and electrically connected to the second memory chip and the substrate.

6. The semiconductor package as described in claim 1, wherein, The redistribution layer is electrically connected to the second memory chip.

7. The semiconductor package as described in claim 1, wherein, The first memory chip is stacked on the control chip.

8. A method for manufacturing a semiconductor package, comprising: preparing a substrate having a first surface and a second surface opposite to each other; forming a plurality of first conductive blocks on a control chip; disposing the control chip on the first surface of the substrate and sandwiching the first conductive blocks between the control chip and the substrate; disposing a first memory chip on the first surface of the substrate and electrically connecting the first memory chip to the substrate; forming a redistribution layer on a second memory chip; disposing the second memory chip on the first memory chip and electrically connecting the second memory chip to the substrate; forming a plurality of second conductive blocks on a third memory chip; and disposing the third memory chip on the redistribution layer and sandwiching the second conductive blocks between the third memory chip and the redistribution layer.

9. The method of manufacturing a semiconductor package as described in claim 8 further comprises: providing a plurality of bonding wires on the first surface of the substrate, and electrically connecting the bonding wires to the first memory chip and the substrate.

10. The method of manufacturing a semiconductor package as described in claim 8 further comprises: providing a plurality of bonding wires on the first surface of the substrate, and electrically connecting the bonding wires to the second memory chip and the substrate.

Images