Modularize die to die io solution in 2.5d / 3d application

Abstract

This invention provides an input / output circuit for a die and its design method. The input / output circuit includes a main input / output cell and a secondary output cell. Bumps on the die are electrically coupled to a first connection node, a first conductor, and a second conductor of the main input / output cell. The secondary output cell includes a second connection node, a third conductor, and a fourth conductor that are electrically coupled to each other. The main input / output cell and the secondary output cell receive the same output signal from the die to the bumps. In response to the secondary output cells being arranged around the main input / output cells, the third conductor is electrically coupled to the first conductor (or the fourth conductor is electrically coupled to the second conductor), so that the main input / output cell and the secondary output cell jointly provide driving capability to the bumps.

Claims

1. An input / output circuit for a die, comprising: A main input / output cell, wherein the main input / output cell includes a first connection node, a first conductor, and a second conductor, the first connection node being electrically coupled to a bump of the die, the first connection node being electrically coupled to the first conductor and the second conductor, the first conductor being disposed along a first direction in a first interconnect layer of the die, and the second conductor being disposed along a second direction in a second interconnect layer of the die; and at least one secondary output cell, wherein each of the at least one secondary output cell includes a second connection node, a third conductor, and a fourth conductor, the second connection node being electrically coupled to a bump of the die, the first conductor being electrically coupled to the bump of the die, the first conductor being disposed along a first direction in a first interconnect layer of the die, and the second conductor being disposed along a second direction in a second interconnect layer of the die; and at least one secondary output cell, wherein each of the at least one secondary output cell includes a second connection node, a third conductor, and a fourth conductor, the second connection node being electrically coupled to the bump of the die, the first conductor ... electrically coupled to the bump of the die, the first conductor being disposed along a first direction in a first interconnect layer of the die, and the second conductor being disposed along a second direction in a second interconnect layer of the die; and at least one secondary output cell, wherein each secondary output cell includes a second connection node, a third conductor, and a fourth conductor, the second connection node being electrically coupled to the bump of the die, the first conductor being electrically coupled to the bump of the die, the first conductor being electrically coupled to the bump of the die, the first conductor being electrically coupled to the bump of the die, the first conductor being The third conductor is electrically coupled to the fourth conductor, which is arranged in the first interconnect layer along the first direction and the fourth conductor is arranged in the second interconnect layer along the second direction. The main input / output cell and the at least one servant output cell receive the same output signal from the die. In response to the at least one servant output cell being arranged around the main input / output cell, one end of the third conductor is electrically coupled to one end of the first conductor, or one end of the fourth conductor is electrically coupled to one end of the second conductor, so that the main input / output cell and the at least one servant output cell jointly provide driving capability to the bump.

2. The input / output circuit as claimed in claim 1, wherein the die is arranged in a 3D integrated circuit or a 2.5D integrated circuit, and the die is electrically connected to at least one other die in the 3D integrated circuit or the 2.5D integrated circuit via the bump.

3. The input / output circuit as claimed in claim 1, wherein the first interconnect layer and the second interconnect layer are both of the same metal layer of the die.

4. The input / output circuit as claimed in claim 1, wherein the first interconnect layer and the second interconnect layer are different metal layers of the die.

5. The input / output circuit as claimed in claim 1, wherein the determination of the number of the at least one output cell includes: The number of the at least one slave output cell is calculated using the drive capability of the main input / output cell, the drive capability of each of the at least one slave output cell, and a total load value of an external load electrically connected to the bump.

6. The input / output circuit as claimed in claim 5, wherein the determination of the number of the at least one output cell further includes: Calculate Nslave = (Ctotal - Cmaster) / Cslave, where Nslave is the number of slave output cells, Ctotal is the total load value of the external load, Cmaster is the drive capability of the master input / output cell, and Cslave is the drive capability of the slave output cell.

7. The input / output circuit as described in claim 1, further comprising: At least one electrostatic discharge cell, each of which includes a third connection node, a fifth conductor, and a sixth conductor, the third connection node being electrically coupled to the fifth conductor and the sixth conductor, the fifth conductor being arranged along the first direction in the first interconnect layer, the sixth conductor being arranged along the second direction in the second interconnect layer, and in response to the at least one electrostatic discharge cell being arranged around the main input / output cell and the at least one secondary output cell, the fifth conductor being electrically coupled to the first conductor, or the sixth conductor being electrically coupled to the second conductor, so that the at least one electrostatic discharge cell collectively provides electrostatic discharge protection capability to the input / output circuit.

8. The input / output circuit as claimed in claim 7, wherein the determination of the number of the at least one electrostatic discharge cell includes: The electrostatic discharge protection level of the die is converted into an electrostatic discharge protection circuit size. The number of the at least one electrostatic discharge cell is calculated using the total electrostatic discharge protection element size in the main input / output cell, the size of each of the at least one electrostatic discharge cell, and the size of the electrostatic discharge protection circuit.

9. The input / output circuit as claimed in claim 8, wherein the determination of the number of the at least one electrostatic discharge cell further includes: Calculate (Stotal-Smaster) / (Sesd×Nesd) <= 1, where Stotal is the size of the electrostatic discharge protection circuit corresponding to the electrostatic discharge protection level of the die, Smaster is the total size of the electrostatic discharge protection elements in the main input / output cell, Sesd is the size of each of the at least one electrostatic discharge cell, and Nesd is the number of the at least one electrostatic discharge cell.

10. The input / output circuit as described in claim 1, further comprising: At least one antenna cell, each of which includes a third connection node, a fifth conductor, and a sixth conductor, the third connection node being electrically coupled to the fifth conductor and the sixth conductor, the fifth conductor being arranged along the first direction in the first interconnect layer, the sixth conductor being arranged along the second direction in the second interconnect layer, and in response to the at least one antenna cell being arranged around the main input / output cell and the at least one secondary output cell, the fifth conductor being electrically coupled to the first conductor, or the sixth conductor being electrically coupled to the second conductor, so that the at least one antenna cell collectively provides antenna effect protection capability to the input / output circuit.

11. The input / output circuit as claimed in claim 10, wherein the determination of the number of the at least one day cell includes: Tracing a conductive path within the grain that electrically connects the bump; Calculate the total conductor area of ​​this conductive path; Calculate a first total active region area of ​​the conductive path electrically connected in the absence of the at least one day cell; and use the total conductor area, the first total active region area, and the area of ​​each of the at least one day cell to calculate the number of the at least one day cell.

12. The input / output circuit as claimed in claim 11, wherein the determination of the number of at least one day cell further includes: Calculate Attotal / [A1+(A2×Nant)] = AR, where Attotal is the total conductor area, A1 is the first total active region area, A2 is the second total active region area of ​​each of the at least one antenna cell, Nant is the number of the at least one antenna cell, and AR is the antenna ratio.

13. The input / output circuit as claimed in claim 1, wherein the main input / output cell further comprises: An output buffer, wherein an input terminal of the output buffer is coupled to a functional circuit of the die to receive the same output signal, and an output terminal of the output buffer is coupled to the first connection node; and an input buffer, wherein an input terminal of the input buffer is coupled to the first connection node; And a gate circuit, wherein an input terminal of the gate circuit is coupled to an output terminal of the input buffer, and an output terminal of the gate circuit is coupled to the functional circuit to provide an input signal.

14. The input / output circuit of claim 13, wherein the output buffer is controlled by an output enable signal, the gate circuit is controlled by an input enable signal, the output buffer is enabled in response to the output enable signal and the gate circuit is disabled in response to the input enable signal, the main input / output cell acts as an output cell and the at least one servant output cell is enabled such that the main input / output cell and the at least one servant output cell jointly output the same output signal to the bump; and the output buffer is disabled in response to the output enable signal and the gate circuit is enabled in response to the input enable signal, the main input / output cell acts as an input cell and the at least one servant output cell is disabled such that the main input / output cell transmits the input signal from the bump to the functional circuit.

15. The input / output circuit as claimed in claim 13, wherein the main input / output cell further comprises: An electrostatic discharge (ESD) protection element, wherein the ESD protection element is coupled to the first connection node to provide ESD protection capability.

16. The input / output circuitry as claimed in claim 13, wherein the main input / output cell further comprises: An antenna effect protection element, wherein the antenna effect protection element is coupled to the first connection node to provide antenna effect protection capability.

17. The input / output circuit as claimed in claim 1, wherein each of the at least one output cell further comprises: An output buffer, wherein an input of the output buffer is coupled to a functional circuit of the die to receive the same output signal, and an output of the output buffer is coupled to the second connection node.

18. The input / output circuit of claim 17, wherein the output buffer is controlled by an output enable signal, and in response to the output enable signal, the output buffer is enabled, the at least one servant output cell is enabled and the main input / output cell acts as an output cell, such that the main input / output cell and the at least one servant output cell jointly output the same output signal to the bump; and in response to the output enable signal, the output buffer is disabled, the at least one servant output cell is disabled and the main input / output cell acts as an input cell, such that the main input / output cell transmits an input signal from the bump to the functional circuit.

19. A method for designing the input / output circuit of a die, comprising: Confirm the total load value of an external load electrically connected to a bump of the die; A main input / output cell is arranged in the input / output circuit, wherein the main input / output cell includes a first connection node, a first conductor, and a second conductor. The first connection node is electrically coupled to the bump, the first conductor, and the second conductor. The first conductor is arranged along a first direction in a first interconnect layer of the die, and the second conductor is arranged along a second direction in a second interconnect layer of the die. The number of the at least one slave output cell is calculated using the drive capability of the main input / output cell, the drive capability of each of the at least one slave output cell, and the total load value. Based on the number of at least one slave output cells, the at least one slave output cell is arranged in the input / output circuit, wherein each of the at least one slave output cell includes a second connection node, a third conductor, and a fourth conductor, the second connection node being electrically coupled to the third conductor and the fourth conductor, the third conductor being arranged along the first direction in the first interconnect layer, the fourth conductor being arranged along the second direction in the second interconnect layer, and the main input / output cell and the at least one slave output cell receiving the same output signal of the die; and in response to the at least one slave output cell being arranged around the main input / output cell, one end of the third conductor is electrically coupled to one end of the first conductor, or one end of the fourth conductor is electrically coupled to one end of the second conductor, so that the main input / output cell and the at least one slave output cell jointly provide driving capability to the bump.

20. The design method as claimed in claim 19, wherein the die is arranged in a 3D integrated circuit or a 2.5D integrated circuit, and the die is electrically connected to at least one other die in the 3D integrated circuit or the 2.5D integrated circuit via the bump.

21. The design method as described in claim 19, wherein the first interconnect layer and the second interconnect layer are both identical metal layers of the grain.

22. The design method as described in claim 19, wherein the first interconnect layer and the second interconnect layer are different metal layers of the grain.

23. The design method as described in claim 19 further includes: Calculate Nslave = (Ctotal - Cmaster) / Cslave, where Nslave is the number of slave output cells, Ctotal is the total load value of the external load, Cmaster is the drive capability of the master input / output cell, and Cslave is the drive capability of the slave output cell.

24. The design method as described in claim 19 further includes: Confirm the electrostatic discharge (ESD) protection level of the die; convert the ESD protection level into an ESD protection circuit size; The number of at least one electrostatic discharge (ESD) cells is calculated using the overall ESD protection element size in the main input / output cell, the size of each of the at least one ESD cells, and the size of the ESD protection circuit. Based on the number of the at least one ESD cells, the at least one ESD cell is arranged in the input / output circuit, wherein each of the at least one ESD cell includes a third connection node, a fifth conductor, and a sixth conductor, the third connection node being electrically coupled to the fifth conductor and the sixth conductor, the fifth conductor being arranged along the first direction in the first interconnect layer, and the sixth conductor being arranged along the second direction in the second interconnect layer. In response to the at least one ESD cell being arranged around the main input / output cell and the at least one secondary output cell, it is electrically coupled to the first conductor by the fifth conductor or to the second conductor by the sixth conductor, so that the at least one ESD cell collectively provides ESD protection capability to the input / output circuit.

25. The design method as described in claim 24 further includes: Calculate (Stotal-Smaster) / (Sesd×Nesd) <= 1, where Stotal is the size of the electrostatic discharge protection circuit corresponding to the electrostatic discharge protection level of the die, Smaster is the total size of the electrostatic discharge protection elements in the main input / output cell, Sesd is the size of each of the at least one electrostatic discharge cell, and Nesd is the number of the at least one electrostatic discharge cell.

26. The design method as described in claim 19 further includes: Confirm the daily line ratio; Tracing a conductive path within the grain that electrically connects the bump; Calculate the total conductor area of ​​this conductive path; Calculate a first total active region area electrically connecting the conductive path in the absence of antenna cells; calculate the number of at least one antenna cell using the total conductor area, the first total active region area, and a second total active region area of ​​each of the at least one antenna cell; based on the number of at least one antenna cells, arrange the at least one antenna cell in the input / output circuit, wherein each of the at least one antenna cell includes a third connection node, a fifth conductor, and a sixth conductor, the third connection node being electrically coupled to the fifth conductor and the sixth conductor, the fifth conductor being arranged along the first direction in the first interconnect layer, and the sixth conductor being arranged along the second direction in the second interconnect layer; and in response to the at least one antenna cell being arranged around the main input / output cell and the at least one secondary output cell, being electrically coupled to the first conductor by the fifth conductor, or electrically coupled to the second conductor by the sixth conductor, so that the at least one antenna cell collectively provides antenna effect protection capability to the input / output circuit.

27. The design method as described in claim 26 further includes: Calculate Attotal / [A1+(A2×Nant)] = AR, where Attotal is the total conductor area, A1 is the first total active region area, A2 is the second total active region area of ​​each of the at least one antenna cell, Nant is the number of the at least one antenna cell, and AR is the antenna ratio.

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