Memory system and decoding circuit

The memory system uses data rotation and interleaving to address periodic errors in non-volatile memory, enhancing error correction capabilities while maintaining a compact circuit design.

TWI934762BActive Publication Date: 2026-08-01KIOXIA CORP
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Patent Information

Application Number
TW114132931
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Priority Date
2025-03-14
Filing Date
2025-08-28
Publication Date
2026-08-01
Estimated Expiration
2045-08-27

AI Technical Summary

Technical Problem

Memory systems face challenges in correcting periodic errors caused by electrical noise in non-volatile memory, which conventional error correction codes struggle to address effectively.

Method used

A memory system and decoding circuit that employs data rotation and interleaving techniques, where each segment undergoes a cyclic shift based on its position, followed by common interleaving and deinterleaving operations, to distribute errors across multiple correction blocks, thereby enhancing tolerance to periodic errors while minimizing circuit size.

Benefits of technology

The proposed solution effectively corrects periodic errors in non-volatile memory systems by distributing them across multiple correction blocks, improving error tolerance without significantly increasing circuit complexity or cost.

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Abstract

This invention provides a memory system and decoding circuit capable of appropriately correcting periodic errors. The memory controller performs a first conversion operation on each of a plurality of first segments, each divided by a first length. This first conversion operation converts the order of symbols within a first segment using a conversion mode corresponding to the position of a first segment in the first symbol row. The memory controller then performs a second conversion operation on each of the plurality of first segments following the first conversion operation. This second conversion operation converts the order of symbols within a first segment using a common conversion mode across the plurality of first segments. Finally, the memory controller performs decoding using the same bit position on the plurality of first segments following the second conversion operation.
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