Memory system and decoding circuit

Abstract

This invention provides a memory system and decoding circuit capable of appropriately correcting periodic errors. The memory controller performs a first conversion operation on each of a plurality of first segments, each divided by a first length. This first conversion operation converts the order of symbols within a first segment using a conversion mode corresponding to the position of a first segment in the first symbol row. The memory controller then performs a second conversion operation on each of the plurality of first segments following the first conversion operation. This second conversion operation converts the order of symbols within a first segment using a common conversion mode across the plurality of first segments. Finally, the memory controller performs decoding using the same bit position on the plurality of first segments following the second conversion operation.

Claims

1. A memory system comprising: a non-volatile first memory; a volatile second memory; and a memory controller, configured to: read a first symbol line from the first memory; perform a first conversion operation on each of a plurality of first segments of the read first symbol line divided according to a first length, the first conversion operation being to convert the arrangement order of symbols within a first segment using a conversion mode corresponding to the position of the first segment in the first symbol line; perform a second conversion operation on each of the plurality of first segments after the first conversion operation, the second conversion operation being to convert the arrangement order of symbols within a first segment using a conversion mode common to the plurality of first segments; and perform decoding using the same bit on the plurality of first segments after the second conversion operation. Perform the inverse conversion of the second conversion operation, i.e., the third conversion operation, on each of the plurality of first segments after the above decoding; perform the inverse conversion of the first conversion operation, i.e., the fourth conversion operation, on each of the plurality of first segments after the above third conversion operation; and store the second symbol row formed by combining the plurality of first segments after the above fourth conversion operation in the above second memory.

2. The memory system of claim 1, wherein the memory controller is configured to, in the first conversion operation, convert the arrangement order of symbols in each of the first sub-segments contained in the first segment to each of the plurality of first sub-segments divided by a first segment according to a factor of the second length, in a conversion mode corresponding to the position of the first segment in the first symbol row.

3. The memory system of claim 2, wherein the memory controller is configured such that, in the first conversion operation, by calculating the first number using the position, the arrangement order of the symbols in each first sub-segment is cyclically shifted only according to the number of times the first number is calculated.

4. The memory system of claim 1, wherein the memory controller is configured to read a third symbol line from the second memory, perform a fifth conversion operation on each of the plurality of second segments divided according to a first length of the third symbol line, wherein the fifth conversion operation is to convert the arrangement order of symbols in a second segment using a conversion mode corresponding to the position of a second segment in the third symbol line, and perform a sixth conversion operation on each of the plurality of second segments after the fifth conversion operation, wherein the sixth conversion operation is to convert the arrangement order of symbols in a second segment using a common conversion mode among the plurality of second segments, generate a corresponding bit by means of error correction code of the plurality of first segment groups after the sixth conversion operation, and write the third symbol line and the corresponding bit to the second memory.

5. A memory system as claimed in any of claims 1 to 4, wherein the memory controller is configured to, in the second transition operation, interleave all symbols within a first segment for each of the plurality of first segments following the first transition operation.

6. The memory system of any of the requests 1 to 4, wherein the aforementioned corresponding bits are corresponding bits of the product code.

7. A decoding circuit comprising: a first terminal input to a first symbol line; a first conversion circuit that, for each of a plurality of first segments dividing the first symbol line according to a first length, converts the arrangement order of symbols within a first segment using a conversion mode corresponding to the position of the first segment in the first symbol line; a second conversion circuit that, for each of the plurality of first segments after conversion by the first conversion circuit, converts the arrangement order of symbols within a first segment using a conversion mode common to the plurality of first segments; a decoder that performs decoding using the same bit on the plurality of first segments after conversion by the second conversion circuit; and a third conversion circuit that performs the inverse conversion of the second conversion circuit on each of the plurality of first segments after decoding. The fourth conversion circuit performs the inverse conversion of the first conversion circuit on each of the plurality of first segments after the inverse conversion of the third conversion circuit; and the second terminal outputs a second symbol row formed by combining the plurality of first segments after the inverse conversion of the fourth conversion circuit.

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