Gate driver and in-vehicle display

Abstract

A gate driver and an automotive display are disclosed herein. The gate driver includes a shift register module and a selection module. The shift register module includes a first dummy shift register circuit to a fourth dummy shift register circuit and N shift register circuits. The first dummy shift register circuit is configured to output a first dummy signal. The second dummy shift register circuit is configured to output a second dummy signal. The third dummy shift register circuit is configured to output a third dummy signal. The fourth dummy shift register circuit is configured to output a fourth dummy signal. The selection module is configured to selectively output one of the first dummy signal and the third dummy signal, and one of the second dummy signal and the fourth dummy signal, based on a forward scan signal and a reverse scan signal.

Claims

1. A gate driver, comprising: A shift register module includes: a first dummy shift register circuit configured to output a first dummy signal; a second dummy shift register circuit configured to output a second dummy signal; a third dummy shift register circuit configured to output a third dummy signal; a fourth dummy shift register circuit configured to output a fourth dummy signal; and N shift register circuits, including a first shift register circuit to an Nth shift register circuit arranged sequentially for outputting a first scan signal to an Nth scan signal respectively, where N is a positive integer; The shift register module is configured to sequentially output the first dummy signal, the second dummy signal, the first scan signal to the Nth scan signal, the third dummy signal, and the fourth dummy signal according to a forward scan signal, and sequentially output the fourth dummy signal, the third dummy signal, the Nth scan signal to the first scan signal, the second dummy signal, and the first dummy signal according to a reverse scan signal; and a selection module is configured to selectively output one of the first dummy signal and the third dummy signal, and output one of the second dummy signal and the fourth dummy signal according to the forward scan signal and the reverse scan signal.

2. The gate driver as claimed in claim 1, wherein the third dummy shift register circuit is further configured to output the third dummy signal according to a first timing signal, the fourth dummy shift register circuit is further configured to output the fourth dummy signal according to a second timing signal, the first dummy shift register circuit is further configured to output the first dummy signal according to a third timing signal, and the second dummy shift register circuit is further configured to output the second dummy signal according to a fourth timing signal.

3. The gate driver as claimed in claim 2, wherein a (4K-3)th shift register circuit of the N shift register circuits is further configured to output the first scan signal to a (4K-3)th scan signal of the Nth scan signal according to the first timing signal, and a (4K-2)th shift register circuit of the N shift register circuits is further configured to output the first scan signal to a (4K-2)th scan signal of the Nth scan signal according to the second timing signal. The signal, one of the N shift register circuits, the (4K-1)th shift register circuit, is further configured to output the first scan signal to the (4K-1)th scan signal in the Nth scan signal according to the third timing signal, and the (4K)th shift register circuit in the N shift register circuits is further configured to output the first scan signal to the (4K)th scan signal in the Nth scan signal according to the fourth timing signal, where 1≤K≤N / 4, and K is a positive integer.

4. The gate driver as claimed in claim 2, wherein the selection module comprises: A first selection circuit is electrically connected to the first dummy shift register circuit and the third dummy shift register circuit, and is configured to output the third dummy signal according to the forward scan signal and the third timing signal, and is configured to output the first dummy signal according to the reverse scan signal and the first timing signal.

5. The gate driver as claimed in claim 4, wherein the selection module further comprises: A second selection circuit is electrically connected to the second dummy shift register circuit and the fourth dummy shift register circuit, and is configured to output the fourth dummy signal according to the forward scan signal and the fourth timing signal, and is configured to output the second dummy signal according to the reverse scan signal and the second timing signal.

6. The gate driver as claimed in claim 4, wherein the first selection circuitry comprises: A first transistor includes: a control terminal configured to receive the third timing signal; a first terminal configured to receive the forward scan signal; and a second terminal; a second transistor includes: a control terminal electrically connected to the second terminal of the first transistor; a first terminal configured to receive the third dummy signal; and a second terminal; and a third transistor includes: a control terminal electrically connected to the second terminal of the first transistor; a first terminal electrically connected to the second terminal of the second transistor; and a second terminal electrically connected to the first terminal of the third transistor and a first output terminal.

7. The gate driver as claimed in claim 6, wherein the first selection circuit further comprises: A fourth transistor includes: a control terminal configured to receive the first timing signal; a first terminal configured to receive the reverse scan signal; and a second terminal; a fifth transistor includes: a control terminal electrically connected to the second terminal of the fourth transistor; a first terminal configured to receive the first dummy signal; and a second terminal; and a sixth transistor includes: a control terminal electrically connected to the second terminal of the fourth transistor; a first terminal electrically connected to the second terminal of the fifth transistor; and a second terminal electrically connected to the first terminal and the first output terminal of the sixth transistor.

8. The gate driver as claimed in claim 5, wherein the second selection circuitry comprises: A seventh transistor includes: a control terminal configured to receive the fourth timing signal; a first terminal configured to receive the forward scan signal; and a second terminal; an eighth transistor includes: a control terminal electrically connected to the second terminal of the seventh transistor; a first terminal configured to receive the fourth dummy signal; and a second terminal; and a ninth transistor includes: a control terminal electrically connected to the second terminal of the seventh transistor; a first terminal electrically connected to the second terminal of the eighth transistor; and a second terminal electrically connected to the first terminal and a second output terminal of the ninth transistor.

9. The gate driver as claimed in claim 8, wherein the second selection circuit further comprises: A tenth transistor includes: a control terminal configured to receive the second timing signal; a first terminal configured to receive the reverse scan signal; and a second terminal; an eleventh transistor includes: a control terminal electrically connected to the second terminal of the tenth transistor; a first terminal configured to receive the second dummy signal; and a second terminal; and a twelfth transistor includes: a control terminal electrically connected to the second terminal of the tenth transistor; a first terminal electrically connected to the second terminal of the eleventh transistor; and a second terminal electrically connected to the first terminal and the second output terminal of the twelfth transistor.

10. A vehicle display, comprising: One substrate; A pixel array is disposed on the substrate and includes a first column of pixel units to an Nth column of pixel units arranged sequentially; a gate driver as described in any one of claims 1 to 9 is disposed on the substrate, wherein the first scan signal to the Nth scan signal is respectively used to output to the first column of pixel units to the Nth column of pixel units; And an automotive chip, disposed on the substrate, and including: a first pin configured to receive one of the first dummy signal and the third dummy signal; And a second pin configured to receive one of the second dummy signal and the fourth dummy signal.

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