Memory package structure and manufacturing method thereof
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- ZHIDING TECHNOLOGY CO LTD
- Filing Date
- 2025-10-22
- Publication Date
- 2026-08-01
Smart Images
Figure TWG2TB001904161_001 
Figure TWG2TB001904161_002 
Figure TWG2TB001904161_003
Abstract
Claims
1. A method for manufacturing a memory package structure, comprising the following steps: providing a memory package structure, including a first substrate, a first chip, a second chip, and a controller, wherein the first chip, the second chip, and the controller are electrically connected to the first substrate; disconnecting the electrical connection between the first chip, the second chip, and the controller and the first substrate; providing a second substrate electrically connected to the second chip and the controller; providing an outer encapsulating colloid to cover and seal the first substrate, the first chip, the second chip, the controller, and the second substrate; and providing a plurality of second solder balls electrically connected to the second substrate.
2. A process method for manufacturing a memory packaging structure as described in claim 1, wherein, The first chip is one of dynamic random access memory and NAND flash memory, and the second chip is the other of dynamic random access memory and NAND flash memory.
3. A process method for manufacturing a memory packaging structure as described in claim 1, wherein, Remove a shielding layer that is located on the surface of the memory package structure.
4. A process method for manufacturing a memory packaging structure as described in claim 1, wherein, The first substrate has a first surface and a second surface opposite to each other. The first surface is provided with a first row of pads and a second row of pads. The second surface is provided with a plurality of first solder balls. The first row of pads and the second row of pads are electrically connected to the first solder balls. The memory package structure also includes an inner encapsulating colloid that covers and seals the first substrate, the first row of pads, the second row of pads, the first chip, the second chip, and the controller.
5. A process method for manufacturing a memory packaging structure as described in claim 4, wherein, Remove part of the inner encapsulating adhesive to expose at least part of the first row of pads and at least part of the second row of pads; Remove the first solder balls; disconnect the first chip, the second chip, and the controller from the first substrate, so that the first chip, the second chip, and the controller are not electrically connected to the first substrate.
6. A process method for manufacturing a memory packaging structure as described in claim 5, wherein, A bottom encapsulating colloid is provided and disposed on the second surface; a second substrate is disposed below the bottom encapsulating colloid and is provided with a third row of pads electrically connected to the first row of pads and a fourth row of pads electrically connected to the second row of pads.
7. A process method for manufacturing a memory packaging structure as described in claim 6, wherein, The outer encapsulating colloid covers and seals the first substrate, the inner encapsulating colloid, the first row of pads, the second row of pads, the bottom encapsulating colloid, the second substrate, the third row of pads, and the fourth row of pads.
8. A process method for manufacturing a memory packaging structure as described in claim 7, wherein, The second solder balls are disposed below the second substrate and electrically connected to the third row of pads and the fourth row of pads.
9. A process method for manufacturing a memory packaging structure as described in claim 1, wherein, A shielding layer is provided to cover the second substrate and the outer encapsulating colloid.
10. A memory packaging structure, comprising: A first substrate has a first surface and a second surface opposite to each other, and the first surface is provided with a first row of pads and a second row of pads; A first chip is disposed on the first surface and is not electrically connected to the first row of pads and the second row of pads; a second chip is stacked on top of the first chip and is electrically connected to the first row of pads and the second row of pads; a controller is disposed on the first surface or stacked on top of the second chip and is not electrically connected to the first chip; an inner encapsulant covers and seals the first substrate, the first chip, the second chip, and the controller; a bottom encapsulant is disposed on the second surface; a second substrate is disposed below the bottom encapsulant and has a third row of pads and a fourth row of pads, the third row of pads being electrically connected to the first row of pads and the fourth row of pads being electrically connected to the second row of pads; An outer encapsulating colloid covers and seals the first substrate, the first chip, the second chip, the controller, the inner encapsulating colloid, the bottom encapsulating colloid, and the second substrate; and a plurality of solder balls are disposed below the second substrate and electrically connected to the third row of pads and the fourth row of pads.
11. The memory packaging structure as described in claim 10, wherein, The first row of pads, the second row of pads, the third row of pads, and the fourth row of pads form a single gold finger.
12. The memory packaging structure as described in claim 10, wherein, The first chip is one of dynamic random access memory and NAND flash memory, and the second chip is the other of dynamic random access memory and NAND flash memory.
13. The memory packaging structure as described in claim 10, wherein, The inner encapsulating colloid, the bottom encapsulating colloid, and the outer encapsulating colloid are all made of epoxy resin.
14. The memory packaging structure as described in claim 10 further includes a shielding layer covering the outer packaging colloid.