Manufacturing method of semiconductor structure
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- POWERCHIP SEMICON MFG CORP
- Filing Date
- 2025-10-22
- Publication Date
- 2026-08-01
Smart Images

Figure TWG2TB001904162_001 
Figure TWG2TB001904162_002 
Figure TWG2TB001904162_003
Abstract
Claims
1. A method for manufacturing a semiconductor structure, comprising: Provide a base; A pad layer is formed on the substrate; A plurality of isolation structures are formed in the substrate and the padding layer, wherein the plurality of isolation structures have a plurality of protrusions, and the top surface of the protrusions is higher than the top surface of the padding layer; a protective gap wall is formed on the sidewall of the protrusion; Using the protective gap wall as a cover, the padding layer is removed; The method for removing the protective gap wall includes: using the protective gap wall as a mask to perform a dry etching process on the pad to remove a portion of the pad; And after the dry etching process, the pad is wet-etched using the protective spacer wall as a cover to remove the remaining pad.
2. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the method for forming a plurality of said isolation structures includes: A rigid cover layer is formed on the padding layer; Multiple trenches are formed in the rigid cover layer, the padding layer, and the substrate; And to form multiple isolation structures in multiple of the aforementioned ditches.
3. The method for manufacturing the semiconductor structure as described in claim 2 further includes: After forming multiple isolation structures, the rigid masking layer is removed.
4. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the method for forming the protective spacer wall comprises: A protective layer is formed on the padding layer and the plurality of the isolation structures; The protective layer is then etched back to form the protective spacer wall.
5. A method for manufacturing a semiconductor structure as claimed in claim 4, wherein the method for forming the protective layer includes chemical vapor deposition or atomic layer deposition.
6. A method for manufacturing a semiconductor structure as claimed in claim 4, wherein the etch-back process includes a dry etching process.
7. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein after the dry etching process, the remaining pad layer is not exposed outside the substrate.
8. The method for manufacturing a semiconductor structure as described in claim 1, further comprising: After the protective gap wall is removed, a first dielectric layer is formed on the substrate; A plurality of floating gates are formed between the plurality of protrusions and on the first dielectric layer; A back-etch process is performed on the plurality of isolation structures to form a plurality of recesses; a second dielectric layer is formed on the plurality of floating gates and the plurality of isolation structures and in the plurality of recesses; and a control gate is formed on the second dielectric layer and in the plurality of recesses.
9. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the method for removing the protective spacer wall includes a wet etching method.