Semiconductor device

Abstract

A semiconductor device includes an epitaxial layer disposed on a substrate, both the substrate and the epitaxial layer having a first conductivity type, and a lateral transistor disposed in a first region of the epitaxial layer. The lateral transistor includes a first high-voltage well region having a second conductivity type, and a second high-voltage well region having a first conductivity type, laterally adjacent to the first high-voltage well region. The first well region has a second conductivity type and is disposed within the first high-voltage well region. In a planar layout, the first well region includes first and second portions with a long axis in a first direction, and third and fourth portions with a long axis in a second direction. A drain region is disposed within the first and second portions of the first well region. A second well region is disposed within the second high-voltage well region, a source region is disposed within the second well region, and a gate electrode is disposed on the first and second high-voltage well regions.

Claims

1. A semiconductor device, comprising: A substrate having a first conductivity type; An epitaxial layer is disposed on the substrate and has the first conductivity type; The image also includes a lateral transistor disposed in a first region of the epitaxial layer, comprising: a first high-voltage well region having a second conductivity type; a second high-voltage well region having the first conductivity type and laterally adjacent to the first high-voltage well region; a first well region having the second conductivity type disposed in the first high-voltage well region, wherein in a planar layout, the first well region includes a first portion and a second portion with a major axis in a first direction, and a third portion and a fourth portion with a major axis in a second direction, the first direction being perpendicular to the second direction; a drain region disposed in the first portion and the second portion of the first well region; a second well region having the first conductivity type disposed in the second high-voltage well region; a source region disposed in the second well region; and a gate electrode disposed on the first high-voltage well region and the second high-voltage well region.

2. The semiconductor device as claimed in claim 1, wherein the doping concentration of the first well region is higher than the doping concentration of the first high-pressure well region and lower than the doping concentration of the drain region.

3. The semiconductor device as claimed in claim 1 further includes a deep high-voltage well region having the first conductivity type, disposed in the epitaxial layer, surrounding the first high-voltage well region, and laterally separated from the first high-voltage well region.

4. The semiconductor device as claimed in claim 3 further includes a vertical transistor disposed in a second region of the epitaxial layer, wherein the deep high-pressure well region is located between the lateral transistor and the vertical transistor.

5. The semiconductor device as claimed in claim 3, wherein the third portion and the fourth portion of the first well region are both located between the deep high-pressure well region and the second high-pressure well region.

6. The semiconductor device as claimed in claim 3, wherein the lateral transistor further includes a first isolation region that extends laterally and continuously from the periphery of the deep high-pressure well region to a portion of the top surface of the first high-pressure well region in the second direction.

7. The semiconductor device as claimed in claim 6, wherein the lateral transistor further includes a second isolation region disposed on the top surface of the first high-pressure well region, the drain region is located between the first isolation region and the second isolation region, and a portion of the gate electrode extends laterally onto the second isolation region.

8. The semiconductor device as claimed in claim 7, wherein the first portion and the second portion of the first well region are both located between the first isolation region and the second isolation region.

9. The semiconductor device as claimed in claim 3, wherein the lateral transistor further includes a third isolation region extending laterally and continuously in the first direction from the top surface of the deep high-pressure well region to the top surface of the first high-pressure well region, a portion of the top surface of the second high-pressure well region, and a portion of the top surface of the second well region.

10. The semiconductor device as claimed in claim 9, wherein the third portion and the fourth portion of the first well region are both located below the third isolation region and in contact with the bottom surface of the third isolation region.

11. The semiconductor device as claimed in claim 1, wherein the lateral transistor further includes a base region disposed in the second well region adjacent to the source region, and in the planar layout, a region of the third portion of the first well region, a region of the fourth portion of the first well region, and the base region are aligned in the first direction.

12. The semiconductor device as claimed in claim 11, wherein the lateral transistor further includes a fourth isolation region disposed in the second well region and located between the base region and the source region.

13. The semiconductor device as claimed in claim 1, wherein the first portion, the second portion, the third portion and the fourth portion of the first well region are interconnected to form a continuous closed loop.

14. The semiconductor device as claimed in claim 1, wherein the first portion and the second portion of the first well region each comprise an elongated shape, and the third portion and the fourth portion each comprise a plurality of blocks spaced apart from each other along the second direction.

15. The semiconductor device as claimed in claim 1, wherein the first portion and the second portion of the first well region each include a plurality of first blocks spaced apart from each other along the first direction, and the plurality of first blocks are located outside the drain region, and the third portion and the fourth portion each include a plurality of second blocks spaced apart from each other along the second direction.

16. The semiconductor device as claimed in claim 1, wherein the outermost edge of the first well region and the outermost edge of the first high-pressure well region are laterally separated.

17. The semiconductor device as claimed in claim 1, wherein the first portion of the first well region is separated from a first outermost edge of the first high-pressure well region by a first distance, the third portion of the first well region is separated from a second outermost edge of the first high-pressure well region by a second distance, and the first distance is greater than the second distance.

18. The semiconductor device as claimed in claim 1, wherein the bottom surface of the first well region is higher than the bottom surface of the second well region.

19. The semiconductor device as claimed in claim 1, wherein the lateral transistor further includes a buried layer having the second conductivity type, disposed directly below the second high-pressure well region, and extending laterally to directly below a portion of the first high-pressure well region.

20. The semiconductor device as claimed in claim 1, wherein the lateral transistor includes a P-type lateral double-diffused metal-oxide-semiconductor transistor, and the semiconductor device further includes an N-type lateral double-diffused metal-oxide-semiconductor transistor and a complementary metal-oxide-semiconductor transistor disposed in the first region of the epitaxial layer.

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