Memory system

Abstract

The memory system includes a memory device, a sensing device, and a bit detection device. The memory device stores a plurality of data sets and compares the stored data sets with a plurality of input data sets to generate a plurality of operation results. The sensing device senses the operation results. The bit detection device detects the operation results to generate a plurality of output voltage signals, wherein the operation results include a calculation result, and the bit detection device compares a first threshold value with a total count to generate one of the output voltage signals.

Claims

1. A memory system comprising: a memory device for storing a plurality of stored data sets and for comparing the stored data sets with a plurality of input data sets to generate a plurality of operation results; a sensing device for sensing the operation results; and a bit detection device for detecting the operation results to generate a plurality of output voltage signals, wherein the operation results include an operation result, the bit detection device for comparing a first threshold value with a total number to generate an output voltage signal among the output voltage signals, the bit detection device comprising a bit detection unit, the bit detection unit comprising: a current generator for receiving a reference code corresponding to the first threshold value to generate a reference current signal passing through a first node; a current mirror circuit for mapping the reference current signal to a second node to generate a sense current signal passing through the second node; and a comparator coupled to each of the first node and the second node for outputting the output voltage signal.

2. The memory system as claimed in claim 1, wherein when the total number is less than or equal to the first threshold, the output voltage signal has a first voltage level, and when the total number is greater than the first threshold, the output voltage signal has a second voltage level, and the first voltage level is different from the second voltage level.

3. The memory system as claimed in claim 1 further includes: a bit counting circuit for receiving the operation result and the output voltage signal, wherein the total number is equal to the number of operands having a first logic value in the operation result, and when the total number is less than or equal to the first threshold, the bit counting circuit is activated and counts the operands having the first logic value in the operation result.

4. The memory system as described in claim 1 further includes: a page buffer coupled to the second node and used to adjust the voltage level of the second node according to the total number.

5. The memory system as described in claim 4, wherein a resistance value of the page buffer is larger when the total number is larger, and a resistance value of the page buffer is smaller when the total number is smaller.

6. The memory system as described in claim 1, wherein the voltage level of the first node increases as the first threshold value increases.

7. The memory system as claimed in claim 1, wherein the bit detection unit is further configured to set a second threshold value, wherein when the bit detection unit switches to the first threshold value, in response to the total number being greater than the first threshold value, the output voltage signal has a first voltage level, and when the bit detection unit switches to the second threshold value, in response to the total number being less than or equal to the second threshold value, the output voltage signal has a second voltage level, and the first voltage level is different from the second voltage level.

8. The memory system as claimed in claim 7, wherein when the bit detection unit switches from the first threshold to the second threshold, in response to the output voltage signal changing from the first voltage level to the second voltage level, the memory system determines that the total is greater than the first threshold and less than or equal to the second threshold.

9. The memory system as claimed in claim 1, wherein the total number corresponds to the Euclidean distance between a first storage data group among the storage data groups and a first input data group among the input data groups.

10. The memory system as claimed in claim 1, wherein the total number corresponds to the Manhattan distance between a first storage data group among the storage data groups and a first input data group among the input data groups.

11. The memory system as claimed in claim 1, wherein the total number corresponds to the dot product between a first stored data group among the stored data groups and a first input data group among the input data groups.

12. A memory system comprising: a memory page for storing a set of stored data and for comparing the set of stored data with an input set of data to generate an operation result; a sensing amplifier for sensing the operation result; and a bit detection unit for comparing the first threshold value with a total of the operation result to generate an output voltage signal, wherein the bit detection unit comprises: a current generator for receiving a reference code corresponding to the first threshold value to generate a reference current signal passing through a first node; a current mirror circuit for mapping the reference current signal to a second node to generate a sensed current signal passing through the second node; and a comparator coupled to each of the first node and the second node for outputting the output voltage signal, wherein a larger first threshold value results in a larger voltage level at the first node.

13. The memory system as claimed in claim 12 further includes: a bit counting circuit for receiving the operation result and the output voltage signal, wherein the total number is equal to the number of operands having a first logic value in the operation result, and when the total number is less than or equal to the first threshold, the bit counting circuit is activated and counts the operands having the first logic value in the operation result.

14. The memory system as claimed in claim 13 further includes: a page buffer coupled to the second node and used to adjust the voltage level of the second node according to the total number, wherein a resistance value of the page buffer is larger when the total number is larger, and a resistance value of the page buffer is smaller when the total number is smaller.

15. The memory system as claimed in claim 13, wherein the bit detection unit is further configured to set a second threshold value, wherein when the bit detection unit switches to the first threshold value, in response to the total number being greater than the first threshold value, the output voltage signal has a first voltage level, and when the bit detection unit switches to the second threshold value, in response to the total number being less than or equal to the second threshold value, the output voltage signal has a second voltage level, and the first voltage level is different from the second voltage level.

16. The memory system as claimed in claim 15, wherein when the bit detection unit switches from the first threshold to the second threshold, in response to the output voltage signal changing from the first voltage level to the second voltage level, the memory system determines that the total is greater than the first threshold and less than or equal to the second threshold.

17. A memory system comprising a bit detection unit for comparing a first threshold value with a total of an operation result to generate an output voltage signal, the bit detection unit comprising: a current generator for receiving a reference code corresponding to the first threshold value to generate a reference current signal passing through a first node; a current mirror circuit for mapping the reference current signal to a second node to generate a sense current signal passing through the second node; and a comparator coupled to each of the first node and the second node for outputting the output voltage signal.

18. The memory system of claim 17 further includes: a page buffer coupled to the second node and used to adjust the voltage level of the second node according to the total number, wherein the total number is equal to the number of operands having a first logic value in the operation result, a larger resistance value of the page buffer when the total number is larger, a smaller resistance value of the page buffer when the total number is smaller, and a larger voltage level of the first node when the first threshold value is larger.

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