Embedded flash memory below 110nm and its fabrication method

Abstract

An embedded flash memory with a wavelength below 110nm and its fabrication method are disclosed. The embedded flash memory with a wavelength below 110nm includes: a substrate, a storage array region and a peripheral logic region on the substrate. The storage array region contains at least one storage cell. The storage cell includes: a common source located in the substrate; a common line located above and connected to the common source; a pair of stacked gates located on both sides of the common line, each stacked gate including a floating gate and a vertically stacked control gate above it; and a pair of select gates located next to the non-common line sides of the two stacked gates. The peripheral logic region contains at least one logic transistor, and the logic transistor includes a logic gate. The control gate in the storage cell has the same height as the logic gate of the logic transistor. This embedded flash memory exhibits good performance, stability, and reliability, and its fabrication method is simple, convenient, and low-cost.

Claims

1. An embedded flash memory with a wavelength below 110nm, comprising: A substrate, and a storage array region and a peripheral logic region on the substrate, the storage array region including at least one storage cell, the storage cell comprising: a common source located in the substrate, a common line located above and connected to the common source; a pair of stacked gates located on both sides of the common line, each stacked gate including a floating gate and a control gate vertically stacked above it; a pair of select gates located next to the non-common line side of the two stacked gates; the peripheral logic region including at least one standard logic transistor, the standard logic transistor including a logic gate; the control gate in the storage cell having the same height as the logic gate of the standard logic transistor, and the control gate and the logic gate being formed by depositing gate material in the same deposition step and then etching them separately during the fabrication process of the standard logic transistor.

2. The embedded flash memory below 110nm as described in claim 1, wherein, The selected gate and the stacked gate have the same or substantially the same height. The selected gate includes upper and lower parts. There is a dielectric layer between the control gate and the floating gate in the stacked gate. The selected gate and the stacked gate have substantially the same height, which means that there is no dielectric layer between the upper and lower parts of the selected gate, resulting in its height being slightly lower than that of the stacked gate. The height difference is the height of the dielectric layer in the stacked gate.

3. Embedded flash memory below 110nm as described in claim 2, wherein, The selected gate has the same structure and height as the stacked gate; the height of the upper and lower parts of the selected gate is the same as that of the control gate and the floating gate, respectively, and there is also a dielectric layer between the upper and lower parts of the selected gate, with the same height as the dielectric layer in the stacked gate; the lower part of the selected gate is electrically connected to the top of the dielectric layer.

4. Embedded flash memory below 110nm as described in claim 2, wherein, The storage array includes rows and columns, and the storage cells in the storage array are arranged in the same direction. The line connecting the same parts of the two select gates in the storage cell is in the column direction. The upper part of the corresponding select gate and the control gate of each storage cell in each row are connected along the row to form a strip. The corresponding floating gates of each storage cell in each row are not connected and are disconnected at the gap between two adjacent storage cells. Alternatively, the line connecting the same parts of the two select gates in the storage cell is in the row direction, and the upper part of the corresponding select gate and the control gate of each storage cell in each column are connected along the column to form a strip. The corresponding floating gates of each storage cell in each column are not connected and are disconnected at the gap between two adjacent storage cells. The corresponding gate of each storage cell in each row or column refers to the gate that is in the same position in each storage cell in that row or column. These gates can be connected in a straight line along the direction of that row or column. The gate can be a selection gate, an upper part of a selection gate, a lower part of a selection gate, a control gate, or a floating gate.

5. Embedded flash memory below 110nm as described in claim 4, wherein, In the storage cell, the select gate and the stacked gate have the same structure and height; the heights of the upper and lower parts of the select gate are the same as those of the control gate and the floating gate, respectively, and there is also a dielectric layer between the upper and lower parts of the select gate, with the same height as that in the stacked gate; In the storage array, the line connecting the same parts of the two select gates in the storage cell is in the column direction, and the upper and lower parts of the corresponding select gates of each storage cell in each row, and the dielectric layer in between, are connected along the row to form a strip; In each row, there is at least one through-hole in the dielectric layer between the upper and lower strips of the vertically aligned select gates, with the bottom electrically connected to the surface of the lower strip of the select gate, and the top exposed to the top surface of the dielectric layer, so that the lower strip of the select gate is electrically conductive to the top of the dielectric layer; or In the storage array, the line connecting the same parts of the two selection gates in the storage cell is in the row direction. The upper and lower parts of the corresponding selection gates of each storage cell in each column, and the dielectric layer in between, are connected along the column to form a strip. In each column, there is at least one through-hole in the dielectric layer between the upper and lower strips of the vertically aligned selection gates. The bottom of the through-hole is electrically connected to the surface of the lower strip of the selection gate, and the top of the through-hole exposes the top surface of the dielectric layer, so that the lower strip of the selection gate is electrically connected to the top of the dielectric layer.

6. The embedded flash memory below 110nm as described in claim 5, wherein, In the storage array, the line connecting the same parts of the two select gates in the storage cell is in the column direction. In each row, there is also a via in the upper part of the select gate strip corresponding to the via in the lower dielectric layer. This via is electrically insulated from the surrounding upper part of the select gate strip, its bottom is connected to the via in the lower dielectric layer and is electrically connected internally, and its top is exposed above the top surface of the upper part of the select gate strip. Alternatively, in the storage array, the line connecting the same parts of the two select gates in the storage cell is in the row direction. In each column, there is also a via in the upper part of the select gate strip corresponding to the via in the lower dielectric layer. This via is electrically insulated from the surrounding upper part of the select gate strip, its bottom is connected to the via in the lower dielectric layer and is electrically connected internally, and its top is exposed above the top surface of the upper part of the select gate strip.

7. Embedded flash memory below 110nm as described in claim 5, wherein, In the storage array, the line connecting the same portions of the two select gates in the storage cell is in the column direction. In each row, every 16-32 storage cells along the row, there is a via in the dielectric layer between the upper and lower stripes of the vertically aligned select gates; or in the storage array, the line connecting the same portions of the two select gates in the storage cell is in the row direction. In each column, every 16-32 storage cells along the column, there is a via in the dielectric layer between the upper and lower stripes of the vertically aligned select gates.

8. An embedded flash memory of 110nm or less as described in any one of claims 1 to 7, wherein, It is an embedded flash memory device of 90nm and below.

9. A method for fabricating embedded flash memory below 110 nm, wherein the embedded flash memory is an embedded flash memory below 110 nm as described in any one of claims 1 to 8, the method comprising the steps of: forming the control gate in the storage cell and the logic gate in the standard logic transistor in such a manner that: in the same deposition step, a gate material is simultaneously deposited at predetermined locations in the storage array region and the peripheral logic region, and then the gate material deposited on the storage array region and the peripheral logic region is etched using different photomasks respectively.

10. The method for fabricating embedded flash memory below 110 nm as described in claim 9, wherein, The method further includes the following steps: Before forming the control gate and the logic gate, a deposition material is formed on the substrate surface of the peripheral logic region during the fabrication of the storage cells in the storage array, and the deposition material is removed by etching.

11. The method for fabricating embedded flash memory below 110 nm as described in claim 9 or 10, wherein, The selected gate comprises upper and lower parts, and a dielectric layer exists between the control gate and the floating gate of the stacked gate. The method further includes the following steps: When the selected gate and the stacked gate have the same height, a dielectric layer exists between the upper and lower parts of the selected gate, and the selected gate and the stacked gate are formed together through the same fabrication steps; or when there is no dielectric layer between the upper and lower parts of the selected gate, the height of the selected gate and the stacked gate are substantially the same, that is, the height of the selected gate is slightly lower than that of the stacked gate, and the height difference is the height of the dielectric layer in the stacked gate; in this case, the selected gate and the stacked gate are formed together through substantially the same fabrication steps, where substantially the same fabrication steps mean that the fabrication steps of the selected gate are different from those of the stacked gate except that the deposition and formation step of the dielectric layer in the stacked gate is missing.

12. The method for fabricating embedded flash memory below 110 nm as described in claim 11, wherein: The selected gate and the stacked gate in the storage cell have the same structure and height. The height of the upper and lower parts of the selected gate is the same as that of the control gate and the floating gate, respectively. There is a dielectric layer between the upper and lower parts of the selected gate, with the same height as that in the stacked gate. The lower part of the selected gate is electrically conductive to the top of the dielectric layer. The storage array includes rows and columns, and the arrangement direction of each storage cell in the array is the same. The method includes the following steps in sequence: (1) On the substrate, a layer of thallium oxide material and a layer of lower gate material are deposited one after the other. Then, using a photomask, the deposited lower gate material layer is etched away at the gap between adjacent storage cells in the predetermined storage array area, at the location between the floating gates corresponding to the predetermined adjacent storage cells, and the deposited lower gate material layer is etched away in the predetermined peripheral logic area. However, no etching is performed at the location between the lower parts of the selected gates corresponding to the predetermined adjacent storage cells. When the line connecting the same locations of two select gates in the storage cell is in the column direction, the etching to remove the deposited lower gate material layer at the gap between adjacent storage cells in the predetermined storage array area, at the location between the corresponding floating gates of the predetermined adjacent storage cells, is performed along the row direction, in the region of each predetermined row of storage cells, at the location between the corresponding floating gates of the predetermined adjacent storage cells; or when the line connecting the same locations of two select gates in the storage cell is in the row direction, the etching to remove the deposited lower gate material layer at the gap between adjacent storage cells in the predetermined storage array area, at the location between the corresponding floating gates of the predetermined adjacent storage cells, is performed along the column direction, in the region of each predetermined column of storage cells, at the location between the corresponding floating gates of the predetermined adjacent storage cells. (2) A dielectric layer is deposited simultaneously on the lower gate layer in the storage array region and on the gate oxide layer in the peripheral logic region; then, a photomask is used to etch through the dielectric layer deposited in the storage array region to form vias, and the dielectric layer deposited in the peripheral logic region is etched away. The method of etching vias in a dielectric layer deposited in the storage array region includes: When the line connecting the same locations of two select gates in the storage cell is in the column direction, etching at least one via in the dielectric layer above the region of the lower portion of a predetermined select gate in each predetermined row of storage cells, wherein the bottom of the via contacts the surface of the lower gate layer and the top of the via exposes the top surface of the dielectric layer; When the line connecting the same locations of two select gates in the storage cell is in the row direction, etching at least one via in the dielectric layer above the region of the lower portion of a predetermined select gate in each predetermined column of storage cells, wherein the bottom of the via contacts the surface of the lower gate layer and the top of the via exposes the top surface of the dielectric layer. (3) On the dielectric layer in the storage array region and on the gate oxide layer in the peripheral logic region, an upper gate material is deposited simultaneously; then, in the storage array region, a photomask is used to simultaneously etch down to the gate oxide layer in the area other than the predetermined select gate and control gate, removing the upper and lower gate material layers and the dielectric layer in between in these areas, and forming the strip of the upper part of the select gate, the strip of the lower part of the select gate, the strip of the control gate, and the floating gate; then, in the peripheral logic region, a photomask is used to etch away the upper gate material layer in the area other than the predetermined logic gate to form the logic gate.

13. The method for fabricating embedded flash memory below 110 nm as described in claim 12, wherein: The etching of vias in the dielectric layer deposited in the storage array region includes: when the direction of the line connecting the same locations of two select gates in the storage cell is column-oriented, etching at least one via in the dielectric layer above the region below the predetermined select gate at positions every predetermined 16-32 storage cells in each predetermined row of storage cells; and when the direction of the line connecting the same locations of two select gates in the storage cell is row-oriented, etching at least one via in the dielectric layer above the region below the predetermined select gate at positions every predetermined 16-32 storage cells in each predetermined column of storage cells.

14. The method for fabricating embedded flash memory below 110 nm as described in claim 12, wherein: The specific operation of etching to form upper select gate stripes, lower select gate stripes, control gate stripes, and floating gates in the storage array area is as follows: When the line connecting the same parts of two select gates in the storage cell is in the column direction, along the row direction, in a predetermined area of ​​each row of storage cells, two upper select gate stripes, two lower select gate stripes, two control gate stripes, and a floating gate are etched in each row; or when the line connecting the same parts of two select gates in the storage cell is in the row direction, along the column direction, in a predetermined area of ​​each column of storage cells, two upper select gate stripes, two lower select gate stripes, two control gate stripes, and a floating gate are etched in each column.

15. A method for fabricating embedded flash memory below 110 nm as described in any one of claims 12 to 14, wherein, The method further includes the following steps: before step (1), forming wells of storage cells in the storage array in the substrate; and between step (2) and step (3), forming wells of the standard logic transistors in the peripheral logic region, then removing the gate oxide layer formed in step (1) on the substrate surface of the peripheral logic region, and then regrowing the gate oxide layer of the logic region.

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