Energy efficient power distribution circuits for protection of sensitive information

Abstract

A power distribution circuit may include a comparator circuit consisting of an inverter. The inverter may be configured with a trip voltage (Vtrip) that is different from half (VDD / 2) of a supply voltage for further energy efficiency in discharging a charge storage device used for safety in the power distribution circuit.

Description

Technical Field

[0001] This disclosure relates to energy-efficient power distribution circuits for protecting sensitive information. Prior Technology

[0002] Integrated circuits (ICs) may include designs containing sensitive information. One example of such sensitive information is key information used in cryptographic engine implementations (such as AES). Attempts to access secure or sensitive information (cryptographically compiled or otherwise) on an IC can be carried out via unauthorized or unintended access methods used on the circuit. Such methods include side-channel attacks, in which an adversary searches for information about the secure or sensitive information from the circuit's power characteristics, electromagnetic characteristics, or other physical characteristics. Summary of the Invention

[0003] An energy-efficient power distribution circuit is provided for protecting sensitive information. The power distribution circuit includes an energy-efficient comparator circuit system with a low-power inverter.

[0004] The energy efficiency comparator circuit system may include an inverting stage configured with a trip voltage greater than half a supply voltage (VDD / 2), and a buffer stage coupled to an output of the inverting stage. The trip voltage (Vtrip) is the input voltage point in the voltage transfer characteristic diagram of an inverter, such as a complementary metal-oxide-semiconductor (CMOS) inverter, where the output voltage equals the input voltage. When the input crosses Vtrip, the output state of the inverter changes.

[0005] In one implementation example, the Vtrip of the inverter in the inverting stage is used as the reference voltage for the comparator.

[0006] In another implementation example, the inverter stage consists of a reference voltage stage and an input stage, both of which include inverters. The reference voltage stage is configured to accommodate process and temperature variations, and the input stage is configured to provide Vtrip > VDD / 2, where Vtrip equals Vref, and Vref is the input voltage of the reference stage.

[0007] A power distribution circuit may include an energy-efficient comparator circuit with a low-power inverter for controlling the discharge of a portion of a charge storage device. The charge storage device is used to supply power to a sensitive or safety circuit system and is replenished by a voltage supply. The comparator monitors the voltage of the charge storage device and triggers (e.g., opens / closes) a shunt switch when the voltage of the charge storage device drops below a reference voltage. The power distribution circuit may further include at least one supply trigger and one logic trigger. The supply trigger controls when the charge storage device is coupled to a supply voltage, for example, to replenish the voltage on the charge storage device. The logic trigger controls when the charge storage device is coupled to a circuit system powered by the power distribution circuit so that the circuit system can be powered using the voltage on the charge storage device.

[0008] This [Summary of the Invention] is provided to introduce, in a simplified form, a concept selection further described below in the [Embodiments]. This [Summary of the Invention] is not intended to identify key or important features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Simple Explanation of the Diagram

[0009] Figure 1A shows an example circuit diagram of a simplified power distribution circuit.

[0010] Figure 1B illustrates an exemplary implementation of a switching capacitor circuit used in a power distribution circuit.

[0011] Figure 2 shows a functional diagram of an energy efficiency comparator circuit.

[0012] Figure 3A illustrates an example of a biased inverting comparator.

[0013] Figure 3B illustrates an example of a biased inverting comparator with planned trip voltage and power gate control.

[0014] Figures 4A and 4B are plots illustrating the voltage transfer characteristics (VTC) of an example operating state of a biased inverting comparator.

[0015] Figure 5A illustrates one of the power distribution circuits in which a partial discharge scheme is applied.

[0016] Figure 5B shows a timing diagram and the corresponding voltage of the charge storage capacitor and the comparator output waveform for the power distribution circuit shown in Figure 5A using a biased inverting comparator.

[0017] Figure 6A illustrates an example of a variable tolerance inverting comparator and an optional power gate.

[0018] Figure 6B illustrates an exemplary variation-tolerant inverting comparator with a common variation compensation device for both the reference voltage stage and the input stage.

[0019] Figures 7A-7I illustrate the electrical characteristics of an exemplary implementation of a variation-tolerant inverting comparator. Figures 7A to 7F show VTC for Vo1 (e.g., Figures 7A to 7C) and Vout (e.g., Figures 7D to 7F) across process (SS, FF, SF, FS, TT) and temperature (-40°C, 25°C, 125°C) at a 0.99 V supply voltage; Figures 7G to 7I show Vbias across different Vref, process (SS, FF, SF, FS, TT), and temperature (-40°C, 25°C, 125°C) at a 0.99 V supply voltage.

[0020] Figure 8A illustrates one of the power distribution circuits in which a partial discharge scheme is applied.

[0021] Figure 8B illustrates a practical example of a power distribution circuit shown in Figure 8A using a voltage divider as a reference voltage.

[0022] Figure 8C shows a timing diagram and the corresponding voltage of the charge storage capacitor and the comparator output waveform for the power distribution circuit shown in Figure 8B, which uses a variation-tolerant inverting comparator. Implementation

[0023] An energy-efficient power distribution circuit is provided for protecting sensitive information. The power distribution circuit includes an energy-efficient comparator circuit system with a low-power inverter.

[0024] Figure 1A illustrates an exemplary circuit diagram of a simplified power distribution circuit. The exemplary simplified power distribution circuit 100 includes a charge storage device (e.g., a capacitor) 110, a switch 120, and a comparator 130. The charge storage device 110 (via an internal power node) supplies power to at least a portion of a circuit that may contain security or sensitive information; and is replenished by a power supply (not shown) according to any suitable timing or triggering. To make it difficult to read circuit operation from the depletion and replenishment of the charge storage device 110, a discharge operation can be performed from a branch (for example, via switch 120), such that the replenishment of the charge storage device does not correspond to the consumption by the circuit.

[0025] Comparator 130 is coupled to the charge storage device to receive a voltage value from the charge storage device and outputs a signal to shunt switch 120. Comparator 130 monitors the voltage of charge storage device 110 and triggers (for example, opens / blocks) shunt switch 120 when the voltage drops below a threshold voltage Vref. This ensures that the voltage across charge storage device 110 remains at a consistent value each time it is replenished. This arrangement can be used to provide isolation between the circuit's power consumption and the power supply line, thereby providing protection against side-channel attacks.

[0026] Figure 1B illustrates an exemplary implementation of a switching capacitor circuit used in a power distribution circuit. Vdd_Supply is the input supply voltage, and Vdd_Critical is the output of the switching capacitor circuit supplying power to a sensitive or safety circuit system. An exemplary implementation of the switching capacitor circuit 140 includes a critical capacitor 150 for the charge storage device 110, a shunt switch 120, and a comparator 130. Additionally, the switching capacitor circuit 140 includes a first switch 160 controlled by clock S1, a second switch 170 controlled by clock S2, and a third switch 180 controlled by clock S3.

[0027] The challenge of using available techniques with a switching capacitor circuit lies in the additional power load caused by the circuit's power consumption. For Internet of Things (IoT), embedded user identity modules (eSIM), and integrated user identity modules (iSIM) applications, as well as other low-voltage, low-power, and battery-operated applications, any improvement in power consumption while providing the security performance available via a switching capacitor circuit is desirable. Helpfully, the energy-efficient comparator circuit system with a low-power inverter described herein can contribute to the aforementioned power savings. Furthermore, as shown in Figures 1A and 1B, the comparator circuit described herein can be used to partially discharge the charge storage device 110 (or critical capacitor 150) via the shunt switch 120, enabling less charge waste.

[0028] Specifically, regarding Figure 1B, for optimal power saving, comparator 130 should be fast enough that it immediately blocks the S3 path when Vdd_Capi equals Vref. In a partial discharge scheme feasible for the switched capacitor circuit, Vdd_Capi is discharged down to a level set by Vref, rather than fully discharged (discharging to the second power rail, e.g., to Vss). When the critical capacitor 150 discharges to its maximum voltage, it needs a significant voltage charge to reach Vdd_Supply when the first switch 160 is turned on by the S1 clock. Furthermore, power saving is achieved by bringing Vref closer to Vdd_critical (e.g., greater than Vdd_Supply / 2). However, due to the limited time delay of comparator 130 and the switches involved in the S3 phase of the cycle (e.g., switches 120 and 180), Vdd_Capi always falls below Vref at the end of the S3 phase, resulting in less power saving than intended.

[0029] The "integrated design" of comparator 130 and the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) sizes in, for example, shunt switch 120 and third switch 180, improves power efficiency. As mentioned above, the duration of the S3 phase (a constant fixed by the design) > comparator delay + time to discharge the critical capacitor to Vref + switching and parasitic delays. Therefore, the sum of all three different delay components must be less than the duration of the S3 phase. The difference between Vdd_Capi when Vdd_Capi reaches Vref and when the S3 path (e.g., switch 120) is blocked by comparator 130 is directly proportional to the delay of comparator 130 and the discharge rate through the S3 path switch. If the comparator delay is smaller, the size of the MOSFETs forming the S3 path switch can be adjusted to reduce the discharge rate. This means that Vdd_Capi is close to Vref at the end of the S3 phase, causing the comparator to quickly block S3 before the end of the S3 phase. This slow discharge rate also ensures less charge waste during the delay period of comparator 130.

[0030] Alternatively, increasing the duration of stage S3 loosens the delay specification of comparator 130, allowing for a slower discharge of the critical capacitor 150 and saving more power. In this case, the durations of clocks S1 and S2 are reduced. The reverse is also true when comparator 130 has a larger delay and this is the case for most of the time (i.e., less power saving). This is because the critical capacitor 150 can be implemented as one of the MOS capacitors with a non-linear CV (capacitance-voltage) characteristic (to achieve higher capacitance density). As in any standard MOS capacitor, the capacitance decreases at a faster rate as the voltage across it decreases during discharge. This smaller capacitance results in less charge conservation (Q=CV), and therefore less power saving. Furthermore, even if partial discharge techniques can improve power saving, the critical capacitor 150 still depends on the CV characteristic, which affects power saving. Therefore, a fast comparator is desirable, making designers less dependent on the physical behavior of capacitor 150 for power saving.

[0031] Figure 2 illustrates a functional diagram of an energy efficiency comparator circuit. Comparator circuit 200 can be used to implement comparator 130 and includes an inverting stage 210 and a buffer stage 220 configured with a breakout voltage value that differs from half of a supply voltage value. Inverting stage 210 includes a pull-up network and a pull-down network, wherein the breakout voltage value is set by the ratio of the drive strength (or on-resistance) of the pull-up network and the pull-down network. In some cases, inverting stage 210 can be implemented using a complementary metal-oxide-semiconductor (CMOS) inverter (with a pull-up network composed of p-channel MOSFETs (PMOS transistors) and a pull-down network composed of n-channel MOSFETs (NMOS transistors). A CMOS inverter is a digital circuit. However, it is possible to use a CMOS inverter relative to a reference value to compare an analog voltage.

[0032] The jump voltage (Vtrip) is the input voltage point on the voltage transfer characteristic diagram of this inverter, where the output voltage equals the input voltage. When the input crosses Vtrip, the output state of the inverter changes. Typically, for digital applications, Vtrip is set to VDD / 2 (half the supply voltage value) to provide a large noise margin for logic 1 (high) and logic 0 (low). For the analog comparator applications described herein, the inverter's Vtrip is set differently from VDD / 2 (e.g., a reference voltage value compared to the input voltage).

[0033] Circuits implemented using CMOS devices are generally considered to have lower power consumption. In addition, a CMOS inverter can be configured with a breakout voltage value that is more than half the supply voltage value, as discussed in this paper, which can further reduce power consumption (and positively influence timing delays to meet the needs of power distribution circuits).

[0034] The comparator circuit 200 can also be implemented using advanced CMOS technology, as well as technologies different from CMOS using suitable design techniques (e.g., technologies other than bulk CMOS or SOI CMOS). For example, in some cases, the inverter of the comparator circuit 200 can be implemented to achieve a higher Vtrip by using an SLVT (ultra-low threshold voltage) P-type FET for stronger pull-up and an LVT (low threshold voltage) / SVT (standard threshold voltage) / HVT (high threshold voltage) N-type FET for weaker pull-down. In other implementations, a single PFET with a larger width and a single NFET with a smaller width can be used.

[0035] In one implementation of the inverting stage 210, the inverter's trip voltage (Vtrip) serves as the reference voltage Vref. This implementation is called a biased inverting comparator. By providing a Vtrip greater than VDD / 2 and using Vtrip as Vref, it is possible to partially discharge a charge storage device in a switched capacitor circuit.

[0036] Figure 3A illustrates an exemplary biased inverting comparator. A biased inverting comparator 300 includes an inverting stage comprised of a CMOS inverter 310 coupled to receive an input voltage (Vin_P), and a buffer stage coupled to an output of the inverting stage. The CMOS inverter 310 includes at least one PMOS transistor and at least one NMOS transistor configured to bias the CMOS inverter such that Vtrip > VDD / 2. Therefore, the CMOS inverter 310 can be referred to as a biased inverter. By making the number of NMOS transistors greater than the number of PMOS transistors, the CMOS inverter 310 can be biased such that Vtrip > VDD / 2. In the illustrated example, the CMOS inverter 310 has one PMOS transistor (M0) and five NMOS transistors (M1, M2, M3, M4, M5).

[0037] In some cases, the CMOS inverter 310 can be biased to Vtrip > VDD / 2 by adjusting the size gradient of the at least one PMOS transistor and the at least one NMOS transistor. Indeed, different pull-up and pull-down network strengths can be achieved by using various MOSFET sizes (channel length and width) and various MOSFET selections with different threshold voltages (Vth) available in a fabrication technology. For example, using a low-Vth MOSFET can provide lower on-resistance, while a high-Vth MOSFET provides even higher on-resistance. A higher-resistance network (i.e., lower drive strength) can also be achieved by connecting more than two MOSFETs in series, as in the case shown in Figure 3A. The backing effect of the MOSFET also contributes to increasing the on-resistance of the network.

[0038] To maintain a non-inverting output in this particular instance, the buffer stage consists of an odd number of buffers. The number and size of the buffer stages can be designed depending on the required output type (i.e., inverting or non-inverting), load capacitance, and delay.

[0039] Here, the buffer stage includes a first buffer 320 coupled to receive the output (Vo1) of the CMOS inverter 310 of the inverting stage, a second buffer 330 coupled to receive the output (Vo2) of the first buffer 320, and a third buffer 340 coupled to receive the output (Vo3) of the second buffer 320 and output a comparator result as an output voltage (Vout). Each buffer 320, 330, and 340 may be constructed from PMOS / NMOS pairs (M6 / M7, M8 / M9, M10 / M11, unbiased) and configured to appropriately drive a load.

[0040] The first buffer 320 can be designed as one of the smallest possible inverters in the technology to provide minimal load to the biased inverter 310. Due to the increased pull-down network resistance of the biased inverter stage implemented by the CMOS inverter 310, the minimum size of the first buffer 320 helps to reduce heavy rotation when Vo1 switches from high to low at high speed.

[0041] Figure 3B illustrates an exemplary biased inverting comparator with programmed trip voltage and power gate control. The biased inverting comparator 350 with programmed trip voltage includes an inverting stage 360 ​​composed of a programmed selection circuit consisting of a CMOS inverter 362 and a set of bypass switches 364. The inverting stage 360 ​​is coupled to receive an input voltage (Vin_P) and outputs a signal (Vo1) to a buffer stage of the biased inverting comparator 350.

[0042] In the example shown in Figure 3B, the bypass switch 364 includes three bypass transistors MNVRF0, MNVRF1, and MNVRF2, which can be turned on by inputs vref_sel_v0, vref_sel_v1, and vref_sel_v2, respectively. MOSFETs M1 and M2 can be bypassed by setting vref_sel_v2 to a high level; M1, M2, and M3 can be bypassed by setting vref_sel_v1 to a high level; and M1, M2, M3, and M4 can be bypassed by setting vref_sel_v0 to a high level. Bypassing a larger number of NMOSFETs in the pull-down network of the biased inverter 362 changes the drive strength ratio of the biased inverter, resulting in a variable Vtrip value. This is one example of Vtrip programmability. It should be understood that in some situations, in addition to the planned selection of NMOS transistors or as an alternative to the planned selection, a planned selection can also be applied to a network of PMOS transistors.

[0043] Just as with the biased inverting comparator 300, for the biased inverting comparator 350, in order to maintain a non-inverting output, the buffer stage can be composed of an odd number of buffers. The number and size of the buffer stages can be designed depending on the required output type (i.e., inverting or non-inverting), load capacitance, and delay.

[0044] Here, the buffer stage includes a first buffer 370 coupled to receive the output (Vo1) of the CMOS inverter 362 of the inverter stage 360, a second buffer 380 coupled to receive the output (Vo2) of the first buffer 370, and a third buffer 390 coupled to receive the output (Vo3) of the second buffer 380 and output a comparator result as an output voltage (Vout). Each buffer 370, 380, and 390 may be constructed from PMOS / NMOS pairs (M6 / M7, M8 / M9, M10 / M11, unbiased) and configured to appropriately drive a load. Additionally, the first buffer 370 may be designed as one of the smallest possible inverters in the art to provide minimal load to the biased inverter 362. As the pull-down network resistance of the biased inverter stage implemented by CMOS inverter 362 increases, the minimum size classification of the first buffer 370 helps to reduce heavy rotation when Vo1 switches from high to low at high speed.

[0045] In some cases, a power gate may be included in a biased comparator inverter design. Although the biased inverting comparator 350 is shown with optional power gate, it should be understood that the power gate can still be omitted from the biased inverting comparator 350. Alternatively, power gate may also be applied to the biased inverting comparator 300 of FIG3A.

[0046] Power gate control can be implemented by adding power gate transistors (e.g., MOSFETs), such as the PMG 392 (a PMOS) and / or the NMG 394 (an NMOS). The power gate MOSFETs can be controlled by complementary digital signals Comp_En_B and Comp_En, respectively. In addition to their useful functions for power gate control in low-power applications, these devices provide additional safety for the circuit. For example, referring to Figure 1A, since the voltage waveform across the charge storage device 110 is a function of the activity of the circuit supplying power to the charge storage device 110, characteristics of the circuit activity can be detected as side-channel leakage due to changes in displacement current through parasitic capacitive paths. Side-channel leakage can be reduced by increasing the parasitic path impedance through more series (parasitic) capacitance, such as by including the PMG 392 and NMG 394 in comparator 130.

[0047] Although the breakout voltage of CMOS inverter 310 and the available breakout voltage of CMOS inverter 362 are set by the strength ratio of the pull-up and pull-down networks, the actual size of the transistor can still be selected based on the delay, operating frequency, and Vtrip PVT (process, voltage, and temperature) variation specifications.

[0048] For example, referring to Figure 1B, in a partial discharge application of the critical capacitor 150, the voltage Vdd_Capi is connected to the input of comparator 130. When Vdd_Capi decreases during the conduction phase of the third switch 180, Vo1 (in Figures 3A or 3B) increases. Therefore, accelerating this increase in Vo1 helps reduce the overall comparator delay, resulting in greater power savings during partial discharge operation. For example, this can be achieved by selecting a larger M0 width, which in turn determines the size of all other MOSFETs in the biased inverting stage based on a specific ratio of Vtrip.

[0049] The capacitance between the inputs and outputs of each stage also plays a significant role in the overall delay. The Miller effect amplifies the effect of these capacitances, thus having a significant impact and should be considered during circuit and layout design.

[0050] Finally, Vtrip can be set through DC analysis and VTC of the inverter. The actual value is set through transient analysis. One of these two analyses, the iterative method, is used to design skewed inverting comparators, while the "overall design" method (explained earlier) is used to design the overall partial discharge circuit layout.

[0051] Figures 4A and 4B are plots illustrating the voltage transfer characteristics (VTC) of an exemplary implementation of a biased inverting comparator. Figure 4A shows the voltage transfer characteristics (Vo1 to Vin_P) of the inverting stage of a biased inverting comparator such as that shown in Figure 3A; and Figure 4B shows the voltage transfer characteristics (Vout to Vin_P) of a biased inverting comparator such as that shown in Figure 3A.

[0052] The plot in Figure 4A is obtained by simulating a DC voltage in Vin_P and observing Vo1 using an exemplary analog scan of the biased inverting comparator in Figure 3A. The Vtrip at the corner of the TT, 0.99 V, 25C (center curve) is 686.6125 mV. The Vtrip varies depending on the process (SS, SF, FS, FF, TT) and temperature (-40C, 25C, 125C) from approximately 603 mV to approximately 783 mV (at a 0.99 V supply voltage), as indicated by the two points on the plot.

[0053] Figure 4B shows the response of Vout to Vin_P as it changes from VSS to VDD. The Vtrip of the full-biased inverting comparator is the intersection of the Vout and Vin_P curves. The process (SS, SF, FS, FF, TT) and temperature (-40°C, 25°C, 125°C) dependent variation (at a supply voltage of -0.99 V) of the Vtrip of the full-biased inverting comparator ranges from approximately 626 mV to approximately 818 mV, as indicated by the two points in the graph. All Vtrip values ​​are significantly higher than VDD / 2 (450 mV). Therefore, it is named a "biased inverting comparator".

[0054] One type of biased inverting comparator, such as the biased inverting comparator 300 or 350, can be connected to a portion of the discharge technique in a switching capacitor circuit of a power distribution circuit to provide power saving.

[0055] Figure 5A illustrates one of the power distribution circuits employing a partial discharge scheme; and Figure 5B shows the power distribution circuit shown in Figure 5A using a biased inverting comparator, illustrating a timing diagram and the corresponding voltage of the charge storage capacitor and the comparator output waveform.

[0056] Referring to Figure 5A, a power distribution circuit 500 can be configured according to the switching capacitor circuit of Figure 1B. Specifically, the power distribution circuit 500 includes a critical capacitor 510, a shunt switch 520, a comparator 530, a first switch 540 controlled by clock S1, a second switch 550 controlled by clock S2, and a third switch 560 controlled by clock S3. The comparator 530 can be configured as a biased inverting comparator, as described with respect to biased inverting comparator 300 or biased inverting comparator 350. The inputs connected to the comparator 530 shown in Figure 5A include a first supply rail (Vdd_supply), a second supply rail (Vss), and a critical capacitor voltage (Vdd_Capi). The critical capacitor voltage is connected to the Vin_P input shown in Figure 3A or 3B. An external reference voltage input is not shown because the Vtrip of the comparator 530 acts as a reference voltage.

[0057] Referring to Figure 5B, in the time domain, clocks S1 and S2 are shown independently, and clock S3 is shown as the output (Vout) and Vdd_Capi waveforms of a biased inverting comparator (for one of the PVT corners for partial discharge and for full discharge). As can be seen, clock S3 has a pulse width much smaller than clocks S1 and S2. Within this pulse duration, it is expected that (for example, comparator 530) the overall comparator response and (for example, switch 520) the shunt switch response will occur. This means that the sum of the delays of the comparator and the entire switching network should be less than the duration of this pulse, which is difficult to achieve with a typical analog comparator because to make an analog comparator act as quickly as possible, it would consume a significant amount of current (and thus electrical charge). Helpfully, during the S3 conduction phase, the partial discharge Vdd_Capi value of the biased inverting comparator for the partial discharge scheme did not drop below 561.72 mV (where Vdd_Supply = 1.1 V). Of course, since the full discharge Vdd_Capi value also drops to 1.16462 mV (approximately 0 V), the full discharge scheme could potentially operate for the duration of the S3 clock cycle; however, as mentioned above, this scheme consumes more power. The blocking of the shunt switch 520 is accomplished by the output signal (Vout) of the biased inverting comparator, which prevents any further discharge of Critical_Cap, thereby reducing power consumption. It should be understood that this is one example of circuit operation, and specific values ​​can vary depending on the technology, PVT angle, and specifications.

[0058] As mentioned above, by using a CMOS inverter as part of the comparator circuit, it is possible to introduce less delay (compared to existing analog comparator circuits), lower power consumption (due to the absence of DC bias), and Vtrip variability that is directly proportional to the inverter's supply voltage (for example, as the VDD supply increases, its output voltage increases, and Vref can increase accordingly because Vtrip increases along with the VDD supply). It should be noted that Vtrip values ​​will vary significantly across process and temperature, requiring designers to ensure during the design phase that Vtrip across all PVT corners and operating conditions is not equal to or greater than Vdd_Critical (the output voltage of the switched capacitor circuit) to ensure effective protection against side-channel attacks (and recognizing that this may lead to trade-offs regarding power saving). Using MOSFETs (e.g., MOSFETs for analog applications) in a manufacturing process, taking advantage of their smaller variations in process, voltage, and temperature variability, can also reduce Vtrip variability.

[0059] In another implementation of the inverting stage 210, the reference voltage is set by a reference circuit or by a simple resistive or capacitive voltage divider. The inverting stage 210 can therefore consist of two stages: a reference voltage stage and an input stage. The reference voltage stage is configured to achieve (process and temperature) variation tolerance and also to set the Vtrip of the input stage to be equal to Vref (i.e., the input voltage connected to the reference voltage stage, for example, to achieve a value greater than VDD / 2). This implementation can be called a variation-tolerant inverting comparator. In yet another implementation of the inverting stage 210, both the reference voltage stage and the input stage of the inverting stage 210 are configured using a common transistor to achieve process and temperature variation tolerance. This implementation can also be called a variation-tolerant inverting comparator. Both implementations tolerate process and temperature variations.

[0060] For a variation-tolerant inverting comparator, the reference voltage can be set by applying the desired voltage to the Vref terminal input of the reference voltage level. In some cases, Vref can be set by a reference circuit such as a bandgap voltage reference circuit or by a resistive (or capacitive) voltage divider, depending on the application and implementation (for example, for one example of a resistive voltage divider, see Figure 8B). Similar to a biased inverting comparator, a variation-tolerant inverting comparator utilizes the properties of a digital inverter for its advantages. For example, it has less delay and power consumption compared to an analog comparator because there is no DC bias current.

[0061] Figure 6A illustrates an exemplary variation-tolerant inverting comparator and an optional power gate; and Figure 6B illustrates an exemplary variation-tolerant inverting comparator with a common variation compensation device for both the reference voltage stage and the input stage.

[0062] Referring to Figure 6A, a variation-tolerant inverting comparator 600 includes an inverting stage consisting of a reference voltage stage 605 and an input stage 610; and a buffer stage coupled to an output of the inverting stage.

[0063] The buffer stage can be composed of an odd number of buffers. The number and size of the buffer stages can be designed depending on the required output type (i.e., inverting or non-inverting), load capacitance, and delay. Here, the buffer stage includes a first buffer 615 coupled to receive the output (Vo1) of the input stage 610, a second buffer 620 coupled to receive the output (Vo2) of the first buffer 615, and a third buffer 625 coupled to receive the output (Vo3) of the second buffer 620 and output a comparator result as an output voltage (Vout). Each buffer 615, 620, 625 can be composed of PMOS / NMOS pairs (MPB1 / MNB1, MPB2 / MNB2, MPB3 / MNB3, unbiased) and configured to appropriately drive the load.

[0064] Reference voltage stage 605 includes a CMOS inverter with transistor pairs MPREF and MNREF, the inputs of which (at Vref) serve as a reference voltage for variation-tolerant inverting comparator 600; and input stage 610 includes a CMOS inverter with transistor pairs MPI1 and MNI2, which (as copies and in the layout) are matched to the transistor pairs MPREF and MNREF of reference voltage stage 605. The input of input stage 610 is connected to the input of the comparator (Vin_P).

[0065] Due to process variations and temperature, the transistors of these two CMOS inverters may have different strengths. To compensate for these variations, the reference voltage stage 605 further includes a pull-up compensation transistor MPFB1 and a pull-down compensation transistor MNFB1; and the input stage 610 further includes a pull-up compensation transistor MPFB2 and a pull-down compensation transistor MNFB2.

[0066] Compensating transistors MPFB1 and MNFB1 are coupled to the CMOS inverter of the reference voltage level 605 to form two negative feedback loops, which helps improve the process and temperature variation tolerance of comparator 600. The loop with MPFB1, MPREF, and the attached bias (Vbias) output node forms a loop for controlling the pull-up network. The loop with MNFB1, MNREF, and the attached Vbias output node forms a loop for controlling the pull-down network.

[0067] The CMOS inverter of input stage 610 is biased, so that Vtrip > VDD / 2 to Vbias through Vbias, where Vbias is the output of reference voltage stage 605. That is, the trip point voltage (Vtrip) of input stage 610 is equal to (with a small actual variation) the voltage applied to the Vref terminal of reference voltage stage.

[0068] As mentioned earlier, the Vtrip of an inverter is controlled by the strength of the pull-up and pull-down networks. Therefore, for a Vtrip > VDD / 2, due to MNI1 and MNFB2, the pull-up network in input stage 610 (with MPFB2 and MPI1) should provide a higher drive strength (lower resistance) than the pull-down network of that stage. The strength of the pull-up and pull-down networks is controlled by the voltage Vbias. Vbias is not a digital (binary) signal, but can take a continuous value. The value of Vbias is a function of Vref, process, and temperature. Vbias has two roles, and their combined effect determines the value of Vbias. First, the Vtrip of input stage 610 must be set to be equal to Vref. Second, variations due to process and temperature changes must be compensated for.

[0069] Regarding the first point about Vref controlling Vbias to set the Vtrip of the input stage 610, if Vref > VDD / 2, then MNREF in the pull-down network has better drive strength than MPREF in the pull-up network. Therefore, Vbias ≦ VDD / 2. If Vref < VDD / 2, then MPREF in the pull-up network has better drive strength than MNREF in the pull-down network, and Vbias ≧ VDD / 2. When Vref = VDD / 2, both MNREF and MPREF have the same drive strength, and Vbias is approximately VDD / 2. A Vref closer to or equal to the rail (e.g., VDD or VSS) will block the MOSFET, and the circuit will become inoperable. Therefore, the Vref value should be properly within the range of (VDD-Vtp) and Vtn, where Vtp and Vtn are the threshold voltages of the PMOS and NMOS FETs, respectively. Therefore, choosing a MOSFET with a smaller threshold voltage helps to operate over a larger Vref range at the cost of higher current consumption.

[0070] Devices MPFB1 and MNFB1 do not allow Vbias to vary with the rail-to-rail supply voltage (such as a digital signal). As mentioned above, MPFB1 and MNFB1 are part of the negative feedback loop, which keeps Vbias within a certain range of approximately VDD / 2. A decrease in Vbias is achieved by controlling the gate of the source voltage (Vgs) connected to MNFB1 to reduce the strength of the pull-down network (resistors provided by MNREF and MNFB1), and by controlling Vgs of MPFB1 to increase the strength of the pull-up network (resistors provided by MPFB1 and MPREF). This increase in the pull-up network drive further increases Vbias to a smaller value; thus, the drive strength of the pull-up network is reduced to a stable level (and negative feedback). However, the value of Vbias is an optimal function of Vref and is only slightly affected by negative feedback. An increase in Vbias leads to a decrease in the control of the pull-up and pull-down networks. Therefore, the feedback loop ensures that Vbias does not transition to VDD or VSS. For a given Vref, this feedback control leads to a steady state of Vbias. This steady state is reached once the pull-up and pull-down networks of the Vref stage achieve equal drive strength through the feedback operation.

[0071] Regarding the second point about the impact of process and temperature variations on compensation, it is known that the on-resistance (Rds) of a MOSFET varies with process and temperature. This means that the drive strength of the pull-up and pull-down networks also varies with process and temperature. The negative feedback loop in reference voltage stage 605 compensates for this variation in Vtrip drive strength based on process and temperature. As explained in detail below, Vbias is an optimal function of Vref because the strength of the pull-up and pull-down networks depends on the Rds of MPREF and MNREF, respectively. Any change in these strengths due to process and / or temperature variations causes a change in Vbias and the activation of the negative feedback loop; and the negative feedback loop compensates for this change in Vbias. Therefore, Vbias simply (or to a large extent) becomes only a function of Vref.

[0072] In fact, Vbias is inversely proportional to Vref. Therefore, Vref > VDD / 2, resulting in Vbias ≦ VDD / 2. A smaller Vbias makes the pull-down network of input stage 610 weaker, while the pull-up network of input stage 610 is stronger. This tilt in the drive strength of the pull-up and pull-down networks of input stage 610 causes its Vtrip to change from VDD / 2. Since input stage 610 is a copy of reference voltage stage 605, the drive strength of MPFB1 is equal to that of MPFB2, and the drive strength of MNFB1 is equal to that of MNFB2. However, MPFB2 is stronger than MNFB2. Therefore, a larger gate overdrive is required in MNI1 to change the state of Vo1 from high to low. A larger Vin_P value can provide this additional overdrive to MNI1 and equally reduce the gate overdrive of MPI1. The Vin_P value that Vo1 switches its state (or Vo1 equals Vin_P) becomes the Vtrip of input stage 610. With the help of a replica design and matching of reference voltage stage 605 and input stage 610, Vtrip equals Vref (with only minor variations).

[0073] Referring now to Figure 6B, the variation-tolerant inverting comparator 650 can be almost identical in design to the variation-tolerant inverting comparator 600 in Figure 6A, but MPFB2 and MNFB2 have been removed, and the widths of MPFB1 and MNFB1 have been doubled. That is, the compensation device is MPFB1, and MNFB1 is shared by both the reference voltage stage 660 and the input stage 670. As described with respect to the reference voltage stage 605 and the input stage 610, for the variation-tolerant inverting comparator 650, MPREF and MPI1 and MNREF and MNI1 are replicas and matched pairs.

[0074] Power gate control can be included in a variation-tolerant inverting comparator. While optional power gate control is shown in variation-tolerant inverting comparators 600 and 650, it should be understood that power gate control can still be omitted. As previously described with respect to Figure 3B, power gate control can be implemented by adding power gate MOSFETs, namely MPG, a PMOS power gate MOSFET 630, and MNG, an NMOS power gate MOSFET 635. The power gate MOSFETs can be controlled by complementary digital signals Comp_En_B and Comp_En, respectively. In addition to their function of power gate control, which is useful in low-power applications, these devices also provide additional safety for the circuit (e.g., to reduce side-channel leakage).

[0075] Because of the negative feedback loop in the circuit topology, the type of transistor used is largely unknown. As in any other circuit, it is preferable to use components whose characteristics change less with PVT. The size classification of the inverters (MPREF and MNREF, MPI1 and MNI1) is designed by first maintaining Vref = VDD / 2. At this Vref, it is expected that Vtrip of the input stage 610 equals Vref. This is ensured by selecting the inverter size classification. Any difference in drive strength due to improper inverter size classification will result in a larger comparator offset. The negative feedback loop may not be able to fully compensate for this difference in drive strength. The MOSFET width is selected based on the operating frequency. Higher speeds use a larger width (and therefore a smaller RC time constant), and vice versa. This also determines the area and power consumed by the comparator. The reference voltage stage 605 does consume some quiescent current due to its analog nature (caused by Vbias not reaching VDD or VSS to completely block the pull-down or pull-up networks, respectively). However, the current consumed by the input stage 610 depends on the input signal (Vin_P). For a given specification, the total current consumption is less than that of a conventional analog comparator. MPFB1, MPFB2, MNFB1, and MNFB2 can be made larger if needed, since they do not perform any high-frequency operation. The sizes of the power gates MPG and MNG are adjusted to minimize the voltage drop across them during normal comparator operation. The buffer stage is designed to achieve a smaller overall delay for the comparator. The capacitance between the inputs and outputs of each stage also plays a significant role in the overall delay. The Miller effect amplifies the effect of these capacitances, thus having a significant impact. Therefore, these capacitances should be taken into account in the circuit and layout design. The overall partial discharge circuit layout can be designed using the "overall design" method explained above.

[0076] Figures 7A-7I illustrate the electrical characteristics of an exemplary implementation of a variation-tolerant inverting comparator. Figures 7A to 7F show the VTC of Vo1 (e.g., Figures 7A to 7C) and Vout (e.g., Figures 7D to 7F) across process (SS, FF, SF, FS, TT) and temperature (-40°C, 25°C, 125°C) at a 0.99 V supply voltage. Specifically, Figure 7A shows the VTC (Vo1 to Vin_P) of a variation-tolerant inverting comparator 600 with Vref=300 mV, as shown in Figure 6A, where the maximum offset is approximately 34 mV; Figure 7B shows the VTC (Vo1 to Vin_P) of a variation-tolerant inverting comparator 600 with Vref=500 mV, as shown in Figure 6A, where the maximum offset is approximately 5.5 mV; Figure 7C shows the VTC (Vo1 to Vin_P) of a variation-tolerant inverting comparator 600 with Vref=800 mV, as shown in Figure 6A, where the maximum offset is approximately 61 mV; Figure 7D shows the VTC (Vout to Vin_P) of a variation-tolerant inverting comparator 600 with Vref=300 mV, as shown in Figure 6A, where the maximum offset is approximately 13 mV; and Figure 7E shows the VTC of a variation-tolerant inverting comparator 600 with Vref=500 mV, as shown in Figure 6A. (Vout to Vin_P), where the maximum offset is approximately 5 mV; and Figure 7F shows the VTC (Vout to Vin_P) of a variant-tolerant inverting comparator 600 with Vref=800 mV, as shown in Figure 6A, where the maximum offset is approximately 32.5 mV.

[0077] It can be observed that the maximum offset is much smaller than the Vtrip variation of the biased inverting comparator. Similarly, the variation-tolerant Vtrip in the inverting comparator is closer to the set Vref (which is quite different from Vdd / 2 in a conventional inverter). Therefore, this circuit can operate like a comparator.

[0078] Figures 7G to 7I illustrate Vbias across different Vrefs, processes (SS, FF, SF, FS, TT), and temperatures (-40°C, 25°C, 125°C) at a supply voltage of 0.99 V. The Vbias overview in Figures 7G to 7I relates to the combined effect of setting the input stage Vtrip equal to Vref and compensating for variations due to process and temperature changes. Specifically, Figure 7G shows the Vbias versus Vin_P relationship for a variation-tolerant inverting comparator 600 with Vref = 300 mV, as shown in Figure 6A; Figure 7H shows the Vbias versus Vin_P relationship for a variation-tolerant inverting comparator 600 with Vref = 500 mV, as shown in Figure 6A; and Figure 7I shows the Vbias versus Vin_P relationship for a variation-tolerant inverting comparator 600 with Vref = 800 mV, as shown in Figure 6A.

[0079] Figure 8A illustrates one of the power distribution circuits in which a partial discharge scheme is applied; Figure 8B illustrates an actual implementation of the power distribution circuit shown in Figure 8A with a voltage divider used as a reference voltage; and Figure 8C shows a timing diagram of the power distribution circuit shown in Figure 8B using a variable tolerance inverting comparator, along with the corresponding voltage of the charge storage capacitor and the comparator output waveform.

[0080] Referring to Figures 8A and 8B, a power distribution circuit 800 can be configured according to the switching capacitor circuit of Figure 1B. Specifically, the power distribution circuit 800 includes a critical capacitor 810, a shunt switch 820, a comparator 830, a first switch 840 controlled by clock S1, a second switch 850 controlled by clock S2, and a third switch 860 controlled by clock S3. The comparator 830 can be configured as a variation-tolerant inverting comparator, as described with respect to variation-tolerant inverting comparator 600 or variation-tolerant inverting comparator 650. The inputs connected to the comparator 830 shown in Figure 8A include a first supply rail (Vdd_supply), a second supply rail (Vss), a critical capacitor voltage (Vdd_Capi), and a reference voltage (Vref). The critical capacitor voltage is connected to the Vin_P input shown in Figure 6A or 6B. Vref can be set using a reference circuit element 870 coupled to a reference voltage level (for example, reference voltage level 605 in Figure 6A or reference voltage level 660 in Figure 6B). Examples of reference circuit elements 870 include a bandgap voltage reference circuit, a resistive voltage divider, and a capacitive voltage divider. In the exemplary implementation of Figure 8B, the reference voltage Vref is set using a resistive potentiometer 875 as the reference circuit element.

[0081] The transient waveforms of different signals are similar to those shown in Figure 5B. Specifically, referring to Figure 8C, in the time domain, the S1 and S2 clocks are shown independently, and the S3 clock is shown as the output (Vout) and Vdd_Capi waveforms of the variation-tolerant inverting comparator (for one of the PVT corners for partial discharge and for full discharge). Helpfully, during the S3 conduction phase, the Vdd_Capi value of the variation-tolerant inverting comparator for the partial discharge scheme does not drop below 671.826 mV (where Vdd_Supply = 1.21 V and Vref = 980.349 mV). It should be understood that this is one example of circuit operation, and specific values ​​can vary depending on the technology, PVT corner, and specifications.

[0082] Unlike the implementation of a biased inverting comparator, Vref (which indirectly sets the Vtrip of the input stage inverter) can be dynamically set during circuit operation. In the illustrated example of a biased inverting comparator, Vtrip is set by design and cannot be changed to the desired value later during operation. In contrast, the PVT variation of Vtrip (set by Vref) used in a variation-tolerant inverting comparator is much smaller than that of a biased inverting comparator.

[0083] The specific implementation for the inverting stage can depend on the technology used, specifications, process-voltage-temperature corners, and available design time. Furthermore, power saving can be further improved when there are more lenient specifications regarding operating frequency (e.g., lower frequencies result in greater power saving), operating temperature (e.g., a smaller operating temperature range results in greater power saving), and safety requirements (e.g., a more lenient safety requirement results in greater power saving). Fabrication technology also has an impact on circuit performance. For example, using a threshold voltage control of a MOSFET in SOI technology with back-gate control can improve performance compared to an illustrative analog. It should be further understood that although the specific examples presented herein demonstrate CMOS technology implementations, other technologies and topologies can still be used.

[0084] Although the subject matter has been described using terminology specific to structured features and / or actions, it should be understood that the subject matter as defined in the appended claims is not necessarily limited to the aforementioned specific features or actions. Rather, the aforementioned specific features and actions are disclosed as examples of implementing the claims, and other equivalent features and actions are intended to be within the scope of the claims.

[0085] 100, 500, 800: Power distribution circuit 110: Charge storage device 120, 160, 170, 180, 540, 550, 560, 840, 850, 860: Switch 130, 530, 830: Comparators 140: Switching Capacitor Circuit 150, 510, 810: Critical capacitors 200: Comparator Circuit 210,360: Inverting phase 220: Buffer level 300, 350: Biased Inverting Comparator 310, 362: CMOS inverters 320, 330, 340, 370, 380, 390, 615, 620, 625: Buffer 364: Bypass Switch 392:PMG 394:NMG 520, 820: Branch switch 600, 650: Mutation-tolerant inverting comparators 605, 660: Reference voltage level 610, 670: Input level 630: PMOS power gated MOSFET 635: NMOS power gated MOSFET 875: Resistive potentiometer

Claims

1. A comparator circuit comprising: an inverting stage having a trip voltage (Vtrip) that is different from half (VDD / 2) of a supply voltage, wherein, The break-out voltage value represents a value that changes the output state of the inverting stage when both the rising and falling input voltages input to the inverting stage are crossed; and a buffer stage coupled to one output of the inverting stage, wherein the inverting stage includes a single reference voltage stage and an input stage, wherein the single reference voltage stage includes a first inverter coupled to receive a reference voltage and output a bias voltage, and wherein the input stage includes a second inverter matched to the first inverter, the second inverter being coupled to receive an input voltage, the input stage being coupled to the reference voltage stage such that the bias voltage sets the break-out voltage value of the input stage to be different from VDD / 2.

2. The comparator circuit of claim 1 further comprises: a first power gated transistor coupled between a first supply rail and the inverting stage; and a second power gated transistor coupled between a second supply rail and the inverting stage.

3. The comparator circuit of claim 1, wherein the single reference voltage level further includes an output from the first inverter for controlling a first negative feedback loop of a pull-up network; and the output from the first inverter for controlling a second negative feedback loop of a pull-down network.

4. The comparator circuit of claim 3, wherein the first negative feedback loop includes a PMOS transistor of the first inverter, a pull-up compensation transistor, and an output node of the first inverter; and wherein the second negative feedback loop includes an NMOS transistor of the first inverter, a pull-down compensation transistor, and the output node of the first inverter.

5. The comparator circuit of claim 4, further comprising: a first power gated transistor coupled between a first supply rail and the pull-up compensation transistor; and a second power gated transistor coupled between a second supply rail and the pull-down compensation transistor.

6. The comparator circuit of claim 4, wherein the input stage further includes a second pull-up compensation transistor coupled to receive the bias voltage from the single reference voltage level; and a second pull-down compensation transistor coupled to receive the bias voltage from the single reference voltage level.

7. The comparator circuit of claim 4, wherein the input stage shares the pull-up compensation transistor and the pull-down compensation transistor with the single reference voltage stage.

8. The comparator circuit of claim 1, wherein the buffer stage comprises an odd number of buffers.

9. A power distribution circuit comprising: a charge storage device; and a comparator circuit coupled to the charge storage device to receive a voltage value from the charge storage device, wherein, The comparator circuit includes: an inverting stage having a trip voltage (Vtrip) different from half a supply voltage (VDD / 2); a buffer stage coupled to an output of the inverting stage; wherein the trip voltage represents a value that changes the output state of the inverting stage when both a rising input voltage and a falling input voltage are passed; wherein the inverting stage includes a single reference voltage stage and an input stage; wherein the single reference voltage stage includes a first inverter coupled to receive a reference voltage and output a bias voltage; and wherein the input stage includes a second inverter matched to the first inverter, the second inverter being coupled to receive an input voltage; the input stage is coupled to the reference voltage stage such that the bias voltage sets the trip voltage of the input stage to be different from VDD / 2; and a shunt switch coupled to receive an output of the comparator circuit.

10. The power distribution circuit of claim 9, wherein the single reference voltage level further includes an output from the first inverter for controlling a first negative feedback loop of a pull-up network; and the output from the first inverter for controlling a second negative feedback loop of a pull-down network.

11. The power distribution circuit of claim 9 further includes a bandgap voltage reference circuit, a resistive voltage divider, or a capacitive voltage divider coupled to the reference voltage level.

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