Dielectric sputter deposition target, process chamber including such target, and method for performing physical vapor deposition in such process chamber

Abstract

This application provides a method and apparatus for using a plasma chamber target to reduce defects in a workpiece during dielectric sputtering. For example, the dielectric sputtering deposition target may include a dielectric compound having a predetermined average grain size ranging from about 65 μm to 500 μm, wherein the dielectric compound is at least one of magnesium oxide or aluminum oxide.

Description

[Technical Field]

[0001] The embodiments of this disclosure generally relate to substrate processing chambers used in semiconductor manufacturing systems. [Previous Technology]

[0002] Sputtering (also known as physical vapor deposition (PVD)) is a method for forming features in integrated circuits, typically performed in a processing chamber. Sputtering deposits a layer of material (such as a dielectric material) on a workpiece (such as a substrate). A source material (such as a target) is bombarded by ions that are strongly accelerated by an electric field. Ion bombardment causes the material to be ejected from the target and accumulates or deposits on the substrate (such as the workpiece). During deposition, ejected particles may also deposit on other surfaces, such as shielding or other inner surfaces of the processing chamber.

[0003] Unnecessary coatings on the shielding may cause defects in the substrate being processed or in subsequent substrate processing. For example, defects may occur when unnecessary deposits occur on the shielding and charge accumulates on the unnecessary deposits, leading to arc discharge or peeling of dielectric material collected on the shielding.

[0004] Therefore, the inventors provide embodiments of an improved target for reducing defects during dielectric sputtering. [Summary of the Invention]

[0005] This application provides a method and apparatus for using a plasma chamber target to reduce defects in a workpiece during dielectric sputtering. For example, in some embodiments, an apparatus may include a dielectric sputtering deposition target, which may contain a dielectric compound having a predetermined average grain size ranging from about 65 μm to 500 μm, wherein the dielectric compound is at least one of magnesium oxide or aluminum oxide.

[0006] In at least some embodiments, a processing chamber includes a chamber body defining an internal space; a substrate support supporting a substrate within the internal space; and a plurality of targets to be sputtered onto the substrate, the plurality of targets including at least one dielectric target and at least one metal target, wherein the dielectric target includes a dielectric compound having a predetermined average grain size ranging from about 65 μm to 500 μm.

[0007] In at least some embodiments, a method of performing physical vapor deposition in a processing chamber may include the steps of: selecting a first target in the processing chamber and depositing a dielectric compound on a workpiece via the first target, wherein the dielectric compound has a predetermined average grain size ranging from about 65 μm to 500 μm; and selecting a second target in the processing chamber and depositing a metal over the dielectric compound on the workpiece via the second target.

[0008] Other and further embodiments of this disclosure are described below.

Implementation Method

[0016] Magnetic random access memory (MRAM) requires a barrier layer to be constructed as part of the memory element. The barrier layer must have high purity and a low defect number to function correctly. Magnesium oxide (MgO) and / or aluminum oxide (Al2O3) are among the dielectric materials that can be used as the barrier layer. However, using RF power to deposit MgO on the substrate surface inherently results in poor defect performance.

[0017] This application provides embodiments of sputtering deposition targets comprising a dielectric compound having a predetermined average grain size for reducing defects in workpieces (such as substrates) during the fabrication of MRAM. As used herein, grain size is the average grain size of the compound across the target, wherein the size itself has a wide distribution range. In some embodiments, each grain is within 20% of the predetermined grain size, while in other embodiments, each grain is within 30% of the average grain size (such as the predetermined grain size). According to some embodiments, at least 80% of the grains in the target, or in other embodiments, at least 90% of the grains in the target, have a grain size within 20% or 30% of the preferred grain size. Preferred grain size ranges from about 20 µm, 40 µm, and 50 µm to 500 µm, even for pure single crystals. In another embodiment, at least 80% of the grains in the target have a grain size of at least 20 µm.

[0018] During the physical vapor deposition of a dielectric film on a substrate (e.g., a substrate) in a processing chamber, dielectric powder can also form on the shielding within the processing chamber because the shielding is closer to the target than the workpiece. Subsequently, when RF power is applied to the processing chamber, an electric arc may occur between the shielding and the substrate due to the high concentration of positive ions (e.g., sheath voltage) on the shielding. In other words, charge accumulates on the shielding because the dielectric film is aggregated on it and is non-conductive. The charge on the shielding is difficult to dissipate, resulting in an electric arc. Furthermore, after processing multiple subsequent substrates in the processing chamber, more dielectric film may accumulate on the shielding, and due to poor adhesion between the film and the shielding, the film may flake or peel off and deposit on the substrate. The inventors have discovered that modifying the target grain size and the structure of the target and shielding to reduce defects in the workpiece by preventing arc discharge and preventing the dielectric film from peeling off from the shielding.

[0019] The inventors have observed that when a target containing a dielectric compound (such as MgO, Al2O3) is used in the processing chamber, most defects on the workpiece are dielectric particle defects. For example, the inventors have observed that when a metal target (such as tantalum) is exposed in a processing chamber with a shield, the number of Ta defects is insignificant. However, when a dielectric target is exposed in the chamber, a large number of defects in the form of dielectric particles are found on the workpiece. The source of the defects can be verified by experiments (such as energy-dispersive X-ray spectroscopy (EDX)), but other methods can also be used. The shield remains consistent, thus confirming that the defects originate from the dielectric target.

[0020] In some embodiments, a multi-cathode PVD chamber (such as processing chamber 100) includes a plurality of cathodes 106 having corresponding plurality of targets (at least one dielectric target 110 and at least one metallic target 112), (such as six cathodes arranged in an alternating 3 RFx3 DC configuration) attached to a chamber body 140 (such as via a top adapter assembly 142) that defines an internal space. Other RF / DC cathode configurations, such as 1x1, 2x2, 4x4, 5x5, etc., may also be used. The numbers represent the ratio of RF-powered cathodes to DC-powered cathodes. In some embodiments, RF and DC cathodes alternate in the top adapter assembly 142. In other embodiments, RF cathodes may be adjacent to other RF cathodes and the same applies to DC cathodes. In other embodiments, the ratio of RF cathodes to DC cathodes may be non-equal ratios, such as 1×2, 2×1, 1×3, 3×1, 2×3, etc. When using multiple RF cathodes, the operating frequency can be offset to reduce any interference during the deposition process. For example, in an embodiment with three RF cathodes, the first RF cathode may operate at a frequency of 13.56 MHz, the second RF cathode at 13.66 MHz (+100 kHz), and the third RF cathode at 13.46 MHz (-100 kHz). The offset can be selected based on crosstalk prevention for a given number of cathodes.

[0021] The RF cathode is typically used in conjunction with the dielectric target 110 for depositing a dielectric film on a substrate. The DC cathode is typically used in conjunction with the metal target 112 for pasting after the dielectric film has been deposited on the substrate. Pasting reduces the chance of particle formation and defects in the deposited film. Having a processing chamber with both RF and DC cathodes allows for faster substrate production because pasting and dielectric deposition can be completed in one chamber. Furthermore, having multiple cathodes of the same type allows for better pasting and deposition rates. Better deposition rates mean that the substrate spends less time in the chamber to achieve a certain film thickness. The reduced time or residence time in the chamber results in fewer substrate defects.

[0022] In some embodiments, the metal target 112 may be formed of a metal, such as tantalum, aluminum, titanium, molybdenum, tungsten, and / or magnesium. The dielectric target 110 may be formed of a metal oxide, such as titanium oxide, magnesium titanium oxide, and / or magnesium tantalum oxide. However, other metals and / or metal oxides may be used alternatively.

[0023] The dielectric target 110 comprises a dielectric compound having a predetermined grain size, and the grains are generally uniform across the dielectric target 110 with a small size variation, such as 20-30%. The predetermined grain size varies in different embodiments. In some embodiments, the grain size is selected from the range of about 20 μm to 500 μm. In some embodiments, at least 80% of the grains in the target, or in some embodiments at least 90% of the grains in the target, have a grain size equal to the preferred grain size (such as 20 μm, 40 μm, 50 μm, and up to about 500 µm or even larger).

[0024] Figure 3 illustrates an exemplary target having a grain size of 8 µm, wherein the substrate contains 218 defects with a particle size greater than 40 nm. However, when the target grain size is increased to about 30 µm, as shown in Figure 4, the number of particles (defects) is reduced to, for example, 96. In some embodiments, the grain size is increased to about 40 µm, wherein the number of defects is estimated to be about 50-60 particles, a significant reduction from 218 defects. Other embodiments have targets with grain sizes of about 80 µm, 120 µm, 400 µm, 500 µm, or even larger. Although individual results for all grain sizes anticipated in this embodiment are not shown, Figures 3 and 4 illustrate, for example, a reduction in particle defects on the substrate obtained by reducing the target grain size of dielectric target 110. While some embodiments described herein are directed to the above-described grain sizes, other grain sizes of about or greater than 20 µm may also be used to reduce the number of defects on the substrate.

[0025] As the grain size increases from 8 µm to at least 20 µm, the number of particle defects decreases significantly because a larger grain size significantly increases the surface area to volume ratio, while smaller grains have a larger surface area to volume ratio. The increase in grain size reduces the particle boundary region, as shown in Figure 4. Due to the larger grain size and smaller grain boundary area, fewer defects are generated. In other embodiments, the finish of the dielectric target 110 is modified. For example, the target may have a sputtered surface with a surface roughness ranging from about 6 µm to a polished surface with a mirror finish (virtually no surface roughness). The inventors have found that the closer to a mirror finish, the fewer particles are detected on the workpiece. In some embodiments, the dielectric target 110 has a density of at least 99.7% pure single-crystal MgO, or in some cases, at least 99.98% pure single-crystal MgO, to reduce defects in the workpiece. As used herein, target density refers to the percentage of the target relative to the theoretically available pure single-crystal density.

[0026] The processing chamber 100 also includes a substrate support 130 to support the substrate 132. The processing chamber 100 includes an opening (not shown) (such as a slit valve) through which an end effector (not shown) extends to place the substrate 132 on a lifting pin (not shown) for lowering the substrate 132 onto the support surface 131 of the substrate support 130. In the embodiment shown in FIG1, the dielectric target 110 and the metal target 112 are arranged substantially parallel to the support surface 131. The substrate support 130 includes a bias source 136, which is coupled to a bias electrode 138 disposed in the substrate support 130 via a mating network 134. A top mating assembly 142 is coupled to the upper portion of the chamber body 140 of the processing chamber 100 and grounded. Each cathode 106 may have a DC power supply 108 or an RF power supply 102 and an associated magnetron. In the case of RF power supply 102, RF power supply 102 is coupled to cathode 106 via RF matching network 104.

[0027] Shield 121 is rotatably coupled to the top connector assembly 142 and shared by the cathode 106. In some embodiments, shield 121 includes a shield body 122 and a shield top 120. In other embodiments, shield 121 has a configuration where the shield body 122 and shield top 120 are integrated into a single unitary component. In other embodiments, there may be more than two shields 121. Depending on the number of targets to be sputtered at the same time, shield 121 may have one or more apertures to expose one or more corresponding targets. Shield 121 advantageously limits or eliminates cross-contamination between multiple targets, including dielectric target 110 and metal target 112. Shield 121 is rotatably coupled to the top connector assembly 142 via shaft 123. Shaft 123 is attached to shield 121 via coupler 119. Furthermore, since the shield 121 is rotatable, areas of the shield 121 that would normally not receive adhesive are moved, allowing these areas to now be adhesively bonded, thereby significantly reducing deposit buildup and particle formation spalling. The processing chamber 100 may also include at least one shunt disposed on the top side of the shield 121 to accommodate and shield at least one other target among the plurality of targets that are not intended to be sputtered.

[0028] Actuator 116 is coupled to shaft 123 opposite to shield 121. Actuator 116 is configured to rotate shield 121 as shown by arrow 144, and to move shield 121 vertically up and down along the central axis 146 of processing chamber 100 as shown by arrow 145. During processing, shield 121 is raised to an upward position. The raised position of shield 121 exposes the target used during processing and also shields the target not used during processing. The raised position also grounds the shield for RF processing.

[0029] In some embodiments, the processing chamber 100 further includes a processing gas supply 128 to supply processing gas to the interior space 125 of the processing chamber 100. The processing chamber 100 may also include an exhaust pump 124 fluidly coupled to the interior space 125 to exhaust processing gas from the processing chamber 100. In some embodiments, for example, after the metal target 112 has been sputtered, the processing gas supply 128 may supply oxygen to the interior space 125.

[0030] FIG2 is a diagram of the spatial configuration of the processing chamber 100 in FIG1 according to the exemplary embodiment described in this case.

[0031] According to some embodiments, the dielectric target 110 and the metal target 112 (along with any other targets) are positioned away from the edge of the shield 121, typically about 0.5 inches to 2.0 inches from the edge of the shield 121. When the targets are positioned at the edge of the shield, the film deposited there tends to be subjected to greater stress than in other areas, resulting in particle detachment and deposition on the workpiece. Because the targets are positioned towards the center of the shield 121, the stress on the film is significantly reduced due to the lower film concentration in the narrow area, thereby reducing detachment and particle defects deposited on the workpiece.

[0032] FIG5 illustrates a flowchart of a method 500 for depositing a film on a substrate according to an exemplary embodiment of the present invention.

[0033] Method 500 begins at 502 and proceeds to 504. In 504, a first target is selected in the processing chamber 100 and a dielectric compound (such as MgO, Al2O3) is deposited on a workpiece (such as a semiconductor substrate) via the first dielectric target. For example, in at least some embodiments, the dielectric compound may be a single-crystal target with a diameter from about two inches to about six inches. The predetermined grain size varies in different embodiments. For example, in some embodiments, the predetermined grain size is selected from the range of about 20 μm to 500 μm. In some embodiments, the predetermined grain size may be from about 65 μm to about 500 μm. In some embodiments, at least 80% of the grains in the target, or in some embodiments at least 90% of the grains in the target, have a grain size equal to a preferred grain size (such as 20 μm, 40 μm, 50 μm, 400 μm, 500 μm, or even larger).

[0034] Next, at 506, a second target is selected in the processing chamber 100 and a second metal is deposited over the dielectric material on the workpiece via the second target. The second target is generally a metal target and the metal may be, for example, tantalum.

[0035] Thereafter, the processing chamber 100 prepares for the next or subsequent workpiece and the method 500 ends at 508.

[0036] Although the foregoing description is directed to embodiments of this disclosure, other and further embodiments disclosed herein may be designed without departing from the basic scope of this disclosure. [Simplified Explanation of the Diagram]

[0009] The embodiments of this disclosure have been briefly summarized above and are discussed in more detail below, which can be understood by referring to the exemplary embodiments of this disclosure illustrated in the accompanying drawings. However, the accompanying drawings only illustrate typical embodiments of this disclosure, and since this disclosure allows for other equivalent embodiments, the accompanying drawings should not be considered as a limitation on the scope of this disclosure.

[0010] FIG1 illustrates a schematic diagram of a multi-cathode processing chamber according to an exemplary embodiment of the present invention;

[0011] FIG2 is a diagram illustrating the spatial configuration of the chamber in FIG1 according to an exemplary embodiment described in this case;

[0012] Figure 3 is an enlarged image of a target with a specific grain size;

[0013] Figure 4 is an enlarged image of a target with grain size according to an exemplary embodiment of the present invention; and

[0014] Figure 5 illustrates a flowchart of a method for reducing defects on a workpiece according to an exemplary embodiment of the present invention.

[0015] For ease of understanding, the same numerical designations are used to represent the same elements in the figures where possible. For clarity, the figures are not drawn to scale and may be simplified. Elements and features in one embodiment may be advantageously used in other embodiments without further description. [Biomaterial Storage]

[0038] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A dielectric sputtering deposition target, primarily composed of: a dielectric compound having a predetermined average grain size ranging from greater than 400 μm to 500 μm, wherein the dielectric compound is at least one of magnesium oxide or aluminum oxide, and wherein at least 90% of the grains in the dielectric compound have a grain size equal to the predetermined average grain size.

2. The dielectric sputtering deposition target as claimed in claim 1, wherein at least 90% of the grains of the dielectric compound have a size within 20% or 30% of the predetermined average grain size.

3. The dielectric sputtering deposition target as described in claim 1, wherein the dielectric compound is a single crystal.

4. The dielectric sputtering deposition target as claimed in claim 1, wherein the dielectric compound has a density of at least 99.7%.

5. A dielectric sputtering deposition target as described in any one of claims 1 to 4, wherein the dielectric compound has a density of at least 99.98%.

6. The dielectric sputtering deposition target as claimed in claim 1, wherein the dielectric compound has the predetermined average grain size ranging from about 450 μm to about 500 μm.

7. A processing chamber, comprising: A chamber body that defines an interior space; A substrate support that supports a substrate within an internal space; and a plurality of targets to be sputtered onto the substrate, the plurality of targets comprising at least one dielectric target and at least one metal target, wherein the dielectric target comprises a dielectric compound having a predetermined average grain size ranging from greater than 400 μm to 500 μm, wherein at least 90% of the grains in the dielectric compound have a grain size equal to the predetermined average grain size.

8. The processing chamber as described in claim 7, wherein the dielectric compound is a single crystal.

9. The processing chamber as described in claim 7, further comprising: A plurality of cathodes are coupled to the chamber body and correspond to the plurality of targets.

10. The processing chamber as claimed in claim 7, further comprising a shield coupled to the chamber body and having at least one aperture that exposes at least one of the plurality of targets to be sputtered, wherein the plurality of targets are disposed at least 0.5 inches away from an edge of the shield.

11. The processing chamber as claimed in claim 10, wherein the shield is rotatably coupled to an upper portion of the chamber body.

12. The processing chamber as claimed in claim 10, wherein the shielding further comprises: At least one shunt is disposed on a top side of the shield to accommodate and shield at least one other target among the plurality of targets which are not intended to be splashed.

13. The processing chamber as claimed in claim 10 or 12, wherein the shield is configured to rotate about a central axis of the processing chamber and move linearly along a central axis of the processing chamber.

14. The processing chamber as claimed in claim 7, wherein the dielectric compound has the predetermined average grain size ranging from about 450 μm to about 500 μm.

15. A method for performing physical vapor deposition in a processing chamber, the method comprising the steps of: selecting a first target in the processing chamber and depositing a dielectric compound on a workpiece via the first target, wherein the dielectric compound has a predetermined average grain size ranging from greater than 400 μm to 500 μm, wherein at least 90% of the grains in the dielectric compound have a grain size equal to the predetermined average grain size; and selecting a second target in the processing chamber and depositing a metal over the dielectric compound on the workpiece via the second target.

16. The method as described in claim 15, wherein the first target is a dielectric target and the second target is a metallic target.

17. The method as described in claim 15, wherein the metal is tantalum.

18. The method as described in claim 15, wherein the first target is disposed at a distance of about 0.5 inches to 2.0 inches from an edge of a shield of the processing chamber.

19. The method as described in any one of claims 15 to 18, wherein the first target has a mirror finish.

20. The method as claimed in claim 15, wherein the dielectric compound has the predetermined average grain size ranging from about 450 μm to about 500 μm.

Images