SRAM and sensing method with robust charge-transfer sense amplification

Abstract

A charge-transfer transistor is coupled between a bit line and a sensing node for a sense amplifier. During a readout operation, a charge-transfer driver drives the gate voltage of the charge-transfer transistor to control whether the transistor is turned on during a charge-transfer period. To assist the charge transfer performed by the charge-transfer transistor, first and second cross-coupled transistors are coupled between the bit line and a complementary bit line.

Description

[Technical Field]

[0001] Priority is claimed in accordance with 35 USC §119.

[0002] This patent application claims priority to non-provisional application No. 17 / 008,476, filed on August 31, 2020, entitled “SRAM WITH ROBUST CHARGE-TRANSFER SENSE AMPLIFICATION”, which has been assigned to the assignee of this application and is expressly incorporated herein by reference.

[0003] This application relates to memory, and more specifically, to low-power memory with charge transfer sensing amplification. [Previous Technology]

[0004] In conventional static random access memory (SRAM), the bit line voltage difference during a read operation is not full track, but rather equal to a small fraction of the supply voltage. For example, if the supply voltage is 1 volt, the voltage difference may be only 100 millivolts or less. In order to respond to this relatively small voltage difference and make decisions about the contents stored in the bit cell, a typical sense amplifier requires a relatively large gain and therefore does not fit the column spacing, making each sense amplifier multiplexed across a set of multiplexed columns.

[0005] Therefore, there is a need in the art for SRAM with increased density. [Summary of the Invention]

[0006] According to a first aspect of this disclosure, a memory is provided, comprising: a bit line; a complementary bit line; a sense amplifier having a first logic gate cross-coupled to a second logic gate, the first logic gate having an input connected to a sense node, and the second logic gate having an input connected to a complementary sense node; a first charge transfer transistor connected between the bit line and the sense node; a second charge transfer transistor connected between the complementary bit line and the complementary sense node; a first cross-coupled transistor having a drain connected to the bit line and a gate connected to the complementary bit line; and a second cross-coupled transistor having a drain connected to the complementary bit line and a gate connected to the bit line.

[0007] According to a second aspect of this disclosure, a method for sensing bits stored in a bit lattice is provided, comprising: pre-charging bit lines and complementary bit lines to a power supply voltage while discharging a sensing node and a complementary sensing node; coupling the bit lines and the complementary bit lines to the bit lattice to partially discharge the complementary bit lines in response to a binary value of the bit stored in the bit lattice; conducting charge via a cross-coupled transistor to substantially maintain the charge of the bit lines at the power supply voltage, the cross-coupled transistor having a gate connected to the complementary bit lines and a drain connected to the bit lines; transferring charge from the bit lines to the sensing node via a charge transfer transistor during a charge transfer period to induce a sensing node voltage difference between the sensing node and the complementary sensing node, the sensing node voltage difference being greater than the bit line voltage difference between the complementary bit lines and the bit lines; and sensing the binary value of the bit in response to the sensing node voltage difference.

[0008] According to a third aspect of this disclosure, a memory is provided, comprising: a bit line; a complementary bit line; a bit cell configured to store bits; a first cross-coupled transistor having a gate connected to the complementary bit line and a drain connected to the bit line; a sense amplifier having a sense node; a first charge transfer transistor coupled between the bit line and the sense node; and a charge transfer driver configured to charge the gate of the first charge transfer transistor to a gate voltage during a charge transfer period such that the first charge transfer transistor turns on in response to the bit being equal to a first binary value, and remains off in response to the bit being equal to the complement of the first binary value.

[0009] These and additional advantages can be better understood through the following detailed description.

Implementation Method

[0016] Memory such as SRAM is provided having multiple bit cells arranged according to rows and columns. Each column has bit line pairs consisting of true bit lines and complementary bit lines. Each row has word lines. At the intersection of each row and each column, there is a corresponding bit cell in the bit cell. Each column includes its own sense amplifier, which latches a decision into one bit cell of its bit cell during a read operation. In a read operation, the word line of the accessed row is asserted such that the sense amplifier of each column latches a decision from the bit cell shared by that column and the accessed row.

[0017] To improve density and power efficiency for each column, a sense amplifier is disclosed, comprising a true sense node coupled to a true bit line via a first charge-transfer transistor. For simplicity, the true bit line will be simply referred to as a bit line in the following discussion. Similarly, the sense amplifier comprises a complementary sense node coupled to a complementary bit line via a second charge-transfer transistor. The source of each charge-transfer transistor is connected to the corresponding bit line, and its drain is connected to the corresponding sense node. Although coupling the sense amplifier to the bit line via a column multiplexer transistor is conventional, it is noted that conventional column multiplexers are controlled as switches such that when a sense node is coupled to a bit line, it is fully turned on during readout operations.

[0018] In contrast to this conventional fully on operation, during the charge transfer period of a read operation, the charge transfer driver charges the gate of each charge transfer transistor to the gate voltage, causing the charge transfer transistor to be on only for one polarity of the binary value stored in the accessed bit cell. Each bit line is charged to a pre-charge voltage before the word line voltage is asserted during the read operation, while each charge transfer transistor remains off. Then, while the charge transfer transistors are still off, the word line voltage is asserted to couple the bit cell to the pre-charged bit line. The bit cell is then charged to one of the pre-charged bit lines to a voltage affecting the bit cell, which depends on the binary content of the bit cell.

[0019] An unexpected result is that charge transfer depends on the binary state stored in the bit lattice. If the binary state equals a first binary value, the first charge transfer transistor turns on to change the sense node voltage from its default value. The second charge transfer transistor initially does not turn on during the charge transfer period in response to the first binary value. However, if the binary state equals a second binary value (the complement of the first binary value), the first charge transfer transistor initially does not conduct charge, causing the sense node voltage to remain at its default value. Conversely, it is the second charge transfer transistor that initially turns on in response to the second binary value. Note that the capacitance of each sense node is typically smaller than the corresponding bit line capacitance. Therefore, the conduction of charge by the charge transfer transistor will rapidly charge the corresponding sense node voltage from its default state to substantially equal to the pre-charged bit line voltage. Thus, the charge transfer generated by the charge transfer transistor operates to amplify the bit line difference voltage substantially across the entire track. In conventional SRAM, the sense amplifier must be relatively sensitive to respond to the bit line voltage difference across bit line pairs. In stark contrast, this paper uses a simple inverter to sense the voltage at the sensing node, because it will swing significantly from its default voltage due to the amplification provided by the charge transfer function.

[0020] Note that the preceding discussion regarding the polarity of charge-transfer transistors is general. It can be a p-type metal-oxide-semiconductor (PMOS) charge-transfer transistor or an n-type metal-oxide-semiconductor (NMOS) charge-transfer transistor. In both cases, the source is connected to the corresponding bit line, and the drain is connected to the corresponding sensing node. However, the polarity is reversed for these PMOS and NMOS implementations. In a PMOS charge-transfer transistor implementation, the bit line pair is pre-charged to the supply voltage, while the default voltage of the sensing node pair is ground. However, in an NMOS charge-transfer transistor implementation, the bit line pair is pre-charged via ground, and the default voltage of the sensing node pair will be equal to the supply voltage. The following discussion will focus on the PMOS charge-transfer implementation, followed by a discussion of the NMOS charge-transfer implementation.

[0021] In a memory with PMOS charge-transfer transistors, the bit line pairs are pre-charged to the supply voltage VDD before the word line is triggered. When the sense node pair is isolated from the pre-charged bit line pair by a pair of PMOS charge-transfer transistors, the sense node pair is discharged to ground in the default (pre-charged) state. When the word line is asserted, the byte cell can then partially discharge one bit line of the bit line pair in response to the binary value stored in the byte cell.

[0022] An example charge-transfer SRAM 100 is shown in Figure 1. A pair of bit lines, bit line bl and complementary bit line blb, cross the first column. Bit cell 105 is located at the intersection of the first column and word line wl. Bit cell 105 includes a pair of cross-coupled inverters. The output node of the first inverter in the inverters is the true (Q) output node of bit cell 105. This output node is coupled to bit line bl via NMOS access transistor M4. Similarly, the output node of the remaining second inverter in the inverters is the complementary (QB) output node of bit cell 105, which is coupled to complementary bit line blb via NMOS access transistor M3. Word line wl is coupled to the gates of access transistors M3 and M4, such that the Q and QB nodes drive their respective bit lines during word line assertion periods.

[0023] SRAM 100 includes a second column, which has bit cells at its intersection with word line wl. Since the second column is a repetition of the structure in the first column, details for the second column are not shown in Figure 1 for clarity. The two columns are multiplexed via column multiplexer 125. If a read operation (whether in random or burst mode) is directed to bit cell 105, column multiplexer 125 selects the sense amplifier output from sense amplifier 110 for the first column. For example, column multiplexer 125 may include a tri-state buffer 130 for the first column and a tri-state buffer 135 for the second column. The tri-state buffers for unselected columns are tri-stateted to form a selection in column multiplexer 125. The output of column multiplexer 125 is latched in data output latch 140.

[0024] Before word line assertion during a read operation, bit line precharge circuit 150 precharges bit lines bl and blb to the supply voltage. This precharging of the bit lines is conventional, and therefore details of bit line precharge circuit 150 are not shown in FIG1. ​​The timing of various actions, such as bit line precharging during a read operation and pulse width for word line assertion, is controlled by self-timed clock circuit 155 triggered by memory clock signal 102. The timing of these actions during a read operation is conventional. Before word line assertion, bit line precharge circuit 150 precharges bit lines bl and blb to the supply voltage. After bit line precharging, bit line precharge circuit 150 floats the bit lines. Bit line bl is coupled to the corresponding sensing node sl of sensing amplifier 110 via PMOS charge transfer transistor P1. Similarly, complementary bit line blb is coupled to the corresponding complementary sensing node slb via PMOS charge transfer transistor P2. Prior to word line assertion, a charge transfer driver, such as a dummy bit line (bl), charges the charge transfer read multiplexer (rm) signal driving the gate of the charge transfer transistor to the supply voltage to prevent any charge transfer to the sensing node. Simultaneously or approximately simultaneously, a self-timed clock circuit 155 charges the sensing node pre-charge signal (cts_pre_n) to the supply voltage. The charged cts_pre_n signal drives the gates of NMOS transistors M1 and M2. The sources of transistors M1 and M2 are connected to ground, while their drains are connected to complementary sensing nodes slb and sl, respectively. Therefore, an assertion of the cts_pre_n signal will discharge both the sensing node sl and the complementary sensing node slb for the first column, as both transistors M1 and M2 are turned on to couple their respective bit lines to ground. As previously described, the second column has the same structure as shown for the first column.

[0025] During word line assertion in a read operation, access transistors M4 and M3 are turned on by assertion of the word line voltage, causing one of the bit lines bl or blb to slightly discharge from its pre-charge state, depending on the binary content stored in bit cell 105. This slight bit line discharge is amplified by a charge transfer period during which charge transfer transistors P1 and P2 are turned on as follows: The charge transfer period is triggered by the discharge of the charge transfer rm signal. The discharge of the charge transfer rm signal can begin while the word line voltage is still asserted. The discharge of the charge transfer rm signal can end after the word line voltage has been discharged. The discharge of the charge transfer rm signal has a certain slope relative to it. One way to discharge the charge transfer rm signal relatively slowly is to use a small inverter acting as a charge transfer driver to form the signal. Due to its relatively small size, the inverter will cause the gate voltage of the charge transfer transistor to drop relatively slowly during the charge transfer period. As an alternative, a dummy bit line can be used to act as a charge transfer driver to form the charge transfer rm signal. As is known in SRAM technology, dummy bit lines are used for modeling when the bit line voltage has been sufficiently generated to warrant the start of the sensing enable period. Since the dummy bit lines model the capacitance of the bit lines, they discharge from the precharge state to the threshold voltage at approximately the same rate as the bit lines discharge from the supply voltage to the bit line voltage difference.

[0026] Due to this sub-instantaneous discharge of the charge transfer rm signal, the charge transfer rm signal will discharge such that the source-to-gate voltage of the charge transfer transistor connected to the fully charged bit line will meet its threshold voltage, but will not meet the threshold voltage of the charge transfer transistor connected to the partially discharged bit line. Therefore, the charge transfer transistor for the fully charged bit line will conduct charge to its sensing node before another charge transfer transistor conducts charge from the partially discharged bit line. For example, suppose bit line bl is a fully charged bit line, such that charge transfer transistor P1 begins to conduct current I before charge transfer transistor P2 turns on. Since the capacitance Cs of sensing node sl is relatively small compared to the bit line capacitance Cbl, the current I will charge sensing node s1 from ground toward the power supply voltage relatively quickly. Then, the remaining complementary sensing node slb will remain discharged during the initial portion of the sensing transfer period. Therefore, compared to the bit line voltage difference across bit pairs, the charge transfer process amplifies the sensing node voltage difference between sensing node sl and complementary sensing node slb, resulting in a sensing node voltage difference across almost the entire track.

[0027] The sense amplifier 110 includes a pair of cross-coupled logic gates, such as through a NAND gate 115 cross-coupled with a NAND gate 120. A sense node sl is connected to the input of the NAND gate 115. Similarly, a complementary sense node slb is connected to the input of the NAND gate 120. Pre-charging the sense node to zero volts causes both outputs of the NAND gates 115 and 120 to be asserted as high as the supply voltage. The output of the NAND gate 120 also forms an output terminal for a first column. A corresponding NAND gate in a second column (not shown) forms an output terminal for a second column. The capacitance of the sense node, conceptually represented by capacitor Cs, is relatively small compared to the bit-line capacitance conceptually represented by capacitor Cbl. Therefore, the brief amount of time by which charge-transfer transistor P1 begins to conduct before charge-transfer transistor P2 conducts results in a significant increase in the voltage of sense node sl (compared to sense node slb). This increase in voltage exceeds the threshold voltage for the NAND gate 115, causing its output to discharge to zero. The zero output of NAND gate 115 enhances the binary high output of NAND gate 120, causing the binary one value stored in bit cell 105 to be latched in sense amplifier 110.

[0028] Although bitline capacitance is typically larger than sense node capacitance, it is important to note that bitline capacitance decreases as the number of word lines used for each column decreases. However, charge transfer amplification during the charge transfer period is proportional to the ratio of bitline capacitance to sense node capacitance. As bitline capacitance decreases, charge transfer amplification decreases accordingly. Therefore, the decrease in bitline capacitance can reduce the charging of the sense node voltage during the charge transfer period, causing the sense node voltage to fail to meet the threshold voltage in sense amplifier 110. The sense amplifier 110 may then incorrectly sense the binary value of bit cell 105. Furthermore, leakage in bit cell 105 can reduce the bitline voltage difference across bitline pairs during the word line assertion period, especially as the word line assertion period increases. As discussed earlier, the bitline voltage difference can be relatively small (e.g., 100 mV), making leakage in bit cell 105 problematic. Therefore, reduced bitline capacitance and / or bit cell leakage can cause errors during read operations of sense amplifier 110. To provide more robust charge transfer, PMOS transistors P6 and P7 are cross-coupled across bit lines. The cross-coupled transistors P6 and P7 connect their sources to the power node used for the supply voltage. The drain of transistor P6 is connected to bit line b1, while its gate is connected to the complementary bit line blb. Similarly, the drain of transistor P7 is connected to the complementary bit line blb, while its gate is connected to bit line b1.

[0029] Due to the cross-coupling of transistors P6 and P7, partial discharge of one bit line during a read operation will support charging of the remaining bit lines. For example, assuming cell 105 stores binary 1, the complementary bit line blb will partially discharge during the word line assertion portion of the read operation. Ideally, bit line blb will remain charged to the supply voltage during the word line assertion period. However, even in the event of leakage causing the voltage of bit line blb to decrease below the supply voltage, this decrease will typically be less than the partial discharge of the complementary bit line blb. The reduced gate voltage of transistor P6 compared to transistor P7 allows transistor P6 to conduct more charge than transistor P7, thus enabling transistor P6 to maintain bit line blb substantially charged to the supply voltage during the word line assertion period.

[0030] The cross-coupling of transistors P6 and P7 also serves to support the non-discharge bit line during the charge transfer period. For example, suppose bit cell 105 is storing binary zero, making it the complementary bit line blb, which is the non-discharge bit line. As the charge transfer rm signal discharges to ground, the source-to-gate voltage of the charge transfer transistor P2 will meet its threshold voltage, while the charge transfer transistor P1 remains off. Therefore, the charge transfer transistor P2 will begin to conduct charge during the charge transfer period. If the bit line capacitance is not significantly greater than the sensing node capacitance, the charge transfer from the complementary bit line voltage blb may not be sufficient to charge the complementary sensing node voltage above the threshold voltage of the sensing amplifier 110 to sense the binary zero value of bit cell 105. However, even during the charge transfer period, due to the charge transfer, the complementary bit line voltage will discharge from the supply voltage, and the complementary bit line voltage will still tend to discharge a portion above the bit line blb voltage. Therefore, compared to transistor P6, transistor P7 will be turned on to a greater extent to essentially keep the complementary bit line blb charged to the supply voltage, even though the ratio of bit line capacitance to sensing node capacitance is reduced.

[0031] To assist latching within the sense amplifier 110, the sense node precharge signal cts_pre_n drives the gate of PMOS transistor P5, whose source is connected to the power node for the power supply voltage. The drain of transistor P5 is connected to the sources of a pair of PMOS transistors P4 and P3. The drain of transistor P4 is connected to sense node sl, while the drain of transistor P3 is connected to complementary sense node slb. The output of NAND gate 115 drives the gate of transistor P4. Similarly, the output of NAND gate 120 drives the gate of transistor P3. Assuming that the voltage of sense node sl is charged above the threshold voltage of NAND gate 115 during a read operation, the output of NAND gate 115 is low. This low-potential output from NAND gate 115 turns on transistor P4 to reinforce the charging state of sense node sl, which in turn reinforces the zero output of NAND gate 115. Conversely, assuming that after the sensing enable period, the output of NAND gate 120 is low because the complementary sensing node slb is charged above the threshold voltage of NAND gate 120, the transistor P3 is then turned on. The turn-on of transistor P3 reinforces the charging state of the complementary sensing node slb, which in turn reinforces the zero output of NAND gate 120. In this way, the latching of the sensed bit in the sensing amplifier 110 is strengthened or reinforced.

[0032] The cross-coupling of transistors P6 and P7 can adequately support the charging of non-discharge bit lines, allowing transistors P3, P4, and P5 to be eliminated, as shown for the charge transfer SRAM 200 of FIG. 2. SRAM 200 is arranged as discussed with respect to SRAM 100, except that transistors P3, P4, and P5 are omitted. Furthermore, the arrangement of bit lines bl and blb in FIG. 2 is reversed compared to FIG. 1. Since the cross-coupled transistors P6 and P7 support the charge of non-discharge bit lines in the bit line pair, the sense amplifier 110 is used to latch the sensed binary value from bit cell 105 without supporting transistors P3, P4, and P5. In SRAM 200, the charge transfer driver is formed by inverter 210. Output buffer 225 buffers the output from sense amplifier 110. Output buffer 225 includes an inverter 205 that inverts the output from NAND gate 115. The output of inverter 205 drives the gate of NMOS transistor M5, which has a source connected to ground and a drain forming an output node for the data output signal Dout. Therefore, in response to the output of NAND gate 115 being charged to the power supply voltage, the data output signal is discharged by transistor M5. Output buffer 225 also includes a PMOS transistor P12 having a source connected to the power supply node and a drain connected to the drain of transistor M5. Therefore, in response to the output of NAND gate 120 being discharged to ground, the data output signal is charged to the power supply voltage.

[0033] As discussed above, in an alternative implementation, the charge transfer transistor can be an NMOS transistor. An exemplary NMOS-based charge transfer SRAM 300 is shown in Figure 3. The PMOS charge transfer transistors P1 and P2 are replaced with NMOS charge transfer transistors M7 and M6, respectively. In this NMOS charge transfer implementation, the bit lines are pre-charged by being discharged to ground. Conversely, the sensing nodes are pre-charged by being charged to the supply voltage. The bit grid 305 is coupled to the bit line b1 via PMOS access transistor P11 and to the complementary bit line blb via PMOS access transistor P10. Thus, the word line W1 is asserted by being discharged during the word line assertion period. The default state of the word line W1 is then charged to the supply voltage to keep access transistors P10 and P11 off outside the word line assertion period. The pre-charge circuit 350 is used to discharge the bit lines before the word line assertion period.

[0034] A self-timed clock circuit 345 controls a charge transfer precharge signal cts_pre to control the precharge of the sensing node. Before the word line assertion period, the self-timed clock circuit 345 discharges the cts_pre signal to turn on a pair of PMOS transistors P8 and P9, both of which have sources connected to the power supply node. The drain of transistor P9 is connected to the complementary sensing node slb. Similarly, the drain of transistor P8 is connected to the sensing node sl. The turn-on of transistors P8 and P9 thus precharges the sensing node to the power supply voltage. Given this precharge state of the sensing node, the sensing amplifier 310 can be formed by a pair of cross-coupled NOR gates 315 and 320. NOR gate 315 has an input connected to the complementary sensing node slb and an output connected to the input of NOR gate 320. Similarly, NOR gate 320 has an input connected to the sensing node sl and an output connected to the input of NOR gate 315. Similar to the discussion regarding SRAM 100, the NOR gate 320 has an output drive data output latch (not shown).

[0035] During the word line assertion period, one bit line in the bit line is partially charged from ground toward the power supply voltage according to the binary value stored in bit cell 305. For example, if bit cell 305 is storing binary zero, then during the word line assertion period, it is the complementary bit line blb that is partially charged. Conversely, if bit cell 305 is storing binary one, then during the word line assertion period, it is the bit line b1 that is partially charged. It can be seen that, according to the binary value stored in bit cell 305, one bit line in the bit line will be partially charged, while another bit line in the bit line will be discharged. During the charge transfer period, a low-state active charge transfer read multiplexer (rm_n) signal, such as that driven by inverter 325, controls the charge transfer rm_n signal to charge to the power supply voltage. This charging has a certain slope, such as that caused by the relatively small size of inverter 325. The drains of charge transfer transistors M6 and M7 are charged to the supply voltage from the pre-charge of the sensing node. Therefore, a charge transfer transistor whose source is connected to a fully discharged bit line will tend to turn on faster than a charge transfer transistor whose source is connected to a bit line that is partially charged.

[0036] If the bit line capacitance is significantly greater than the sensing node capacitance, the sensing node connected to the charge transfer transistor (the charge transfer transistor is further connected to the fully discharged bit line in the bit line) will essentially discharge to ground due to the charge amplification from the charge transfer. However, as the bit line capacitance decreases, this charge amplification may be insufficient for the sensing amplifier 310 to successfully sense the binary value of the bit cell 305. To enhance the charge amplification, a pair of NMOS transistors M8 and M9 are cross-coupled between bit lines bl and blb. The sources of transistors M8 and M9 are both connected to ground. The drain of transistor M8 is connected to the complementary bit line blb, while its gate is connected to bit line bl. Similarly, the drain of transistor M9 is connected to bit line bl, while its gate is connected to the complementary bit line blb. Depending on which bit line in the bit line is partially charged, the cross-coupled transistors for the remaining discharged bit lines in the bit line will tend to turn on during the word line assertion period to keep the discharged bit lines in the bit line fully discharged. In this way, any conduction in bit grid 305 that tends to charge the discharged bit lines in the bit line is resolved. Furthermore, similar to what was discussed for transistors P6 and P7, the cross-coupling of transistors M8 and M9 assists in charge transfer amplification.

[0037] A method for sensing bits using charge-transfer SRAM will now be discussed with reference to the flowchart of FIG4. The method includes the following action 400: pre-charging bit lines and complementary bit lines to the power supply voltage while discharging sensing nodes and complementary sensing nodes. Pre-charging bit lines b1 and blb via pre-charging circuit 150 and discharging sensing nodes via transistors M1 and M2 are examples of action 400. The method also includes the following action 405: coupling bit lines and complementary bit lines to a bit cell to partially discharge the complementary bit lines in response to the binary value of the bit stored in the bit cell. Discharging the complementary bit line blb in SRAM 100 or 200 during a word line assertion period is an example of action 405. The method also includes the following action 410: conducting charge via a cross-coupled transistor to substantially maintain the charge of the bit lines at the power supply voltage, the cross-coupled transistor having a gate connected to the complementary bit lines and a drain connected to the bit lines. An example of action 410 is maintaining the charge on bit line bl in SRAM 100 or 200 by conducting through cross-coupled transistor P6. Furthermore, the method includes action 415, which occurs during a charge transfer period and includes transferring charge from the bit line to a sensing node via a charge transfer transistor to induce a sensing node voltage difference between the sensing node and a complementary sensing node, the sensing node voltage difference being greater than the bit line voltage difference between the complementary bit line and the bit line. An example of action 415 is conducting charge through charge transfer transistor P1 to charge sensing node sl. Finally, the method includes action 420, which senses the binary value of a bit in response to a sensing node voltage difference. An example of action 420 is latching the sensed bit into sensing amplifier 110.

[0038] Memory with improved charge transfer as discussed herein can be incorporated into a variety of electronic systems. For example, as shown in Figure 5, according to this disclosure, a cellular phone 500, a laptop computer 505, and a tablet computer 510 can all include memory with improved charge transfer capabilities. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers can also be configured with charge transfer memory constructed according to this disclosure.

[0039] As those skilled in the art will understand to date, and depending on the particular application at hand, numerous modifications, substitutions, and variations can be made to the materials, apparatus, configuration, and methods of use of the devices disclosed herein without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments shown and described herein (as they are merely examples thereof), but should be fully commensurate with the scope of the appended claims and their functional equivalents. [Simplified Explanation of the Diagram]

[0010] Figure 1 illustrates a charge transfer SRAM comprising a pair of PMOS cross-coupled transistors according to one aspect of the present disclosure.

[0011] Figure 2 illustrates a charge transfer SRAM comprising a pair of PMOS cross-coupled transistors according to one aspect of the present disclosure.

[0012] Figure 3 illustrates a charge transfer SRAM comprising a pair of NMOS cross-coupled transistors according to one aspect of the present disclosure.

[0013] Figure 4 is a flowchart of bit sensing in a charge transfer memory according to one aspect of the present disclosure.

[0014] Figure 5 illustrates some example electronic systems according to one aspect of this disclosure, each electronic system including a charge transfer memory.

[0015] Embodiments of this disclosure and their advantages can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements shown in one or more of the figures.

Claims

1. A memory, comprising: Bit line; Complementary bit lines; A sensing amplifier having a first logic gate cross-coupled to a second logic gate, the first logic gate having an input connected to a sensing node, and the second logic gate having an input connected to a complementary sensing node; a first charge-transfer transistor connected between the bit line and the sensing node; a second charge-transfer transistor connected between the complementary bit line and the complementary sensing node; and a first cross-coupled transistor having a drain connected to the bit line and a gate connected to the complementary bit line. And a second cross-coupled transistor having a drain connected to the complementary bit line and a gate connected to the bit line, wherein the capacitance of the sensing node is relatively small compared to the bit line capacitance.

2. The memory according to claim 1 further includes: A first pre-charged transistor is configured to pre-charge the sensing node; And a second pre-charged crystal, which is configured to pre-charge the complementary sensing node.

3. The memory according to claim 1, wherein, The first cross-coupled transistor and the second cross-coupled transistor each include a PMOS cross-coupled transistor having a source connected to a power node.

4. The memory according to claim 3 further includes: A pre-charge circuit is configured to pre-charge the bit lines and the complementary bit lines to the power supply voltage.

5. The memory according to claim 3, wherein, The first charge transfer transistor and the second charge transfer transistor each comprise a PMOS charge transfer transistor.

6. The memory according to claim 5 further includes: A dummy bit line is connected to the gate of the first charge transfer transistor and to the gate of the second charge transfer transistor.

7. The memory according to claim 5, further comprising: A bit cell includes a first access transistor having a drain connected to the bit line, and a second access transistor having a drain connected to the complementary bit line. And word lines, which are connected to the gates of the first access transistor and the second access transistor.

8. The memory according to claim 7, wherein, The first access transistor and the second access transistor each include an NMOS access transistor.

9. The memory according to claim 5, wherein, The first logic gate and the second logic gate each include a NAND gate.

10. The memory according to claim 1, wherein, The first cross-coupled transistor and the second cross-coupled transistor each include an NMOS cross-coupled transistor having a source terminal connected to ground.

11. The memory according to claim 10, further comprising: A pre-charge circuit is configured to discharge the bit line and the complementary bit line to ground.

12. The memory according to claim 10, wherein, The first charge transfer transistor and the second charge transfer transistor each comprise an NMOS charge transfer transistor.

13. The memory according to claim 12 further includes: An inverter is connected to the gate of the first charge transfer transistor and to the gate of the second charge transfer transistor.

14. The memory according to claim 12 further includes: A bit cell includes a first access transistor having a drain connected to the bit line, and a second access transistor having a drain connected to the complementary bit line. And word lines, which are connected to the gates of the first access transistor and the second access transistor.

15. The memory according to claim 14, wherein, The first access transistor and the second access transistor each include a PMOS access transistor.

16. The memory according to claim 12, wherein, The first logic gate and the second logic gate each include a NOR gate.

17. A method for sensing bits stored in a bit lattice, comprising: Precharge the bit lines and complementary bit lines to the power supply voltage, while discharging the sensing nodes and complementary sensing nodes. The bit lines and the complementary bit lines are coupled to the bit grid to partially discharge the complementary bit lines in response to the binary value of the bit stored in the bit grid; charge is conducted via a cross-coupled transistor to substantially maintain the charge of the bit lines at the power supply voltage, the cross-coupled transistor having a gate connected to the complementary bit lines and a drain connected to the bit lines; during a charge transfer period, charge is transferred from the bit lines to the sensing node via a charge transfer transistor to induce a sensing node voltage difference between the sensing node and the complementary sensing node, the sensing node voltage difference being greater than the bit line voltage difference between the complementary bit lines and the bit lines; And sensing the binary value of the bit in response to the voltage difference of the sensing node, wherein the capacitance of the sensing node is relatively small compared to the bit line capacitance.

18. The method according to claim 17 further includes: The sensing node and the complementary sensing node are discharged during the pre-charging of the bit line and the complementary bit line.

19. The method according to claim 17, wherein, Sensing the binary value of the bit includes using a cross-coupled pair of logic gates to sense the binary value of the bit.

20. The method according to claim 19, wherein, Sensing the binary value of the bit includes using a cross-coupled pair of NAND gates to sense the binary value of the bit.

21. The method according to claim 17 further includes: The gate of the charge-transfer transistor is discharged during the charge transfer period.

22. A memory, comprising: Bit line; Complementary bit lines; A bit cell, which is configured to store bits; A first cross-coupled transistor having a gate connected to the complementary bit line and a drain connected to the bit line; a sense amplifier having a sense node; a first charge transfer transistor coupled between the bit line and the sense node; and a charge transfer driver connected to the first charge transfer transistor and configured to charge the gate of the first charge transfer transistor to a gate voltage during a charge transfer period, such that the first charge transfer transistor turns on in response to the bit being equal to a first binary value, and remains off in response to the bit being equal to the complement of the first binary value, wherein the capacitance of the sense node is relatively small compared to the bit line capacitance.

23. The memory according to claim 22 further includes: The second cross-coupled transistor has a gate connected to the bit line and a drain connected to the complementary bit line.

24. The memory according to claim 22, wherein, The charge transfer driver includes an inverter.

25. The memory according to claim 22, wherein, The charge transfer driver includes dummy bit lines.

26. The memory according to claim 23, wherein, The first cross-coupled transistor and the second cross-coupled transistor each include a PMOS cross-coupled transistor.

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