Semiconductor device and method of fabricating the same, and method of fabricating thin film transistor

Abstract

This disclosure includes a semiconductor device comprising: a substrate having a device surface; and a patterned metal electrode disposed on the substrate. The patterned metal electrode is formed of one or more of copper, gold, and silver. The patterned metal electrode includes a lower surface adjacent to the substrate, an upper surface adjacent to the substrate, and a sidewall extending between the lower surface and the upper surface, with a sidewall barrier layer extending on the sidewall. The sidewall barrier layer may be a manganese oxide barrier layer.

Description

[Technical Field]

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 114,569, filed on November 17, 2020, which is incorporated herein by reference in its entirety.

[0003] This specification relates generally to semiconductor electronic devices, and more specifically to semiconductor electronic components including metal electrodes having sidewall barrier layers disposed thereon, and methods of manufacturing thereof. [Previous Technology]

[0004] Copper electrodes offer several advantages over other types of electrodes due to their relatively low resistivity. However, the presence of metals such as copper in semiconductor devices can lead to various complications in the manufacturing process. For example, copper can diffuse into adjacent semiconductor layers, thereby increasing leakage current through them. Furthermore, if copper is exposed to oxygen, it can be oxidized and adversely affect the conductivity of the electrode. Such oxidation problems are particularly severe when copper is exposed to oxygen at high temperatures, such as during the formation of additional semiconductor device components (e.g., passivation layers). [Summary of the Invention]

[0005] The first aspect of this disclosure includes a semiconductor device, the semiconductor device comprising: a substrate; the substrate including a device surface; and a patterned metal electrode disposed on the substrate. The patterned metal electrode is formed of one or more of copper, gold, and silver. The patterned metal electrode includes a lower surface adjacent to the substrate, an upper surface adjacent to the substrate, and a sidewall extending between the lower surface and the upper surface, the sidewall barrier layer extending on the sidewall.

[0006] The second state sample disclosed herein includes a semiconductor device according to any of the first state samples, wherein the sidewall barrier layer includes a magnesium oxide barrier layer.

[0007] The third state sample disclosed herein includes a semiconductor device according to any one of the first to second state samples, wherein the sidewall barrier layer has a thickness of greater than or equal to 1 nm and less than or equal to 5 nm.

[0008] The fourth state sample disclosed herein includes a semiconductor device according to any one of the first to third state samples, further comprising: a first barrier layer that contacts the lower surface and is disposed between the patterned metal electrode and the substrate, wherein neither the first barrier layer nor the second barrier layer directly contacts the sidewall.

[0009] The fifth state sample disclosed herein includes a semiconductor device according to any one of the first to fourth state samples, wherein the sidewall layer is disposed directly on the sidewall between the first barrier layer and the second barrier layer.

[0010] The sixth state sample disclosed herein includes a semiconductor device according to any one of the first to fifth state samples, further including an oxide passivation layer disposed on the patterned metal electrode, the oxide passivation layer directly contacting at least a portion of the sidewall barrier layer.

[0011] The seventh state sample disclosed herein includes a semiconductor device according to any one of the first to sixth states samples, further comprising: a gate electrode disposed on the substrate; a dielectric layer disposed on the gate electrode; a semiconductor layer disposed on the dielectric layer; a source electrode disposed on a first portion of the semiconductor layer; and a drain electrode disposed on a second portion of the semiconductor layer. The source electrode and the drain electrode overlap with the gate electrode in a direction perpendicular to the surface of the device at the first gate overlap region and the second gate overlap region. The patterned metal electrode is one of the source electrode and the drain electrode, such that the sidewall barrier layer directly contacts the source electrode or the drain electrode.

[0012] The eighth state of this disclosure includes a semiconductor device according to any one of the first to seventh states, wherein the other of the source electrode and the drain electrode, which is not the patterned metal electrode, includes an additional sidewall extending near the lower surface, the upper surface and between the lower surface and the upper surface of the substrate, and the semiconductor device further includes an additional sidewall barrier layer partially disposed on the additional sidewall.

[0013] The ninth state of this disclosure includes a semiconductor device according to any one of the first to eighth state samples, wherein the lengths of the first gate overlap region and the second gate overlap region differ from each other by less than or equal to 10 nm.

[0014] The tenth state sample disclosed herein includes a semiconductor device according to any one of the first to ninth state samples, further including a passivation layer disposed on the source electrode and the drain electrode, the passivation layer containing an oxide, wherein the passivation layer directly contacts at least a portion of the sidewall and the additional sidewall.

[0015] The eleventh state of this disclosure includes a semiconductor device according to any one of the first to eleventh states, and further includes an additional metal layer disposed on the source electrode and the drain electrode.

[0016] The twelfth state of this disclosure includes a semiconductor device according to any one of the first to twenty-first states, further including a copper barrier layer partially disposed on the gate electrode and in direct contact with the gate electrode.

[0017] The thirteenth state of this disclosure includes a semiconductor element according to any one of the first to twelfth states, wherein the patterned metal electrode is a component of a thin-film transistor.

[0018] The fourteenth state of this disclosure includes a semiconductor element according to any one of the first to thirteenth states, wherein the thin-film transistor is a component of a touch panel display.

[0019] The fifteenth aspect of this disclosure includes a method for manufacturing a semiconductor electronic device, the method comprising the steps of: providing a substrate and forming a patterned electrode structure on the substrate. The patterned electrode structure includes: a first barrier layer disposed on the substrate; a metal electrode layer disposed on the first barrier layer, the metal electrode layer being formed of one or more of copper, gold, and silver; and a second barrier layer disposed on the upper surface of the metal electrode layer. The first barrier layer, the metal electrode layer, and the second barrier layer are patterned such that the sidewalls of the metal electrode layer are exposed between the first barrier layer and the second barrier layer. The method includes the steps of: heating the substrate to a deposition temperature of at least 300°C; and exposing the patterned electrode structure to a manganese precursor in a deposition chamber at the deposition temperature for a deposition cycle, wherein the pressure at the deposition temperature during the deposition cycle is at least 0.1 Torr. The deposition cycle is at least 1 second and the manganese precursor selectively migrates the sidewalls. The method also includes: after exposing the substrate to the manganese precursor, exposing the patterned electrode structure to an oxide that reacts with the manganese precursor to form a MnOx barrier layer locally disposed on the sidewall.

[0020] The sixteenth state of this disclosure includes a method according to any of the fifteenth state, wherein the manganese precursor is an amidomanganese having the structure and is supplied to the deposition chamber via a bubbler in fluid communication with the deposition chamber.

[0021] The seventeenth state of this disclosure includes a method according to any one of the fifteenth to sixteenth states, wherein the manganese precursor is an amidomanganese having the structure in which R1, R2, R3, R1'R2' and R3' are groups composed of one or more nonmetallic atoms.

[0022] The eighteenth state of this disclosure includes a method according to any one of the fifteenth to seventeenth states, wherein R1, R2, R1' and R2' are isopropyl groups and R3 and R3' are n-butyl groups.

[0023] The nineteenth state of this disclosure includes a method according to any one of the fifteenth to eighteenth states, further comprising: depositing an oxide-containing passivation layer on the patterned electrode structure, the oxide-containing passivation layer at least partially contacting the MnOx barrier layer.

[0024] The twentieth state of this disclosure includes a method according to any one of the fifteenth to nineteenth states, wherein the oxide that reacts with the manganese precursor to form the MnOx barrier layer is a component of the oxide-containing passivation layer, such that the MnOx barrier layer is formed during the deposition of the oxide-containing passivation layer.

[0025] The twenty-first state of this disclosure includes a method according to any one of the fifteenth to twentieth states, wherein the oxide-containing passivation layer is disposed in a plasma-enhanced chemical vapor deposition chamber.

[0026] The twenty-second state of this disclosure includes a method according to any one of the fifteenth to twenty-first states, wherein the patterned electrode layer structure exposed to the manganese precursor in the deposition chamber corresponds to the plasma-enhanced chemical vapor deposition chamber, such that the patterned electrode structure remains in the plasma-enhanced chemical vapor deposition chamber for both exposure to the manganese precursor and deposition of the oxide-containing passivation layer.

[0027] The twenty-third state of this disclosure includes a method according to any one of the fifteenth to twenty-second states, wherein the manganese precursor is introduced into the plasma-enhanced chemical vapor deposition chamber via a bubbler in fluid communication with the plasma-enhanced chemical vapor deposition chamber, wherein the bubbler is heated to a temperature greater than or equal to 75°C and less than or equal to 100°C before the manganese precursor is introduced into the plasma-enhanced chemical vapor deposition chamber.

[0028] The twenty-fourth state of this disclosure includes a method according to any one of the fifteenth to twenty-first states, wherein the semiconductor electronic element is a thin-film transistor element.

[0029] The twenty-fifth aspect of this disclosure includes a method for manufacturing a thin-film transistor, the method comprising the steps of: providing a substrate; depositing a gate electrode layer on a device surface of the substrate and patterning the gate electrode layer into a gate electrode; depositing a dielectric layer on the gate electrode layer; depositing a semiconductor on the dielectric layer; and forming a patterned electrode structure on the channel. The patterned electrode structure includes a first barrier layer disposed on the semiconductor layer, an electrode layer disposed on the first barrier layer, and a second barrier layer disposed on the electrode layer. The electrode layer includes a drain portion including a drain sidewall and a source portion including a source sidewall. The source sidewall and the drain sidewall are disposed on the gate electrode. The method also includes: simultaneously forming a sidewall barrier layer and an oxide-containing passivation layer extending over the source sidewall and the gate sidewall on the patterned electrode structure. The simultaneous formation of the sidewall barrier layer and the oxide-containing passivation layer includes: placing the substrate and the patterned electrode structure into a plasma-enhanced chemical vapor deposition chamber in fluid communication with a bubbler containing a manganese precursor; allowing the manganese precursor to flow into the deposition chamber for a predetermined period, while simultaneously heating the substrate and the patterned electrode to the deposition temperature; and allowing the chemical components of the oxide-containing passivation layer to flow into the deposition chamber, so that the oxide reacts with the manganese precursor to form a manganese oxide sidewall barrier layer on the source sidewall and the gate sidewall.

[0030] The twenty-sixth state of this disclosure includes the method according to the twenty-fifth state, wherein the manganese precursor is an amidomanganese having the structure and is supplied to the deposition chamber via a bubbler in fluid communication with the deposition chamber.

[0031] The twenty-seventh state of this disclosure includes a method according to any one of the twenty-fifth to twenty-sixth states, wherein the manganese precursor is an amidomanganese having the structure in which R1, R2, R3, R1'R2' and R3' are groups composed of one or more non-metallic atoms.

[0032] The twenty-eighth state of this disclosure includes a method according to any one of the twenty-fifth to twenty-seventh states, wherein R1, R2, R1' and R2' are isopropyl groups and R3 and R3' are n-butyl groups.

[0033] The twenty-ninth state of this disclosure includes a method according to any one of the twenty-fifth to twenty-eighth states, wherein the electrode layer is formed of one or more of copper, gold and silver.

[0034] The thirtieth state of this disclosure includes a method according to any one of the twenty-fifth to twenty-ninth states, wherein the electrode layer is formed of pure copper.

[0035] The thirty-first state of this disclosure includes the method according to any one of the twenty-fifth to thirtieth states, wherein the deposition temperature is greater than or equal to 300°C.

[0036] The thirty-second state of this disclosure includes the method according to any one of the twenty-fifth to thirty-first state samples, wherein the deposition temperature is greater than or equal to 350°C.

[0037] The thirty-third state of this disclosure includes a method according to any one of the twenty-fifth to thirty-second states, wherein the predetermined period is greater than or equal to 15 minutes.

[0038] The thirty-fourth state of this disclosure includes a method according to any one of the twenty-fifth to thirty-third states, wherein the oxide-containing passivation layer comprises silicon.

[0039] The thirty-fifth state of this disclosure includes a method according to any one of the twenty-fifth to thirty-fourth states, which further includes: exposing the gate electrode to a manganese precursor at a high temperature before depositing the dielectric layer on the gate electrode.

Implementation Method

[0049] Embodiments of this specification relate to a semiconductor electronic device including a patterned electrode structure with a sidewall barrier layer and a method of manufacturing the same. The patterned electrode structure may include a patterned metal electrode comprising a first surface, a second surface, and a sidewall extending between the first and second surfaces, disposed close to a substrate. In embodiments, the patterned electrode structure also includes a barrier layer disposed between the first and second surfaces to facilitate adhesion of the patterned metal electrode to the substrate and / or prevent diffusion of the patterned metal electrode into adjacent components (e.g., semiconductor layers or dielectric layers) of the semiconductor electronic device. Due to the patterning of the electrode layer forming the patterned metal electrode, the sidewall may be exposed via the barrier layer disposed on the first and second surfaces. Therefore, the semiconductor electronic device disclosed herein may include a sidewall barrier layer formed directly on the sidewall after the electrode layer is patterned. The sidewall barrier layer herein may be formed by exposing the patterned electrode structure to a manganese precursor at a suitable deposition temperature. The manganese precursor can exist as a metallic phase on the inner sidewall of the patterned metal electrode. After exposure to the manganese precursor, the patterned manganese structure can be exposed to an oxide that reacts with manganese atoms present in the patterned metal electrode to form a manganese oxide sidewall barrier layer. This sidewall barrier layer advantageously prevents oxidation of the patterned metal electrode and improves the operation of the semiconductor electronic device. Various embodiments of semiconductor electronic devices and methods including patterned electrode structures with sidewall barrier layers will be described in further detail herein with reference to the accompanying drawings.

[0050] The sidewall barrier layer described herein can be advantageously formed during semiconductor device manufacturing with minimal disruption to existing manufacturing processes. For example, in an embodiment, a semiconductor electronic device according to this specification may include an oxide-containing passivation layer disposed on a patterned electrode structure. The oxide-containing passivation layer may be disposed on the patterned electrode structure via plasma-enhanced chemical vapor deposition (PECVD), wherein the substrate is heated and exposed to a component gas of the oxide-containing passivation layer. Prior to forming the oxide-containing passivation layer, a manganese precursor for forming the sidewall barrier layer described herein may be introduced into the PECVD chamber and react with oxygen included in the component gas, resulting in the simultaneous formation of the sidewall barrier layer and the oxide-containing passivation layer. Therefore, the sidewall barrier layer described herein can be advantageously formed with minimal modifications to existing device manufacturing processes.

[0051] The sidewall barrier layer described herein advantageously improves the performance of semiconductor devices by maintaining the conductivity of patterned metal electrodes throughout the manufacturing process. For example, a semiconductor electronic device that can be manufactured by the method described herein is a thin-film transistor (TFT) device, which, in addition to other components, includes a substrate, a gate electrode disposed on the substrate, a channel semiconductor layer, a source electrode, and a drain electrode. The source electrode and drain electrode may overlap with a gate electrode in a gate overlap region defined at least partially by the source sidewall of the source electrode and the drain sidewall of the drain electrode. A sidewall barrier layer may be formed on the source sidewall and drain sidewall to prevent the sidewall barrier layer from oxidizing during the manufacture of the TFT device. This oxidation prevention can be used to maintain the variability of the size of the gate overlap region of the source electrode and drain electrode. Inconsistencies in the size of the gate overlap region caused by oxidation of the source and drain electrodes at the sidewalls can affect various operating characteristics of TFT devices (e.g., threshold voltage, scattering parameters, electron mobility, and leakage current) in unpredictable ways. Therefore, by reducing this oxidation and maintaining the variability of the gate overlap region within a predetermined threshold (e.g., less than or equal to 10 nm, less than or equal to 5 nm), the sidewall barrier layer described herein can maintain the consistency of TFT device performance. This consistency can improve the bulk operating performance of devices incorporated into TFT devices (touch panel displays, touch panels, and the like).

[0052] As used herein, the term "metal electrode" refers to a pure metal electrode layer of a semiconductor device formed by a sputtering target, which is formed of 99.99% of a particular metal (e.g., Cu). In embodiments, the metal electrode herein is formed by a sputtering target having a purity of 6N or higher.

[0053] A range herein may be expressed as from “about” a particular value and / or to “about” another particular value. When expressing this range, another embodiment includes from one particular value and / or to another particular value. Similarly, when a value is expressed as approximation by using the antecedent “about”, it will be understood that a particular value forms another embodiment. It will be further understood that both the relevance of each endpoint in the range to the other endpoint and its independence from the other endpoint are important.

[0054] The directional terms used herein—for example, up, down, right, left, front, back, top, bottom—are used only with reference to the accompanying drawings and are not intended to imply absolute orientation.

[0055] Unless otherwise expressly stated, it is by no means intended to construe any of the methods articulated herein as requiring the execution of its steps in a specific sequence, nor by requiring specific orientation of any equipment. Therefore, there is no intention to infer order or orientation in any state where the scope of the method patent application does not actually state the sequence followed by its steps, or the order or orientation of individual components is not actually stated in the scope of the patent application for any equipment, or where the scope or description of the patent application does not otherwise specifically state that the steps are limited to a specific order, or the specific order or orientation of the components of the equipment is not stated. This applies to any possible non-explicit basis of interpretation comprising: logical issues concerning step configuration, operational flow, order of components or orientation of components, simple implications derived from syntactic organization or punctuation and; the number or type of embodiments described in the instructions.

[0056] As used herein, the singular forms "a / species (a / an)", and "the / these (the)" contain plural indicators unless the context makes clear otherwise. Unless otherwise explicitly stated by the context, thus, for example, the reference to "a (a)" component comprises having two or more such components.

[0057] 1A, 1B and 1C schematically depict semiconductor electronic components 100 according to the disclosure. Figure 1A schematically depicts a cross-sectional view of a semiconductor electronic component 100 . 1B schematically depicts a cross-sectional view of a first patterned electrode structure 112 of a semiconductor electronic component 100 . Figure 1C schematically depicts a top-down view of an overlay depicting the various components of a semiconductor electronic component 100 . The semiconductor electronics 100 depicted in Figures 1A , 1B , and 1C are bottom gate TFT elements formed on substrate 102 . The semiconductor electronic component 100 includes a substrate 102 and a gate electrode 106 disposed on the element surface 103 of the substrate 102 . The gate electrode 106 may be a patterned electrode patterned (e.g., by any suitable etching technique) from a metal layer (e.g., constituted of copper, gold, or silver) disposed on the element surface 103 . The attachment layer 108 may be disposed between the gate electrode 106 and the substrate 102 to facilitate adhesion between the gate electrode 106 and the substrate 102 . The attachment layer 108 can be patterned together with the gate electrode 106 such that the attachment layer 108 possesses a size and shape corresponding to a large extent to the gate electrode 106 .

[0058] In embodiments, substrate 102 may be made of glass, glass-ceramic, or ceramic materials. Exemplary glass materials include, but are not limited to, borosilicate glass (e.g., glass manufactured by Corning Incorporated of Corning, NY under the Corning® Willow® Glass trademark), alkaline earth borosilicate glass (e.g., glass manufactured by Corning Incorporated under the EAGLE XG® trademark), alkaline earth borosilicate glass (e.g., glass manufactured by Corning Incorporated under the Contego Glass trademark), and ion-exchanged alkaline aluminum silicate (e.g., glass manufactured by Corning Incorporated under the Gorilla® Glass trademark). It should be understood that other glasses, glass-ceramics, ceramics, multilayers, or composite compositions may be used for substrate 102. Additionally, according to this disclosure, substrate 102 may be made of materials other than glass, glass-ceramic, or ceramic materials.

[0059] Referring to Figure 1A, the semiconductor electronic device 100 further includes a first dielectric layer 109 disposed on the substrate 100. The first dielectric layer 109 may cover the gate electrode 106 and be in direct contact with the substrate 102. The first dielectric layer 109 may be formed of a plurality of different materials (e.g., silicon nitride, silicon oxide, silicon oxynitride, elastic or polymer-based dielectric layers) according to embodiments. A semiconductor layer 110 is disposed on the first dielectric layer 109. The semiconductor layer 110 may be formed of organic semiconductor materials or inorganic semiconductor materials according to embodiments. In an embodiment, the semiconductor layer 110 includes a doped semiconductor layer comprising a channel region, a source region, and a gain region. According to this disclosure, any suitable structure for the semiconductor layer 110 may be used. For example, in one embodiment, the semiconductor layer 110 includes an undoped semiconductor layer (e.g., silicon) disposed on the first dielectric layer 109 and an n-doped semiconductor layer (e.g., composed of n-doped amorphous silicon, n-doped microcrystalline silicon, n-doped polycrystalline silicon, or amorphous oxide) disposed on the undoped semiconductor layer. In another embodiment, the undoped semiconductor layer may be omitted. The semiconductor layer 110 may be patterned using any suitable technique.

[0060] The semiconductor electronic device 100 further includes a first patterned electrode structure 112 and a second patterned electrode structure 114 disposed on the semiconductor layer 110. In an embodiment, the first patterned electrode structure 112 includes a drain electrode 116 extending over a drain region of the semiconductor layer 110, and the second patterned electrode structure 114 includes a source electrode 130 extending over a source region of the semiconductor layer 110. In an embodiment, the source electrode 130 and the drain electrode 116 are patterned from a metal electrode layer disposed on the semiconductor layer 110 via any suitable deposition technique (e.g., sputtering) and subsequently etched. In an embodiment, the drain electrode 116 and the source electrode 130 are made of a pure metal such as gold, silver, or copper from their patterned metal electrode layers. For example, in an embodiment, the metal electrode layer forming the source electrode 130 and the drain electrode 116 is made of pure copper via any suitable technique (e.g., magnetron sputtering) and includes a thickness greater than or equal to 250 nm and less than or equal to 500 nm.

[0061] When the source electrode 130 and drain electrode 116 are composed of pure metal layers, pure metals such as gold, copper, and silver may not adhere to the semiconductor layer 110. Furthermore, pure metals can diffuse into the semiconductor layer 110 and generate metal silicides, thereby degrading the electrical performance of the semiconductor electronic device 100. Therefore, for example, as depicted in Figure 1B, the first patterned electrode structure 112 includes a first barrier layer 124 disposed between the drain electrode 116 and the semiconductor layer 110. The first barrier layer 124 can improve the adhesion between the metal electrode layer and the semiconductor layer 110 and prevent metal diffusion into the semiconductor layer 110. The first barrier layer 124 may be composed of various different materials depending on the embodiment, including, but not limited to, titanium, tantalum, and tantalum or tantalum nitrides. In an embodiment, the first barrier layer 124 is formed in a blanket-like manner on the semiconductor layer 110.

[0062] The first patterned electrode structure 112 further includes a second barrier layer 126 disposed on the drain electrode 116. The second barrier layer 126 prevents metal in the drain electrode 116 from diffusing into a passivation layer or other dielectric layer disposed on the first patterned electrode structure 112 (e.g., the oxide-containing passivation layer 144 herein). In an embodiment, the second barrier layer 126 is deposited in a blanket manner on the metal electrode layer 115 forming the drain electrode 116. In an embodiment, according to this specification, the second barrier layer 126 may be formed of a material similar to the first barrier layer 124, although other materials (e.g., silicon carbide, silicon nitride) may also be used. In an embodiment, the first barrier layer 124, the metal electrode layer 115, and the second barrier layer 126 are successively deposited in a blanket manner on the semiconductor layer 110, and then all are patterned in a sequential etching step to form the drain electrode 116 and the source electrode 130 as depicted in Figure 1A. The first barrier layer 124, the metal electrode layer 115, and the second barrier layer 126 can form a multilayer structure, which is patterned to remove parts of the multilayer structure in order to form individual electrodes of the semiconductor electronic device 100.

[0063] As depicted in Figure 1B, the drain electrode 116 includes a lower surface 118 of the substrate 102 (e.g., where a first barrier layer 124 is disposed between the lower surface 118 and the semiconductor layer 110), an upper surface 120, and a drain sidewall 122 extending between the lower surface 118 and the upper surface 120. After etching the multilayer structure, the drain sidewall 122 may be exposed between the first barrier layer 124 and the second barrier layer 126. That is, after patterning the multilayer structure, the drain electrode 116 is exposed to the chemical composition of the environment of the first patterned electrode structure 112. In an embodiment, the second patterned electrode structure 114, which includes the source electrode 130, is formed in the same manner (by patterning the multilayer structure of the first barrier layer 124, the metal electrode layer, and the second barrier layer 126). Therefore, the source electrode 130 may include a source sidewall 131, which is also exposed to the environment after the multilayer structure is patterned.

[0064] Due to the composition of the source electrode 130 and the drain electrode 116, such exposure of the drain electrode 116 and the source electrode 130 can lead to a deterioration in the performance of the semiconductor electronic device 100. For example, copper is particularly prone to oxidation at high temperatures of 300°C or higher. Such environmental conditions conducive to oxidation can occur during the manufacturing process of the semiconductor electronic device 100. For example, as depicted in Figure 1A, after the formation of the first patterned electrode structure 112 and the second patterned electrode structure 114, an oxide-containing passivation layer 144 is disposed on the substrate 102. The oxide-containing passivation layer 144 may be formed from a variety of different materials (e.g., SiO2, Al2O3) depending on the embodiment. In an embodiment, the oxide-containing passivation layer 144 is formed via PECVD, wherein the substrate 102 is placed in a PECVD chamber after the first patterned electrode structure 112 and the second patterned electrode structure 114 have been formed on the substrate 102. The substrate 102 can be heated in a chamber to a suitable deposition temperature (e.g., between 300°C and 400°C) and exposed to the chemical composition of the oxide-containing passivation layer 38 under suitable pressure, while plasma is present in the deposition chamber to promote the reaction of the components on the substrate 102. In this case, the exposed drain sidewall 122 and source sidewall 131 can be exposed to oxides at sufficiently high temperatures to facilitate the formation of metal oxide layers on these sidewalls.

[0065] If the exposure is retained after patterning, a metal oxide layer may be formed on the drain sidewall 122 and the source sidewall 131. Such a metal oxide layer may have a different conductivity than the remainder of the drain electrode 116 and the source electrode 130, thereby causing a change in the performance of the semiconductor electronic device 100. For example, the metal oxide layer formed at the exposed source sidewall 122 and drain sidewall 131 may change the effective area of ​​the drain electrode 116 and the source electrode 130. As depicted in Figure 1C, for example, the semiconductor electronic device 100 includes a first gate overlap region 136 in which the source electrode 130 extends over the gate electrode 106 (e.g., overlaps with the gate electrode 106 in the Z direction depicted in Figure 1C) and a second gate overlap region 140 in which the drain electrode 116 extends over the gate electrode 106. The first gate overlap region 136 is depicted as having a length of 138 in a direction extending parallel to the element surface 103 (e.g., the X direction depicted in Figure 1C), while the second gate overlap region 140 is depicted as having a length of 142 in a direction parallel to the element surface 103. The metal oxide layers formed at the source sidewall 122 and drain sidewall 131 can cause variations in the first gate overlap region 136 and the second gate overlap region 140 by altering the effective regions of the drain electrode 116 and the source electrode 130. Since the drain sidewall 122 and source sidewall 131 are exposed to oxides under conditions favorable for oxidation, the lengths 138 and 142 can differ from each other in an inconsistent manner. Such variations in the gate overlap regions 136 and 140 can affect the performance of the semiconductor electronic device 100 in various ways. For example, a variation of only 1 μm in the lengths 138 and 142 can affect various operating parameters of the semiconductor electronic device 100, including threshold voltage, scattering parameters, electron mobility, and leakage current. Such changes in operating parameters can adversely affect the operation of components incorporated into semiconductor electronic elements (e.g., touch panel elements, displays, and the like).

[0066] To prevent the formation of metal oxides at the drain sidewall 122 and source sidewall 131, the semiconductor electronic device 100 includes a drain sidewall barrier layer 128 disposed on the drain sidewall 122 and a source sidewall barrier layer 132 disposed on the source sidewall 131. In an embodiment, the drain sidewall barrier layer 128 and the source sidewall barrier layer 132 are magnesium oxide barrier layers having a thickness greater than or equal to 1 nm and less than or equal to 5 nm (e.g., in the X direction depicted in Figures 1A to 1C or in a direction perpendicular to the upper surface 118 and lower surface 120 depicted in Figure 1B). In an embodiment, the drain sidewall barrier layer 128 and the source sidewall barrier layer 132 are formed via the processes described herein such that they extend locally over the drain sidewall 122 and the source sidewall 131. For example, as described herein with respect to Figures 4A and 4B, a manganese precursor may be exposed to the drain sidewall 122 and source sidewall 131, thereby diffusing as a metallic phase into the drain electrode 116 and source electrode 130 via the drain sidewall 122 and source sidewall 131. The manganese within the drain electrode 116 and source electrode 130 then reacts with oxygen to form a magnesium oxide barrier layer at the drain sidewall 122 and source sidewall 131. Additional components of the semiconductor element 100 (e.g., the first barrier layer 124 and the second barrier layer 126, the semiconductor layer 110, etc.) resist this diffusion of the manganese precursor and are free of any manganese during subsequent oxygen exposure, such that the drain sidewall barrier layer 128 and the source sidewall barrier layer 132 extend locally over the drain sidewall 122 and source sidewall 131 between the first barrier layer 124 and the second barrier layer 126.

[0067] The manganese oxide sidewall barrier layers (e.g., drain sidewall barrier layer 128 and source sidewall barrier layer 132) herein may include manganese oxide (MnOx) and a metal (e.g., copper) forming the drain electrode 116 and source electrode 130. In embodiments, the MnOx concentration within the drain sidewall barrier layer 128 and source sidewall barrier layer decreases with increasing distance from the drain sidewall 122 and source sidewall 131. The MnOx concentration may be maximized at the surface defining the drain sidewall 122 and source sidewall 131. In embodiments, the Mn concentration within the drain sidewall barrier layer 128 and source sidewall barrier layer 132 follows an error function and decreases with increasing distance from the drain sidewall 122 and source sidewall 131. The Mn concentration within the drain sidewall barrier layer 128 and source sidewall barrier layer 132 may vary depending on the thickness of the drain electrode 116 and source electrode 130. In this embodiment, the drain sidewall barrier layer 128 and the source sidewall barrier layer 132 are 10 nm thick, and the Mn concentration within the drain sidewall barrier layer 128 and the source sidewall barrier layer 132 (e.g., at the sidewall surface) varies from greater than or equal to 0.5 wt% to less than or equal to 20 wt%. MnOx can act as a barrier to prevent further oxidation of the drain electrode and the source electrode 130 during the manufacturing process of the semiconductor electronic device 100. In this embodiment, the drain sidewall barrier layer 128 and the source sidewall barrier layer 132 are designed to maintain the variation of the length 138 of the first gate overlap region 136 and the length 142 of the second gate overlap region 140 below a predetermined threshold. For example, in this embodiment, the difference between the lengths 138 and 142 is maintained at less than or equal to 100 nm (e.g., less than or equal to 50 nm, less than or equal to 10 nm, less than or equal to 5 nm). Therefore, the performance of semiconductor electronic component 100 can be consistently maintained along with that of other semiconductor electronic components manufactured through the same process, thereby improving overall performance.

[0068] Although Figures 1A, 1B, and 1C depict manganese oxide-containing sidewall barrier layers formed only on the sidewalls of the drain electrode 116 and the source electrode 130, it should be understood that the methods described herein can be used to form manganese oxide barrier layers at various alternative locations on a semiconductor electronic device. For illustration, in the examples depicted in Figures 1A, 1B, and 1C, a sidewall barrier layer may be formed on the gate electrode 106 (e.g., on both sidewalls of the gate electrode). Such a sidewall barrier layer on the gate electrode 106 can facilitate patterning of the gate electrode 106 with tighter tolerances (e.g., by preventing oxidation of the electrode) to provide more consistent channel control. The barrier layer formation technique can be applied to any metal layer of a semiconductor device. For example, in an embodiment, the semiconductor electronic device 100 of Figures 1A, 1B, and 1C may include additional metal layers (e.g., disposed on an oxide-containing passivation layer 144). The manganese oxide barrier layer described in this article can be applied to any metal structure within semiconductor electronic components where oxidation prevention may be desired.

[0069] It should also be understood that the manganese oxide barrier layer described herein is applicable to devices other than the bottom-gate TFT elements depicted in Figures 1A, 1B, and 1C. The sidewall barrier layer described herein can be formed in TFT elements having any configuration (e.g., bottom-gate, top-gate, bottom-contact, top-contact, etc.). Furthermore, the manganese oxide barrier layer described herein can also be used in non-transistor semiconductor elements (e.g., capacitors, diodes, and the like). In embodiments, the sidewall barrier layer described herein can be used in any semiconductor electronic element including a metal electrode that provides the desired oxidation resistance. In embodiments, the sidewall barrier layer described herein is most useful for semiconductor electronic elements having an electrode size of less than or equal to 5 μm. For example, the sidewall barrier layer described herein is particularly advantageous in semiconductor electronic elements having an electrode line width of less than or equal to 1 μm and a thickness of greater than or equal to 200 nm and / or greater than or equal to 500 nm. Examples of such semiconductor elements may include capacitors, TFT elements, diodes, and the like.

[0070] The semiconductor electronic components described herein can be used in a variety of electronic assemblies. As described herein, the sidewall barrier layer can have a relatively low thickness (e.g., less than or equal to 5 nm) and minimal impact on the optical performance of lenses or emitting elements. Therefore, the semiconductor electronic components described herein can be used in a variety of display applications. The sidewall barrier layer described herein can also be used in touch panel displays utilizing copper (or other metal) metal electrodes. Thus, the semiconductor electronic components described herein can be used in a wide variety of components and applications.

[0071] Figure 2 depicts a flowchart of a method 200 for forming a manganese oxide barrier layer on the sidewalls of a semiconductor electronic device. Method 200 can be used to form various semiconductor electronic devices in which the metal electrodes require sidewall passivation. For example, method 200 can be used to construct the semiconductor electronic device 100 described herein with respect to Figures 1A, 1B, and 1C. A wide variety of semiconductor devices (e.g., TFT devices, capacitors, diodes, and the like) can be formed via method 200.

[0072] In step 202, a substrate is provided. The substrate can provide a structural base for forming additional components of a semiconductor electronic element. The substrate can be made of a wide variety of materials. For example, in an embodiment, the substrate is similar to substrate 102 described herein with respect to Figure 1A and can be made of glass, glass-ceramic, or ceramic materials. In an embodiment, the substrate is a plastic-based substrate.

[0073] In step 204, a patterned electrode structure is formed on the substrate. The patterned electrode structure may include a metal electrode layer made of pure metal (e.g., copper, gold, or silver). The patterned electrode structure may vary depending on the nature of the semiconductor electronic device formed by performing method 200. Furthermore, various components of the semiconductor electronic device are formed on the substrate prior to forming the patterned metal structure. In an example where a bottom-gate TFT element, such as the semiconductor electronic device 100 described herein, is formed therein, the patterned electrode structure may correspond to a first patterned electrode structure 112 and / or a second patterned electrode structure 114. In this case, method 200 may include forming a gate electrode 106, a dielectric layer 109, and a semiconductor layer 110 prior to performing step 204.

[0074] Forming a patterned electrode structure may involve blanket-depositing a pure metal electrode layer onto the substrate provided in step 202 (or any intervening structure disposed on the substrate) via any suitable technique (e.g., sputtering). In embodiments, the metal electrode layer is made of copper, gold, or silver and has a thickness greater than or equal to 100 nm and less than or equal to 500 nm. Depending on the type of substrate used or the composition of any intervening structure disposed on the substrate, the patterned electrode structure may include one or more barrier layers. Thus, in addition to the pure metal electrode layer, one or more barrier layers may also be blanket-deposited on the substrate. After blanket deposition, the multilayer structure (e.g., comprising a pure metal electrode layer and one or more barrier layers) may be patterned (e.g., via a suitable etching technique) into a patterned electrode structure. Due to patterning, at least one sidewall of the pure metal electrode layer may be exposed (e.g., exposed by any other layer of the multilayer structure), preserving sidewalls that are susceptible to oxidation and subsequent device formation degradation.

[0075] In step 206, the patterned electrode structure is exposed to the manganese precursor while the patterned electrode structure is heated to the deposition temperature. In an embodiment, manganese in the pure metal (e.g., copper) constituting the pure metal electrode layer of the patterned electrode structure may have a temperature-dependent diffusion constant. For example, manganese in polycrystalline copper may have a relatively high diffusion constant at temperatures greater than or equal to 300°C and less than or equal to 400°C (e.g., greater than or equal to 350°C and less than or equal to 400°C). Therefore, in an embodiment, heating the substrate and the patterned electrode structure to a suitable deposition temperature and exposing them to the manganese precursor in the deposition chamber allows manganese in the manganese precursor to diffuse to the exposed sidewalls in the pure metal electrode layer, so that manganese exists as a metallic phase within the pure metal electrode layer. In an embodiment, other components of the semiconductor electronic device exposed to the manganese precursor in the deposition chamber (e.g., dielectric layers, semiconductor layers, barrier layers disposed on the electrode layer) do not have a manganese diffusion constant as high as that of the metal electrode layer. In view of this, manganese can be removed from the deposition chamber after the exposure cycle and remain in the patterned electrode structure only at or near the exposed sidewalls, resulting in a barrier layer that is formed only subsequently at the sidewalls, thereby preventing the adverse effects of manganese in other components such as electrodes (e.g., increased line resistance in the electrodes).

[0076] According to this disclosure, various manganese precursors can be used. In embodiments, for example, (MeCp)Mn(CO)3, (EtCp)2Mn, or Cp2Mn can be used as manganese precursors. In embodiments, the manganese precursor is amidine manganese having the following structure: wherein R1, R2, R3, R1', R2', and R3' are groups composed of one or more non-metallic atoms. In embodiments, R1, R2, R1', and R2' are isopropyl groups, and R3 and R3' are n-butyl groups. In embodiments, amidine manganese may include manganese(II)(R1-R2-amidinyl)R3 or manganese(II)(R1'-R2'-amidinyl)R3', wherein R1, R2, R1', and R2' are isopropyl groups, and R3 and R3' are n-butyl groups. In an embodiment, amidomanganese comprises bis(N,N-diisopropylpentylamine)manganese(II) having the following structure, and is supplied to the deposition chamber via a bubbler in fluid communication with the deposition chamber.

[0077] In an embodiment, a manganese precursor can be heated in a bubbler to a temperature of at least 75°C (e.g., greater than or equal to 75°C and less than or equal to 100°C), converted into a gas, and delivered to the deposition chamber, while the substrate and patterned electrodes are heated to the deposition temperature. When the pressure in the deposition chamber is greater than or equal to 0.1 Torr and less than or equal to 100 Torr (e.g., greater than or equal to 1 Torr and less than or equal to 10 Torr), the patterned electrode structure is exposed to the manganese precursor to promote manganese diffusion while limiting the processing time. Exposure to the precursor can occur over a predetermined period, allowing a sufficient amount of manganese to diffuse into the metal electrode layer. In an embodiment, the predetermined period is greater than or equal to 1 second to provide manganese to the sidewalls and less than or equal to 20 minutes. In an embodiment, the deposition period is greater than or equal to 3 minutes and less than or equal to 6 minutes. This period forms a sufficiently thick sidewall barrier layer while limiting the processing time. Furthermore, exposure to the manganese precursor for more than 20 minutes can lead to increased line resistance within the metal electrode layer and reduced device performance. It should be understood that the exposure period to the manganese precursor may depend on the deposition temperature to which the patterned electrode structure is heated. For example, if the deposition temperature is greater than or equal to 350°C, the deposition time may be less than or equal to 1 minute (e.g., greater than or equal to 1 second and less than or equal to 1 minute).

[0078] Following exposure to the manganese precursor, the patterned electrode structure is exposed to the oxide in step 208. In an embodiment, the manganese precursor is removed from the deposition chamber before exposure to the oxide, such that residual manganese is largely contained within the inner sidewalls of the metal electrode layer to avoid the formation of a manganese oxide layer at an undesirable location on the semiconductor electronic device. The oxide can react with the manganese remaining on the sidewalls of the metal electrode layer to form a magnesium oxide barrier layer having a decreasing MnOx concentration with respect to distance from the sidewalls. MnOx can prevent oxidation of the metal electrode layer and maintain the conductivity on the metal electrode layer at a greater level than would be without the formation of the magnesium oxide barrier layer, thus helping to maintain the electrical performance of the semiconductor electronic device. In an embodiment, a native metal oxide layer may have already formed on the sidewalls before exposure to the manganese precursor. In such embodiments, the native oxide can be reduced before performing steps 206 and 208 to promote the diffusion of manganese into the metal electrode layer. In one embodiment, H2 can be introduced into the deposition chamber at a temperature greater than or equal to 300°C to reduce the natural oxides in preparation for the formation of the magnesium oxide sidewall barrier layer.

[0079] In embodiments, steps 206 and 208 of method 200 are performed during the fabrication process of various other parts of a semiconductor electronic device. For example, in embodiments, the semiconductor electronic device may include an oxide-containing passivation (or other) layer that contacts sidewalls exposed by patterning a patterned electrode structure. Such an oxide-containing passivation layer may involve exposing the patterned electrode structure to conditions conducive to oxidation of the metal electrode layer. For example, in embodiments, the oxide-containing passivation layer may be formed via a PECVD process.

[0080] Figure 3 depicts an exemplary PECVD reactor 300 that can be used to deposit components of semiconductor electronic devices (e.g., an oxide-containing passivation layer 144 for the semiconductor electronic device 100 depicted in Figure 1) and form a sidewall barrier layer. The PECVD reactor 300 includes a PECVD chamber 302 through which a component gas of the generated components is introduced and reacted via a plasma-enhanced process. The PECVD chamber 302 includes an opening (not depicted) to facilitate the introduction of a substrate 304 (e.g., substrate 102 described in Figure 1) on which the semiconductor device assembly is formed. The substrate 304 is shown as being disposed on a substrate holder (e.g., an anode) 306. In an embodiment, the PECVD reactor 300 includes a showerhead (e.g., a cathode) 308 through which the component gas enters the PECVD chamber 302. In an embodiment, the PECVD reactor 300 further includes an RF source (not depicted) and associated circuitry electrically coupled to a showerhead 308. An RF signal can be supplied to the showerhead 308 and cause a discharge extending between the showerhead 308 and the substrate holder 306. The discharge can electronize atoms in the component gas, causing the electronized atoms to be electroattracted to the substrate 304 and undergo a chemical reaction on the substrate 304.

[0081] It should be understood that the diagram of the PECVD reactor 300 in Figure 3 is simplified herein for the purposes of discussion. For example, in an embodiment, the substrate holder 306 includes one or more heating elements for heating the substrate 304 to a suitable temperature for component forming. A pump (not shown) may also be fluidly connected to the interior of the PECVD chamber 302 to regulate the pressure within the PECVD chamber 302 and to remove chemicals from it once the component deposition process is complete. Gas injectors (not shown) for regulating the flow rate of various chemicals forming the component may also be fluidly connected to the interior of the PECVD chamber 302. For example, for depositing an oxide-containing passivation layer such as SiO2, a silicon gas source (e.g., silane) and an oxygen gas source (e.g., oxygen or nitrous oxide) may be fluidly connected to the interior of the PECVD chamber 302. The flow rate of the component gases may be regulated by valves.

[0082] Still referring to Figure 3, the PECVD reactor 300 further includes a carrier gas source 310 in fluid communication with the PECVD chamber 302. The carrier gas source 310 provides a gas carrier for circulating components to the PECVD chamber 302. In embodiments, the carrier gas is an inert gas (e.g., argon) that can act as a diluent to prevent unwanted gas-phase reactions. It should be understood that any number of gas injectors and carrier gas sources can be used according to this disclosure, as the number of such components can vary depending on the semiconductor electronics being formed and the chemical composition being reacted.

[0083] The PECVD reactor 300 further includes a bubbler 312 focused on introducing a manganese precursor for forming the sidewall barrier layer described herein. The bubbler 312 contains the manganese precursor (e.g., described in conjunction with step 206 of method 200 of Figure 2 herein). In embodiments, the manganese precursor may be solid at room temperature but has a melting point of approximately 60°C. The bubbler 312 may heat the manganese precursor above its melting point to form a manganese precursor gas, which is delivered from a gas carrier source 310 to the PECVD chamber 302 via a gas carrier. As depicted, the bubbler 312 is in fluid communication with a showerhead 308 via a delivery line 314. In embodiments, to facilitate the delivery of the manganese precursor to the substrate 304, the delivery temperature of the manganese precursor at the showerhead 308 is greater than or equal to 70°C or less than or equal to 100°C. Therefore, the shower head 308 and the delivery line 314 can be heated to the delivery temperature to promote the formation of the sidewall barrier layer in this paper.

[0084] By incorporating a bubbler 312, the PECVD reactor 300 facilitates the formation of the sidewall barrier layer described herein during the formation of other components of the semiconductor electronic device. For example, as described herein with respect to Figure 5, the PECVD reactor 300 can facilitate the formation of the sidewall barrier layer on the source and gate sidewalls of a TFT element during the formation of an oxide-containing passivation layer on the source and gate sidewalls. For instance, after the exposed sidewalls of the metal electrode layer of the semiconductor electronic device disposed in the PECVD chamber 302 are exposed to a manganese precursor via the bubbler 312, the oxide introduced into the PECVD chamber 302 during the deposition of subsequent layers can react with the manganese at the sidewalls to form the sidewall barrier layer while the subsequent layer is being formed. This process allows the sidewall barrier layer described herein to be generated with minimal disruption to existing manufacturing processes.

[0085] Figures 4A and 4B depict the stage of forming a manganese oxide barrier layer 402 at the sidewall 404 of a patterned electrode structure 400 of a semiconductor electronic element. In an embodiment, the patterned electrode structure 400 is a source electrode or drain electrode of a TFT element. For example, as depicted, the patterned electrode structure 400 is structurally similar to the first patterned electrode structure 112 described herein with respect to Figure 1, including an electrode 450 having a first surface 452, a second surface 454, and a sidewall 404 extending between the first surface 452 and the second surface 454. The electrode 450 is disposed on a semiconductor layer 460. A first barrier layer 456 contacts the first surface 452 and is disposed between the electrode 450 and the semiconductor layer 460, while a second barrier layer 458 contacts the second surface 454. In an embodiment, the electrode 450 is a pure metal electrode made of copper, gold, or silver. In this embodiment, a patterned electrode structure 400 is formed on the semiconductor layer 460 by blanket deposition of a first barrier layer 456, a metal electrode layer and a second barrier layer 458 and subsequent patterning of the multilayer structure.

[0086] Figure 4A depicts a patterned electrode structure 400 immediately after exposure to the manganese precursor 406. The manganese precursor 406 can be any of the manganese precursors described herein (e.g., manganese amidine). For example, the patterned electrode structure 400 can be disposed on the substrate holder 306 of the PECVD reactor 300 described herein with respect to Figure 3, and subsequently heated to a temperature of approximately 350°C. At this temperature, the diffusion constant of manganese within the electrode 450 (e.g., made of copper) can be relatively high. The bubbler 312 can then be heated to generate gaseous manganese precursor 406, which can be guided into the PECVD chamber 302 via a heated delivery line 314 and a showerhead 308. Plasma in the PECVD chamber can facilitate the collection of manganese precursor 406 on the electrode 450. The sidewall 404 may be only the exposed portion of the electrode 450, allowing manganese from the manganese precursor 406 to diffuse as a metallic phase into and be disposed within the sidewall 404 of the electrode 450. As depicted, the concentration of manganese may decrease with increasing distance from the sidewall 404.

[0087] After manganese is deposited on electrode 450, the manganese precursor 406 can be evacuated from the PECVD chamber 302, leaving residual manganese largely at the inner sidewall 404 of electrode 450. After evacuation, oxide can be introduced into the PECVD chamber 302. The oxide can be derived from oxide precursor gas directed into the PECVD chamber 302 during the deposition of additional components of the semiconductor electronic element of the patterned electrode structure 400. In an embodiment, the oxide in the PECVD chamber 302 can react with manganese disposed at the sidewall 404 to form a manganese oxide barrier layer 402 comprising manganese and the metal constituting electrode 450. The manganese oxide barrier layer 402 can have a thickness greater than or equal to 1 nm and less than or equal to 5 nm. In an embodiment, the manganese oxide concentration within the manganese oxide barrier layer 402 decreases with increasing distance from the sidewall 404, depending on the amount of manganese present in electrode 450 before the introduction of the oxide. As illustrated by the process depicted in Figures 4A and 4B, the sidewall barrier layer described herein can be formed in the PECVD chamber currently used in existing manufacturing processes with minimal interruptions and increased setup time.

[0088] Referring now to Figure 5, a flowchart of a method 500 for manufacturing a TFT element comprising a source sidewall barrier layer and a gate sidewall barrier layer is depicted. In an embodiment, method 500 may be performed using the PECVD reactor 300 described herein with respect to Figure 3. In an embodiment, method 500 may be used to form the semiconductor electronic element 100 described herein with respect to Figure 1, although it should be understood that method 500 may be used to form TFT elements having alternative structures and configurations. In step 502, a substrate is provided. The substrate may include glass, glass-ceramic, ceramic, a plastic-based substrate, or any other suitable material according to the embodiment. In an embodiment, the substrate may have dimensions (e.g., less than or equal to 5 μm, less than or equal to 1 μm) or smaller (e.g., length and / or width). In step 504, a gate electrode is formed on the element surface of the substrate. For example, referring to the semiconductor electronic device 100 described herein with reference to Figures 1A, 1B, and 1C, a copper metal electrode layer can be deposited on the device surface 103 using any suitable technique to form a gate electrode 106. In an embodiment, after forming the gate electrode, a sidewall barrier layer can be formed on the sidewalls of the gate electrode by, for example, performing the method 200 described herein with reference to Figure 2. Such a sidewall barrier layer on the gate electrode allows for more precise patterning of the gate electrode (e.g., by preventing oxide formation) and better control over the operation of the semiconductor electronic device.

[0089] In steps 506 and 508, a gate dielectric layer and a semiconductor layer are formed on the gate electrode. The constituent materials of the gate dielectric layer and the semiconductor layer can be deposited onto the substrate in a blanket manner using any suitable technique and patterned based on the configuration of the semiconductor electronic device. At step 510, a metal electrode structure including a source electrode with a source sidewall and a drain electrode with a drain sidewall is formed on the substrate. In an embodiment, the source electrode and the drain electrode are formed by deposition and patterning of the same multilayer structure. For example, as described herein with respect to the semiconductor electronic device 100 of Figures 1A, 1B, and 1C, the drain electrode 116 and the source electrode 130 are simultaneously formed by blanket deposition of a multilayer structure including a first barrier layer 124, a metal electrode layer, and a second barrier layer 126, followed by patterning of the multilayer structure via an etching step. In this example, etching can remove a portion of the multilayer structure to simultaneously expose the drain sidewall 122 and the source sidewall 131 between the first barrier layer 124 and the second barrier layer 126. In an embodiment, the source electrode and the drain electrode can be formed in a separate deposition step.

[0090] At step 512, the metal electrode structure is exposed to the manganese precursor. For example, in an embodiment, a substrate on which the metal electrode structure is disposed may be placed in a deposition chamber. For example, the PECVD chamber 302 described herein with respect to Figure 3 may serve as the deposition chamber. After the substrate is placed in the PECVD chamber 302, any glass present in the PECVD chamber 302 is removed, and it is pumped to a baseline pressure (e.g., less than or equal to 10 Torr). In an embodiment, during or after pumping the PECVD chamber 302 to the baseline pressure, a heating element in the substrate holder 306 may heat the substrate to a predetermined deposition temperature. In an embodiment, the deposition temperature is based on the diffusion function of manganese in the metal constituting the metal electrode layer. For example, in an embodiment, the metal electrode layer is copper, and the substrate is heated to a temperature greater than or equal to 300°C and less than or equal to 400°C (e.g., greater than or equal to 340°C and less than or equal to 360°C, or greater than or equal to 345°C and less than or equal to 355°C). At the deposition temperature, the diffusion constant of manganese in copper can be relatively high to promote manganese entry into the exposed sidewalls of the metal electrode layer.

[0091] In an embodiment, after heating the substrate to the deposition temperature, the bubbler 312 can be heated to a temperature above the melting point of the manganese precursor (e.g., greater than or equal to 60°C) and guided into the PECVD chamber 302 via a heated delivery line 314 (e.g., heated to greater than or equal to 75°C and less than or equal to 100°C). The manganese precursor can be carried from the carrier gas source 310 by a carrier gas, thereby maintaining the PECVD chamber at a predetermined deposition pressure for the exposure cycle. In an embodiment, the exposure cycle is greater than or equal to 1 minute and less than or equal to 20 minutes (e.g., greater than or equal to 3 minutes or less than or equal to 6 minutes), and the deposition pressure is greater than or equal to 0.1 Torr and less than or equal to 100 Torr (e.g., greater than or equal to 1 Torr or less than or equal to 10 Torr). The manganese precursor can diffuse into the metal electrode through the exposed sidewalls. For example, in manufacturing the semiconductor electronic device 100 described herein with reference to Figure 1, a manganese precursor can diffuse into the drain electrode 116 at the drain sidewall 122 and the source electrode 130 at the source sidewall 131, respectively. As depicted in Figure 4A, a concentration gradient of the manganese precursor, which decreases with increasing distance from each of the sidewalls, exists at the exposed sidewalls. In an embodiment, after exposure to the manganese precursor, the PECVD chamber 302 is cleaned and pumped to baseline pressure. This step can advantageously remove manganese from portions of the semiconductor electronic device where undesirable barrier layers may form.

[0092] At step 514, sidewall barrier layers are simultaneously formed on the source and drain sidewalls during the deposition of the oxide-containing passivation layer on the patterned electrode structure. For example, after cleaning the PECVD chamber 302, the chemical composition of the oxide-containing passivation layer may flow into the PECVD chamber 302. The composition may vary depending on the formation of the oxide-containing passivation layer. For example, in an embodiment, the oxide-containing passivation layer 144 of the semiconductor electronic device 100 described herein with respect to Figure 1 may be a SiOx passivation layer. In such embodiments, the chemical composition may include a silicon precursor (e.g., silane) and the oxygen precursor may include N2O. After the pressure within the PECVD chamber 302 increases to the desired deposition temperature, an RF signal may be supplied to the showerhead 308 to induce a discharge between the showerhead 308 and the substrate holder 306. The component gases can be ionized to facilitate their migration to the surface of the semiconductor electronic device and the exposed source and drain sidewalls. The oxide can react with manganese previously diffused into the source and drain electrodes to form manganese oxide source and drain sidewall barrier layers (e.g., drain sidewall barrier layer 128 and source sidewall barrier layer 132 as described herein with respect to Figure 1A). Additionally, the oxide can react with other components of the oxide-containing passivation layer to form a passivation layer on the patterned electrode structure. After a deposition cycle for forming a passivation layer of the desired thickness, the PECVD cavity can be cleaned again and pumped to baseline pressure, and the substrate can be removed from the PECVD chamber 302.

[0093] In step 512, an additional metal layer may be formed on the oxide-containing passivation layer to complete the fabrication of the TFT element. For example, in an embodiment, the TFT element may include an additional gate disposed on the oxide-containing passivation layer. Metal contacts may also be deposited on the oxide-containing passivation layer overlapping with the source and drain electrodes. According to this disclosure, any number of additional metal layers may be included on the TFT element.

[0094] It should be understood that the steps of method 500 can occur in various sequences depending on the configuration of the TFT element being manufactured. For example, when manufacturing a top-gate TFT element, a patterned electrode structure can be deposited on the substrate before forming the semiconductor layer or gate electrode. Furthermore, according to embodiments, semiconductor layers can be formed on the source electrode and drain electrode. The sidewall barrier layer described herein does not need to be formed within the PECVD chamber, but can be formed in a separate deposition step. Typically, the sidewall barrier layer described herein can be used in any application where the metal electrode layer made of gold, copper, or silver can be exposed to oxides at high temperatures.

[0095] In view of the foregoing, it should be understood that the use of manganese precursors and subsequent oxide exposure can be used to form a manganese oxide barrier layer that locally extends over the exposed sidewalls of the patterned electrode structure of a semiconductor electronic device. Such a sidewall barrier layer can prevent oxidation of the electrode at the exposed sidewalls, thereby facilitating a more precise definition of the electrode geometry compared to manufacturing methods that do not include such a sidewall barrier layer. The sidewall barrier layer described herein is particularly useful in manufacturing methods where pure metal electrodes are exposed to oxides in an environment conducive to electrode oxidation. Furthermore, the sidewall barrier layer described herein can be formed with minimal disruption to existing device manufacturing processes. The manganese precursor layer can be added to existing PECVD reactors used to form passivation layers with minimal reconfiguration of the required setup process. Therefore, the method described herein improves device performance without hindering production efficiency.

[0096] Although exemplary embodiments have been described herein, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the scope of the appended claims. [Simplified Explanation of the Diagram]

[0040] The above will become apparent from the following more specific description of exemplary embodiments, as illustrated in the accompanying drawings, in which the same reference characters refer to the same parts in different views. The drawings are not necessarily drawn to scale and are intended to illustrate representative embodiments.

[0041] Figure 1A schematically depicts a cross-sectional view of a semiconductor electronic component according to one or more embodiments herein;

[0042] Figure 1B schematically depicts a cross-sectional view of a patterned electrode structure of a semiconductor electronic element depicted in Figure 1A according to one or more embodiments herein;

[0043] Figure 1C schematically depicts a top-down view of the electrode coverage and associated gate overlap area of ​​a semiconductor electronic element depicted in Figure 1A according to one or more embodiments herein;

[0044] Figure 2 illustrates a flowchart of a method for forming a manganese oxide barrier layer on the sidewall of a metal electrode according to one or more embodiments herein;

[0045] Figure 3 schematically depicts a plasma-enhanced chemical deposition reactor for manufacturing semiconductor electronic components including a manganese oxide sidewall barrier layer according to one or more embodiments herein;

[0046] Figure 4A schematically depicts a patterned electrode structure of a semiconductor according to one or more embodiments herein after exposure to a manganese precursor;

[0047] Figure 4B schematically depicts the patterned electrode structure depicted in Figure 4A after exposure to oxides, according to one or more embodiments herein, resulting in the formation of a manganese oxide barrier layer; and

[0048] Figure 5 is a flowchart of a method for manufacturing a thin-film transistor device including at least one sidewall barrier layer according to one or more embodiments. [Biomaterial Storage]

[0098] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A semiconductor element comprising: A substrate including a component surface; a patterned metal electrode disposed on the substrate, the patterned metal electrode being formed of one or more of copper, gold, and silver, the patterned metal electrode including a lower surface adjacent to the substrate, an upper surface, and a sidewall extending between the lower surface and the upper surface; and a sidewall barrier layer extending over the sidewall; a gate electrode disposed on the substrate; a dielectric layer disposed on the gate electrode; a semiconductor layer disposed on the dielectric layer; a source electrode disposed on a first portion of the semiconductor layer; and a drain electrode disposed on a second portion of the semiconductor layer, wherein: The source electrode and the drain electrode overlap with the gate electrode in the first gate overlap region and the second gate overlap region in a direction perpendicular to the surface of the element; and the patterned metal electrode is one of the source electrode and the drain electrode, such that the sidewall barrier layer directly contacts the source electrode or the drain electrode; wherein the lengths of the first gate overlap region and the second gate overlap region differ from each other by less than or equal to 10 nm.

2. The semiconductor device as claimed in claim 1, wherein the sidewall barrier layer comprises a manganese oxide barrier layer.

3. The semiconductor device as claimed in claim 2, wherein the sidewall barrier layer has a thickness of greater than or equal to 1 nm and less than or equal to 5 nm.

4. The semiconductor device as described in claim 2, further comprising: A first barrier layer is in contact with the lower surface and disposed between the patterned metal electrode and the substrate; And a second barrier layer that contacts the upper surface, wherein neither the first barrier layer nor the second barrier layer directly contacts the sidewall.

5. The semiconductor device as claimed in claim 4, wherein the sidewall barrier layer is disposed directly on the sidewall between the first barrier layer and the second barrier layer.

6. The semiconductor device as claimed in claim 1, further comprising an oxide-containing passivation layer disposed on the patterned metal electrode, the oxide-containing passivation layer directly contacting at least a portion of the sidewall barrier layer.

7. The semiconductor device as claimed in claim 1, wherein the other of the source electrode and the drain electrode, which is not the patterned metal electrode, includes a lower surface, an upper surface, and an additional sidewall extending between the lower surface and the upper surface of the substrate, the semiconductor device further including an additional sidewall barrier layer partially disposed on the additional sidewall.

8. The semiconductor device as claimed in claim 7, further comprising a passivation layer disposed on the source electrode and the drain electrode, the passivation layer containing an oxide, wherein the passivation layer directly contacts at least a portion of the sidewall and the additional sidewall.

9. The semiconductor device as claimed in claim 8, further comprising an additional metal layer disposed on the source electrode and the drain electrode.

10. The semiconductor device as claimed in claim 7, further comprising a copper barrier layer partially disposed on the gate electrode, the copper barrier layer being in direct contact with the gate electrode.

11. The semiconductor device as claimed in claim 1, wherein the patterned metal electrode is a component of a thin-film transistor.

12. The semiconductor element as claimed in claim 11, wherein the thin-film transistor is a component of a touch panel display.

13. A method for manufacturing a semiconductor electronic component, the method comprising the following steps: Provide a substrate; A patterned electrode structure is formed on the substrate, the patterned electrode structure comprising: a first barrier layer disposed on the substrate; a metal electrode layer disposed on the first barrier layer, the metal electrode layer being formed of one or more of copper, gold, and silver; and a second barrier layer disposed on the upper surface of the metal electrode layer, wherein the first barrier layer, the metal electrode layer, and the second barrier layer are patterned such that one sidewall of the metal electrode layer is exposed between the first barrier layer and the second barrier layer; the substrate is heated to a deposition temperature of at least 300°C; At the deposition temperature, the patterned electrode structure is exposed to a manganese precursor in a deposition chamber for a deposition cycle, wherein during the deposition cycle, one of the pressures at the deposition temperature is at least 0.1 Torr, the deposition cycle is at least 1 second, and the manganese precursor selectively migrates to the sidewall; and after exposing the substrate to the manganese precursor, the patterned electrode structure is exposed to an oxide that reacts with the manganese precursor to form a MnOx barrier layer locally disposed on the sidewall; the semiconductor electronic device includes: a gate electrode disposed on the substrate; a dielectric layer disposed on the gate electrode; a semiconductor layer disposed on the dielectric layer; a source electrode disposed on a first portion of the semiconductor layer; and a drain electrode disposed on a second portion of the semiconductor layer, wherein: The source electrode and the drain electrode overlap with the gate electrode in the first gate overlap region and the second gate overlap region in a direction perpendicular to the surface of the element; and the patterned metal electrode is one of the source electrode and the drain electrode, such that the sidewall barrier layer directly contacts the source electrode or the drain electrode; wherein the lengths of the first gate overlap region and the second gate overlap region differ from each other by less than or equal to 10 nm.

14. The method as described in claim 13, wherein the manganese precursor is an amidomanganese having the structure and is supplied to the deposition chamber via a bubbler in fluid communication with the deposition chamber.

15. The method as described in claim 13, wherein the manganese precursor is an amidomanganese having the structure wherein R1, R2, R3, R1', R2' and R3' are groups composed of one or more nonmetallic atoms.

16. The method as described in claim 15, wherein R1, R2, R1' and R2' are isopropyl groups and R3 and R3' are n-butyl groups.

17. The method as described in claim 13, further comprising the step of: depositing an oxide-containing passivation layer on the patterned electrode structure, the oxide-containing passivation layer at least partially contacting the MnOx barrier layer.

18. The method of claim 17, wherein the oxide reacting with the manganese precursor to form a MnOx barrier layer is a component of the oxide-containing passivation layer, such that the MnOx barrier layer is formed during the deposition of the oxide-containing passivation layer.

19. The method as described in claim 18, wherein the oxide-containing passivation layer is deposited in a plasma-enhanced chemical vapor deposition chamber.

20. The method of claim 19, wherein the deposition chamber of the patterned electrode structure exposed to the manganese precursor corresponds to the plasma-enhanced chemical vapor deposition chamber, such that the patterned electrode structure remains in the plasma-enhanced chemical vapor deposition chamber for both exposure to the manganese precursor and deposition of the oxide-containing passivation layer.

21. The method of claim 20, wherein the manganese precursor is introduced into the plasma-enhanced chemical vapor deposition chamber via a bubbler in fluid communication with the plasma-enhanced chemical vapor deposition chamber, wherein the bubbler is heated to a temperature greater than or equal to 75°C and less than or equal to 100°C before the manganese precursor is introduced into the plasma-enhanced chemical vapor deposition chamber.

22. The method as described in claim 13, wherein the semiconductor electronic element is a thin-film transistor element.

23. A method for manufacturing a thin-film transistor, the method comprising the steps of: providing a substrate; depositing a gate electrode layer on a component surface of the substrate and patterning the gate electrode layer into a gate electrode; depositing a dielectric layer on the gate electrode layer; depositing a semiconductor on the dielectric layer; forming a patterned electrode structure on the channel, the patterned electrode structure comprising a first barrier layer disposed on the semiconductor layer, an electrode layer disposed on the first barrier layer, and a second barrier layer disposed on the electrode layer, wherein the electrode layer comprises a drain portion including a drain sidewall and a source portion including a source sidewall, the drain sidewall and the source sidewall being disposed on the gate electrode, the source electrode and the drain electrode overlapping the gate electrode in a direction perpendicular to the component surface at a first gate overlap region and a second gate overlap region, wherein the lengths of the first gate overlap region and the second gate overlap region differ from each other by less than or equal to 10 nm; Simultaneously, a sidewall barrier layer and an oxide-containing passivation layer extending above the source sidewall and the gate sidewall are formed on the patterned electrode structure, wherein the step of simultaneously forming the sidewall barrier layer and the oxide-containing passivation layer includes: The substrate and the patterned electrode structure are placed in a plasma-enhanced chemical vapor deposition chamber that is in fluid communication with a bubbler containing a manganese precursor. The manganese precursor is allowed to flow into the deposition chamber for a predetermined period, while the substrate and the patterned electrode are heated to a deposition temperature; and the chemical components of the oxide-containing passivation layer are allowed to flow into the deposition chamber, so that an oxide reacts with the manganese precursor to form a manganese oxide sidewall barrier layer on the source sidewall and the gate sidewall.

24. The method as described in claim 23, wherein the manganese precursor is an amidomanganese having the structure and is supplied to the deposition chamber via a bubbler in fluid communication with the deposition chamber.

25. The method as described in claim 23, wherein the manganese precursor is an amidomanganese having the structure in which R1, R2, R3, R1'R2' and R3' are groups composed of one or more nonmetallic atoms.

26. The method as described in claim 25, wherein R1, R2, R1' and R2' are isopropyl groups and R3 and R3' are n-butyl groups.

27. The method as described in claim 23, wherein the electrode layer is formed of one or more of copper, gold and silver.

28. The method as described in claim 23, wherein the electrode layer is formed of pure copper.

29. The method as described in claim 23, wherein the deposition temperature is greater than or equal to 300°C.

30. The method as described in claim 23, wherein the deposition temperature is greater than or equal to 350°C.

31. The method as described in claim 23, wherein the predetermined period is greater than or equal to 15 minutes.

32. The method as described in claim 23, wherein the oxide-containing passivation layer comprises silicon oxide.

33. The method as described in claim 23, further comprising the step of exposing the gate electrode to a manganese precursor at a high temperature before depositing the dielectric layer on the gate electrode.

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