Supply-glitch-tolerant regulator

Abstract

This invention discloses a power fault-tolerant voltage regulator, comprising an adjustable voltage node and an output transistor having a source terminal, a gate terminal, and a drain terminal. The source terminal is coupled to the adjustable voltage node. The power fault-tolerant voltage regulator includes a first current generator coupled between a first node and a first power node. The power fault-tolerant voltage regulator includes a second current generator coupled between the first node and a second power node. The power fault-tolerant voltage regulator includes a feedback circuit coupled to the first current generator and the second current generator and configured to adjust a voltage at the first node based on a reference voltage and a voltage level at the adjustable voltage node. The power fault-tolerant voltage regulator includes a diode coupled between the drain terminal and the first power node and a resistor coupled between the gate terminal and the first node.

Description

Technical Field

[0001] This invention relates to integrated circuits, and more specifically, to a voltage regulation circuit that provides a target voltage level under varying conditions. Prior Technology

[0002] Generally, a voltage regulator is a system that maintains a constant voltage level. In an exemplary application, the presence of parasitic inductance can cause a high-frequency, high-amplitude AC signal (i.e., ringing) superimposed on a power node during rapid switching of high current. Depending on the rate of change of the load current in the circuit and the output parasitic capacitance, the power supply voltage level may fail, for example, dropping to ground for a short period during ringing. A power failure can cause a temporary low-voltage reset and subsequent start-up sequence in an integrated circuit system, which is undesirable in normal operation. One purpose of a low-dropout regulator is to prevent a regulated voltage from dropping below a target regulated voltage level VREG during a power failure of less than a specified duration from a target regulated voltage level VREG. If the regulated output voltage does not exceed this specified minimum voltage level during a power failure, the analog and digital circuits will be reset, and the state of the digital circuitry will be disrupted during and after the power failure. Therefore, improved techniques for regulating a voltage level are desired. Summary of the Invention

[0003] In at least one embodiment, a power fault-tolerant voltage regulator includes: a regulating voltage node; and an output transistor having a source terminal, a gate terminal, and a drain terminal. The source terminal is coupled to the regulating voltage node. The power fault-tolerant voltage regulator includes a first current generator coupled between a first node and a first power node. The power fault-tolerant voltage regulator includes a second current generator coupled between the first node and a second power node. The power fault-tolerant voltage regulator includes a feedback circuit coupled to the first current generator and the second current generator and configured to adjust a voltage at the first node based on a reference voltage and a voltage level at the regulating voltage node. The power fault-tolerant voltage regulator includes a diode coupled between the drain terminal and the first power node and a resistor coupled between the gate terminal and the first node.

[0004] In at least one embodiment, a method for generating a power fault-tolerant reference voltage includes generating an output voltage at a regulating voltage node based on a reference voltage level. The method further includes maintaining the output voltage at the regulating voltage node above a predetermined voltage level during a power voltage fault spanning one of a first power node and a second power node. The fault has a duration less than or equal to a target power fault tolerance. Simple Explanation of the Diagram

[0005] Those skilled in the art will better understand the invention and its various objects, features and advantages by referring to the accompanying drawings.

[0006] Figure 1 shows a functional block diagram of an integrated circuit low-dropout regulator in an exemplary integrated circuit system.

[0007] Figure 2 illustrates a circuit diagram of an exemplary low-dropout regulator and associated current flow in response to an exemplary power failure event.

[0008] Figure 3 illustrates a circuit diagram of an exemplary power failure-tolerant voltage regulator consistent with at least one embodiment of the present invention.

[0009] Figure 4 illustrates an exemplary power failure event and associated response waveform of one of various embodiments of a voltage regulator consistent with at least one embodiment of the present invention.

[0010] The use of symbols for the same element in different diagrams indicates similar or identical objects. Implementation

[0011] Referring to Figures 1 and 2, a low-dropout regulator 102 provides a regulated output voltage level at a regulated voltage node VREG, which serves as the power supply voltage for analog and digital circuits. The low-dropout regulator 102 includes a source follower output stage (i.e., a common-drain amplifier, such as an output transistor M PASS, which is n-type in one exemplary embodiment), configured to provide the regulated voltage VREG and an associated current (e.g., 1 mA). A compensation capacitor CCOM is sized to provide a pole of the loop gain of the low-dropout regulator 102. The regulated voltage VREG at the regulated voltage node 203 is based on the current provided by current generators 204 and 206 (e.g., a stack each including at least one diode coupling device) and a control loop that compares the regulated voltage VREG with a reference voltage level VREF.

[0012] During an exemplary power failure event with a duration of t GLITCH (e.g., t GLITCH = 50 ns to 100 ns), the voltage level at power node 201 drops from VDD to ground. Whenever the drain voltage of the output transistor M PASS drops below the regulation voltage V REG, the parasitic diode of the output transistor M PASS becomes forward biased and draws a relatively large reverse current I REV from the bypass capacitor C BYPASS and through one of the parasitic diodes of the source follower output stage to power node 201. As the voltage level at power node 201 drops from VDD to ground, the compensation capacitor C COMP (coupled to the gate of the output transistor M PASS) also begins to discharge via two currents: the compensation loop current I COMP,LOOP (which is a small bias current) and the reverse compensation current I COMP,REV. The reverse compensation current I COMP,REV flows from the compensation capacitor C COMP through the parasitic diode of the current generator 204 to power node 201. The compensation loop current I COMP,LOOP flows from the compensation capacitor C COMP to ground, and the bypass capacitor C BYPASS begins to discharge. The reverse compensation current I COMP,REV is large enough to fully discharge the gate capacitor during a power failure, and recharging the compensation capacitor C COMP after the power failure takes a long time, during which the load current I LOAD continues to discharge the bypass capacitor C BYPASS. Therefore, the regulated voltage V REG at the regulated voltage node 203 drops from a target regulated voltage level to ground, and a temporary low-voltage reset occurs. After the power failure, the voltage level at the power node 201 returns to VDD, and the regulated voltage V REG at the regulated voltage node 203 recovers to the target regulated voltage level. In response, the integrated circuit system coupled to the low-dropout regulator 102 restarts a startup sequence, the analog circuit 104 and the digital circuit 106 are reset, and the state of the digital circuit 106 is disrupted.

[0013] Referring to Figure 3, the power fault-tolerant regulator 302 provides a regulated voltage VREG at the regulated voltage node 303, which is robust to transient large-amplitude noise at the power node 301. The power fault-tolerant regulator 302 includes a source follower output stage (i.e., a common-drain amplifier, such as an output transistor M PASS, which is n-type in one exemplary embodiment) configured to provide the regulated voltage VREG and an associated current (e.g., 1 mA). The voltage level at the regulated voltage node 303 is based on the current provided by current generators 304 and 306 (e.g., each including a current mirror or a stacked current mirror) and a control loop including a transconductance amplifier 308, which compares the regulated voltage VREG at the regulated voltage node 303 with a reference voltage level VREF. Transconductance amplifier 308 causes current generators 304 and 306 to adjust the voltage at node 305 and the voltage at node 307 (the gate of output transistor MPASS) to adjust the level of regulation voltage VREG according to a comparison. In at least one embodiment, power fault-tolerant regulator 302 includes diode DGL, which prevents any flow of reverse current IREV through a parasitic diode in one of the source follower output stages from bypass capacitor CBYPASS to power node 301. Diode DGL is coupled in series with the drain of output transistor MPASS and has at most negligible effect on the normal operation of power fault-tolerant regulator 302.

[0014] In at least one embodiment, to reduce or eliminate excessive discharge of the bypass capacitor C BYPASS, in addition to the diode D GL, the power fault tolerance regulator 302 includes a current-limiting resistor R LIM (e.g., R LIM = 60 kΩ) that prevents the reverse compensation current I COMP from flowing through the self-compensating capacitor C COMP (e.g., C COMP = 10 pF) to the power node 301 via node 307 through the parasitic diode of the current generator 304. The current-limiting resistor R LIM is coupled in series with the gate of the output transistor M PASS to isolate the compensation capacitor C COMP from the body diode of the p-type device in the current generator 304. The current-limiting resistor R LIM limits the reverse current to a level insufficient to cause a large voltage drop across the gate of the output transistor M PASS during a power failure, but also small enough not to affect the normal operation of the power failure-tolerant regulator 302, because the current-limiting resistor R LIM is coupled in series with two opposite current generators providing a substantially large impedance (i.e., R LIM << (Z 304||Z 306)). The current-limiting resistor R LIM and the compensation capacitor C COMP have a time constant (i.e., τ = R LIM × C COMP, for example, R LIM × C COMP = 600 ns), which is greater than a specified power failure tolerance Δt GLITCH_TOL of the power failure-tolerant regulator 302 (e.g., Δt GLITCH_TOL = 100 ns for a regulation voltage lower limit of 3.5 V or 1.9 V).

[0015] In at least one embodiment, since the circuitry receiving power at the self-regulating voltage node 303 must remain functional, the bypass capacitor C BYPASS is configured such that the voltage drop caused by net charge loss (e.g., I LOAD × Δt GLITCH, where I LOAD is the useful load current and Δt GLITCH is the duration of the power failure) is insufficient to cause the regulated voltage V REG to drop below a specified lower limit. The power failure-tolerant regulator 302 prevents the regulated voltage V REG at the regulated voltage node 303 from dropping below a target minimum level during a power failure period shorter than the specified fault tolerance. Therefore, analog and digital circuits powered by the regulated voltage V REG at the regulated voltage node 303 do not reset in response to a power failure, and the digital circuits remain in their normal state during and after a power failure, providing seamless operation of the integrated circuit system even under non-ideal conditions.

[0016] Referring to Figure 4, a simplified timing diagram illustrates the voltage level at the power node VDD and the regulated voltage VREG at the regulated voltage node 303 during an exemplary power failure event. If a voltage regulator does not include a power failure protection, the regulated voltage VREG will immediately respond to the start of the power failure event by dropping from the target regulated voltage level to ground, and will remain there for a relatively long time before the regulated output voltage level returns to the target regulated voltage level, as illustrated by waveform 402. Waveform 404 corresponds to a voltage regulator containing only diode DGL. Diode DGL reduces the rate of change of the regulated voltage VREG, but the regulated voltage VREG continues to decrease after the power failure ends, which can cause the regulated voltage VREG to drop below a specified voltage limit. In an exemplary embodiment, diode DGL and current-limiting resistor RLIM are included in the power failure-tolerant regulator 302, where RLIM × CCOM > Δt GLITCH (e.g., Δt GLITCH ≤ 100 ns). In addition to diode D GL, a current-limiting resistor RLIM is included to prevent the gate capacitor from discharging, and the regulating voltage V REG immediately begins to recover to the target regulating voltage level after the power failure ends, as illustrated in waveform 406. Therefore, by including diode D GL and current-limiting resistor RLIM, and by appropriately selecting bypass capacitor C BYPASS, the regulating voltage V REG at regulating voltage node 303 is maintained within the specified range.

[0017] Although a power fault-tolerant regulator 302 is described in one embodiment of the M PASS series n-type output transistor, those skilled in the art will understand that the teachings herein can be used with a p-type output transistor and a circuit system complementary to the circuitry illustrated in FIG3. Furthermore, the teachings herein can be used with a target regulated voltage level close to or above VDD, a target regulated voltage level close to or below ground, or a target regulated voltage level between VDD, ground, or other power supply voltages. Additionally, the teachings herein can be used with voltage regulators that include other feedback control loop circuitry.

[0018] Therefore, an embodiment of a power failure-tolerant voltage regulator is disclosed. The power failure-tolerant regulator 302 uses a small internal filter capacitor and a small internal current-limiting resistor to maintain the regulated voltage VREG at a level sufficient to sustain the digital circuitry state during a transient (i.e., relatively short) power outage at power node 301. The power failure-tolerant regulator 302 achieves regulation without requiring a relatively large external capacitor and without increasing current consumption in a non-ideal situation. In the event of a power failure of a specified duration, an embodiment of the power failure-tolerant voltage regulator will maintain sufficient power for both analog and digital circuits. Compared to a conventional voltage regulator, an embodiment of the power failure-tolerant voltage regulator requires no large external capacitor and does not increase power consumption.

[0019] The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. Unless otherwise expressly stated herein, the terms "first," "second," "third," etc., as used in the claims are used to distinguish different items within the claims and do not otherwise indicate or imply any temporal order, position, or quality. Variations and modifications to the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope of the invention as set forth in the following claims.

[0020] 102: Low voltage drop regulator 104: Analog Circuits 106: Digital Circuits 201: Power Node 203: Adjusting the voltage node 204: Current Generator 206: Current Generator 301: Power Node 302: Power Fault Tolerant Regulator 303: Adjusting voltage node 304: Current Generator 305: Node 306: Current Generator 307: Node 308: Transconductance Amplifier 402: Waveform 404: Waveform 406: Waveform C BYPASS: Bypass capacitor C COMP: Compensation capacitor C COMP: Compensation capacitor D GL: Diode I COMP,LOOP: Compensation loop current I COMP,REV: Reverse compensation current I LOAD: Load current I REV: Reverse current M PASS: Output transistor M PASS: Output transistor R LIM: Current-limiting resistor VDD: Voltage level V REF: Reference voltage level V REG: Adjust voltage

Claims

1. A power fault-tolerant voltage regulator, comprising: One voltage adjustment node; An output transistor having a source terminal, a gate terminal, and a drain terminal, the source terminal being coupled to the regulating voltage node; a first current generator coupled between a first node and a first power node; a second current generator coupled between the first node and a second power node; a feedback circuit coupled to the first and second current generators and configured to adjust a voltage at the first node based on a reference voltage and a voltage level at the regulating voltage node; a diode coupled between the drain terminal and the first power node; and a resistor coupled between the gate terminal and the first node, the power fault-tolerant voltage regulator maintaining the voltage level at the regulating voltage node above a predetermined voltage level during a power voltage fault spanning the first and second power nodes, the fault having a duration less than or equal to a target fault tolerance of the power fault-tolerant voltage regulator.

2. The power failure fault-tolerant voltage regulator of claim 1 further includes a capacitor coupled between the regulating voltage node and the second power node, the capacitor having a capacitance that causes a voltage drop caused by the current delivered to a load during the fault to be insufficient to reduce the voltage level to a level below a predetermined lower limit.

3. The power fault tolerance voltage regulator of claim 1, further comprising a compensation capacitor coupled to the gate terminal, the resistor and the compensation capacitor having a time constant that is within and greater than the target fault tolerance of the power fault tolerance voltage regulator.

4. The power fault tolerance voltage regulator as claimed in claim 3, wherein the resistor has a first resistance R, the compensation capacitor has a first capacitance C, the target fault tolerance coefficient of the power fault tolerance voltage regulator is tGLITCH, and R×C>tGLITCH.

5. The power failure fault-tolerant voltage regulator as requested in item 4, wherein the first current generator and the second current generator are configured as a parallel impedance and the first resistance is less than the parallel impedance.

6. The power failure fault-tolerant voltage regulator as described in claim 4, wherein the first current generator and the second current generator are configured as a parallel impedance and the first resistance is at least one order of magnitude smaller than the parallel impedance.

7. The power failure fault-tolerant voltage regulator of claim 1, wherein the first current generator includes a first superimposed current mirror coupled between the first node and the first power node, and the second current generator includes a second superimposed current mirror coupled between the first node and the second power node.

8. The power failure fault-tolerant voltage regulator of claim 1, wherein the source terminal is connected to the regulating voltage node, the first current generator is connected to the first node, the second current generator is connected to the first node, and the resistor is connected to the first node.

9. A method for generating a power supply fault-tolerant reference voltage, the method comprising: A first current is supplied from a first power node to a first node; A second current is injected from the first node into the second power node; using the first current and the second current and based on a reference voltage and an output voltage level at a regulating voltage node, a voltage at the first node is adjusted via a feedback circuit, the regulating voltage node being coupled to a source terminal of an output transistor; the output voltage level is generated at the regulating voltage node based on the voltage at the first node; and during a power voltage fault across the first and second power nodes, a resistor and a diode coupled between a drain terminal of the output transistor and the first power node are used to prevent a reverse current from flowing from the regulating voltage node to the first power node and to prevent a current from flowing from the first node to the first power node, thereby maintaining the output voltage level at the regulating voltage node above a predetermined voltage level during the power voltage fault across the first and second power nodes, the fault having a duration less than or equal to a target power fault tolerance, the resistor being coupled between the gate terminal of the output transistor and the first node.

10. The method of claim 9, further comprising providing a first current such that during the fault, a voltage drop caused by a second current supplied to a load is insufficient to reduce the output voltage level to a level below a predetermined lower limit.

11. The method of claim 9, further comprising: A capacitor is used to provide a pole in one loop gain of a voltage regulator; and a resistor is used during the fault to prevent current from flowing from the first node to the first power node, wherein a voltage at the first node controls the output voltage level.

12. The method of claim 11, wherein the resistor and the capacitor have a time constant that is within and greater than one of the target power supply fault tolerance ranges.

13. The method of claim 11, wherein the resistor has a first resistance R, the capacitor has a first capacitance C, and the target power supply fault tolerance coefficient tGLITCH of the voltage regulator is such that R×C>tGLITCH.

14. The method of claim 13, wherein the second current is equal to and opposite to the first current.

15. The method of claim 14, wherein the first current and the second current are generated by a circuit having a first impedance and the first resistance is at least an order of magnitude smaller than a parallel impedance of a current generator configured to generate the first current and the second current.

16. The method of claim 10, further comprising: A capacitor is used to provide a pole in one loop gain of a voltage regulator; a resistor is used to prevent current from flowing from the first node to the first power node during the fault; and a voltage at the first node is used to control the output voltage level.

17. The method of claim 16, wherein the resistor and the capacitor have a time constant that is within and greater than one of the target power supply fault tolerance ranges.

18. The method of claim 16, wherein the resistor has a first resistance R, the capacitor has a first capacitance C, and the target power supply fault tolerance coefficient tGLITCH of the voltage regulator is such that R×C>tGLITCH.

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