Image sensor

Abstract

An image sensor is provided, comprising: a semiconductor substrate having a first surface and a second surface disposed opposite to the first surface; a pixel separation structure disposed in the semiconductor substrate and defining and surrounding a pixel region; a first photoelectric conversion region and a second photoelectric conversion region disposed in the semiconductor substrate on the pixel region; a first transfer gate electrode disposed on the first surface of the semiconductor substrate and between the first photoelectric conversion region and a first floating diffusion region; a second transfer gate electrode disposed on the first surface of the semiconductor substrate and between the second photoelectric conversion region and a second floating diffusion region; a pixel gate electrode disposed on the first surface of the semiconductor substrate and overlapping one of the first photoelectric conversion region and the second photoelectric conversion region; and an impurity region disposed on the opposite side of the pixel gate electrode.

Description

Technical Field

[0001] [Cross - Reference to Related Applications]

[0002] This U.S. non - provisional application claims the priority of Korean Patent Application No. 10 - 2021 - 0057640, filed on May 4, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

[0003] The present inventive concept relates to an image sensor, and more particularly, to an image sensor having improved integration and improved electrical characteristics. Prior Art

[0004] An image sensor converts a photon image into an electrical signal. Current developments in the computer and communication industries have led to a strong demand for high - performance image sensors in various consumer electronic devices such as digital cameras, camcorders, personal communication systems (PCS), game consoles, security cameras, and medical micro - cameras.

[0005] Image sensors include charged coupled device (CCD) and complementary metal oxide semiconductor (CMOS) image sensors. CMOS image sensors have a simple operation method, and because their signal processing circuits are integrated on a single chip, the size of their products can be minimized. In addition, CMOS image sensors require relatively less power and can be used in battery - powered applications. Moreover, since the manufacturing process technology for manufacturing CMOS image sensors is compatible with CMOS process technology, the cost of manufacturing CMOS image sensors can be reduced. Accordingly, due to technological developments and the demand for high resolution, the use of CMOS image sensors has increased rapidly. Summary of the Invention

[0006] At least one embodiment of the present inventive concept provides an image sensor having improved integration and improved electrical characteristics. However, the present inventive concept is not limited thereto and may provide other useful features.

[0007] According to an embodiment of the inventive concept, an image sensor includes: a semiconductor substrate having a first surface and a second surface disposed opposite to the first surface; a pixel isolation structure disposed in the semiconductor substrate and defining a pixel region, the pixel isolation structure surrounding the pixel region in a plan view; a first photoelectric conversion region and a second photoelectric conversion region disposed in the semiconductor substrate on the pixel region; a first transfer gate electrode disposed on the first surface of the semiconductor substrate between the first photoelectric conversion region and the first floating diffusion region; a second transfer gate electrode disposed on the first surface of the semiconductor substrate between the second photoelectric conversion region and the second floating diffusion region; a pixel gate electrode disposed on the first surface of the semiconductor substrate and overlapping with one of the first photoelectric conversion region and the second photoelectric conversion region; and a plurality of impurity regions disposed on opposite side surfaces of the pixel gate electrode.

[0008] According to an embodiment of the inventive concept, an image sensor includes: a semiconductor substrate having a first surface and a second surface disposed opposite to the first surface; a pixel isolation structure disposed in the semiconductor substrate and defining a pixel region, the pixel isolation structure surrounding the pixel region in a plan view; a first photoelectric conversion region and a second photoelectric conversion region disposed in the semiconductor substrate on the pixel region and spaced apart from each other in a first direction; a device isolation layer disposed in the first surface of the semiconductor substrate, the device isolation layer defining a first active portion and a second active portion overlapping with the first photoelectric conversion region and a third active portion and a fourth active portion overlapping with the second photoelectric conversion region; a first transfer gate electrode and a second transfer gate electrode respectively disposed on the first active portion and the third active portion; and a first pixel gate electrode and a second pixel gate electrode extending in the first direction and respectively passing through the second active portion and the fourth active portion.

[0009] According to an embodiment of the inventive concept, an image sensor includes: a semiconductor substrate having a first surface and a second surface disposed opposite the first surface; a pixel isolation structure vertically extending from the first surface of the semiconductor substrate and surrounding each of a first pixel region and a second pixel region; a first photoelectric conversion region and a second photoelectric conversion region disposed in the semiconductor substrate on each of the first pixel region and the second pixel region, the first photoelectric conversion region and the second photoelectric conversion region being spaced apart from each other in a first direction; a device isolation layer disposed adjacent to the first surface of the semiconductor substrate on each of the first pixel region and the second pixel region, the device isolation layer defining a first active portion and a second active portion overlapping the first photoelectric conversion region and a third active portion and a fourth active portion overlapping the second photoelectric conversion region; a first transfer gate electrode disposed on the first active portion on each of the first pixel region and the second pixel region; a first floating diffusion region disposed in the first active portion on one side of the first transfer gate electrode; a second transfer gate electrode disposed on the third active portion on each of the first pixel region and the second pixel region; a second floating diffusion region disposed in the third active portion on one side of the second transfer gate electrode; a first pixel transistor disposed on the second active portion of the first pixel region; a second pixel transistor disposed on the fourth active portion of the first pixel region; a third pixel transistor disposed on the second active portion of the second pixel region; a fourth pixel transistor disposed on the fourth active portion of the second pixel region; a plurality of color filters disposed on the second surface of the semiconductor substrate to correspond to the first pixel region and the second pixel region; a grid structure disposed between the color filters and overlapping the pixel isolation structure; and a plurality of microlenses disposed on the color filters. Brief Description of the Drawings

[0010] FIGS. 1A and 1B illustrate circuit diagrams of unit pixels of a pixel array illustrating some embodiments according to the inventive concept. FIG. 2 illustrates a plan view of a unit pixel of an image sensor illustrating an embodiment according to the inventive concept. FIGS. 3A, 3B, and 3C illustrate cross-sectional views of an image sensor illustrating some embodiments according to the inventive concept taken along lines A-A', B-B', and C-C' of FIG. 2, respectively. FIGS. 4, 5, and 6 illustrate cross-sectional views of an image sensor illustrating some embodiments according to the inventive concept taken along line A-A' of FIG. 2. FIG. 7 illustrates a plan view of a unit pixel of an image sensor illustrating an embodiment according to the inventive concept. FIGS. 8A and 8B illustrate cross-sectional views of an image sensor illustrating some embodiments according to the inventive concept taken along lines A-A' and B-B' of FIG. 7, respectively. FIG. 9 shows a plan view of a unit pixel of an image sensor illustrating an embodiment according to the concept of the present invention. FIG. 10 shows a cross-sectional view taken along line B-B' of FIG. 9 of an image sensor illustrating an embodiment according to the concept of the present invention. FIG. 11 shows a plan view of a unit pixel of an image sensor illustrating an embodiment according to the concept of the present invention. FIGS. 12A and 12B show cross-sectional views taken along line B-B' of FIG. 11 of an image sensor illustrating some embodiments according to the concept of the present invention. FIG. 13 shows a plan view of a unit pixel of an image sensor illustrating an embodiment according to the concept of the present invention. FIG. 14 shows a plan view of a unit pixel of an image sensor illustrating an embodiment according to the concept of the present invention. FIG. 15 shows a cross-sectional view taken along line B-B' of FIG. 14 of an image sensor illustrating some embodiments according to the concept of the present invention. FIG. 16 shows a plan view of a unit pixel of an image sensor illustrating an embodiment according to the concept of the present invention. FIGS. 17 to 24 show enlarged plan views partially illustrating a pixel array of an image sensor according to some embodiments of the concept of the present invention. FIG. 25 shows a simplified plan view of an image sensor illustrating an embodiment according to the concept of the present invention. FIGS. 26 and 27 show cross-sectional views taken along line I-I' of FIG. 25 of an image sensor illustrating some embodiments according to the concept of the present invention. Embodiments

[0011] Some embodiments of an image sensor according to the concept of the present invention will now be described in detail with reference to the accompanying drawings.

[0012] FIGS. 1A and 1B show circuit diagrams of unit pixels of a pixel array of an image sensor illustrating some embodiments according to the concept of the present invention.

[0013] Referring to FIG. 1A, the unit pixel P may include a first photoelectric conversion element PD1 and a second photoelectric conversion element PD2, a first transfer transistor TX1 and a second transfer transistor TX2, and four pixel transistors.

[0014] The four pixel transistors may include a reset transistor RX, a source follower transistor SF, a selection transistor SX, and a dual conversion gain transistor DCX. Although the unit pixel P is illustrated in FIG. 1A as including four pixel transistors, the inventive concept is not limited thereto. For example, the unit pixel P may include fewer than four pixel transistors or more than four pixel transistors in other embodiments.

[0015] The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may generate and accumulate charges proportional to the intensity of incident light. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may be, for example, a photodiode, a phototransistor, a photogate, a pinned photo diode (PPD), or any combination thereof.

[0016] The first transfer transistor TX1 and the second transfer transistor TX2 may provide the charges accumulated in the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 to a charge detection node FD (or a floating diffusion region). The first transfer transistor TX1 and the second transfer transistor TX2 may be controlled by a first transfer signal and a second transfer signal. For example, the first transfer signal and the second transfer signal may be supplied to the respective gate electrodes of the transfer transistors by a control circuit of an image sensor.

[0017] The first transfer transistor TX1 and the second transfer transistor TX2 may share the charge detection node FD (or the floating diffusion region FD).

[0018] In response to the first transfer signal applied to the first transfer gate electrode TG1, the first transfer transistor TX1 may provide the charge accumulated in the first photoelectric conversion element PD1 to the charge detection node FD (or the floating diffusion region).

[0019] In response to the second transfer signal applied to the second transfer gate electrode TG2, the second transfer transistor TX2 may provide the charge accumulated in the second photoelectric conversion element PD2 to the charge detection node FD (or the floating diffusion region).

[0020] The charge detection node FD may receive and accumulate the charges generated from the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2. The source follower transistor SF may be controlled according to the amount of the photocharges accumulated in the charge detection node FD.

[0021] In response to a reset signal applied to the reset gate electrode RG, the reset transistor RX can periodically reset the charge accumulated in the charge detection node FD. For example, the reset transistor RX can have a drain terminal connected to the dual conversion gain transistor DCX or the charge detection node FD, and can also have a source terminal connected to a node receiving the pixel power supply voltage VPIX. When the reset transistor RX and the dual conversion gain transistor DCX are turned on, the pixel power supply voltage VPIX can be transferred to the charge detection node FD. Therefore, the charge accumulated in the charge detection node FD can be discharged to reset the charge detection node FD.

[0022] The dual conversion gain transistor DCX can be connected between the charge detection node FD and the reset transistor RX. In response to a dual conversion gain control signal applied to the dual conversion gain gate electrode DCG, the dual conversion gain transistor DCX can change the capacitance of the charge detection node FD to thereby change the conversion gain of the unit pixel P.

[0023] For example, when capturing an image, the pixel array can receive light at a high illumination level and a low illumination level, and the dual conversion gain transistor DCX can be turned on in the high illumination mode and turned off in the low illumination mode. The dual conversion gain transistor DCX can provide a difference in the conversion gain between the high illumination mode and the low illumination mode.

[0024] When the dual conversion gain transistor DCX is turned off, the capacitance of the charge detection node FD can correspond to the first capacitance CFD1. When the dual conversion gain transistor DCX is turned on, the capacitance of the charge detection node FD can increase to the sum of the first capacitance CFD1 and the second capacitance CFD2. For example, when the dual conversion gain transistor DCX is turned on, the capacitance of the charge detection node FD can increase to reduce the conversion gain, and when the dual conversion gain transistor DCX is turned off, the capacitance of the charge detection node FD can decrease to increase the conversion gain.

[0025] The source follower transistor SF can be a source follower buffer amplifier that generates a source-drain current proportional to the amount of charge applied from the charge detection node FD to the source follower gate electrode SFG. The source follower transistor SF can amplify the change in the potential of the charge detection node FD and can output the amplified signal to the output line VOUT via the selection transistor SX. The source follower transistor SF can have a source terminal connected to a node receiving the pixel power supply voltage VPIX and a drain terminal connected to the source terminal of the selection transistor SX.

[0026] The selection transistor SX can select each column of the unit pixel P to be read. When the selection transistor SX is turned on in response to a selection signal applied to the selection gate electrode SEL, the output line V OUT can output an electrical signal output from the drain terminal of the source follower transistor SF.

[0027] Referring to FIG. 1B, the unit pixel P may include: a first photoelectric conversion element PD1, a second photoelectric conversion element PD2, a third photoelectric conversion element PD3, and a fourth photoelectric conversion element PD4; a first transfer transistor TX1, a second transfer transistor TX2, a third transfer transistor TX3, and a fourth transfer transistor TX4; and four pixel transistors RX, a pixel transistor DCX, a pixel transistor SF, and a pixel transistor SX.

[0028] The first transfer transistor TX1, the second transfer transistor TX2, the third transfer transistor TX3, and the fourth transfer transistor TX4 may share a charge detection node FD. The first transfer transistor TX1, the second transfer transistor TX2, the third transfer transistor TX3, and the fourth transfer transistor TX4 may have respective first transfer gate electrodes TG1, second transfer gate electrodes TG2, third transfer gate electrodes TG3, and fourth transfer gate electrodes TG4 controlled by a first transfer signal, a second transfer signal, a third transfer signal, and a fourth transfer signal, respectively.

[0029] FIG. 2 shows a plan view of a unit pixel of an image sensor illustrating an embodiment according to the concept of the present invention. FIGS. 3A, 3B, and 3C show cross-sectional views of an image sensor illustrating some embodiments according to the concept of the present invention taken along lines A-A', B-B', and C-C' of FIG. 2, respectively.

[0030] Referring to FIGS. 2, 3A, 3B, and 3C, when viewed in cross-section or in plan view, an image sensor according to the concept of the present invention may include a photoelectric conversion layer 10, a readout circuit layer 20, and an optical transmission layer 30.

[0031] When viewed in cross-section, the photoelectric conversion layer 10 may be positioned between the readout circuit layer 20 and the optical transmission layer 30. The photoelectric conversion layer 10 can convert external incident light into an electrical signal. The photoelectric conversion layer 10 may include a semiconductor substrate 100, a pixel isolation structure PIS, and a first photoelectric conversion region 110a and a second photoelectric conversion region 110b.

[0032] For example, the semiconductor substrate 100 may have a first surface (or front surface) 100a and a second surface (or back surface) 100b that face each other. The semiconductor substrate 100 may be an epitaxial layer formed on a bulk silicon substrate having a first conductivity type (e.g., p-type) that is the same as the first conductivity type of the epitaxial layer, or a p-type epitaxial layer from which the bulk silicon substrate has been removed in the manufacture of an image sensor. Alternatively, the semiconductor substrate 100 may be a bulk semiconductor substrate including wells of a first conductivity type.

[0033] A pixel isolation structure PIS that defines a pixel region PR may be disposed in the semiconductor substrate 100. For example, the pixel isolation structure PIS may be located within the semiconductor substrate 100. When viewed in plan view, the pixel isolation structure PIS may surround the pixel region PR. For example, the pixel isolation structure PIS may include a first portion P1 that extends parallel along a first direction D1, a second portion P2 that extends parallel along a second direction D2 and passes through the first portion P1, and a third portion P3 that protrudes from the first portion P1 in the second direction D2. The intervals between the first portions P1 may be substantially the same as the intervals between the second portions P2. The third portions P3 may protrude toward the center of the pixel region PR and may face each other.

[0034] In an embodiment, the pixel isolation structure PIS has a top surface that is substantially coplanar or exactly coplanar with the first surface 100a of the semiconductor substrate 100. In an embodiment, the top surface of the pixel isolation structure PIS is substantially coplanar or exactly coplanar with the top surface of a device isolation layer STI to be discussed below.

[0035] In an embodiment, the pixel isolation structure PIS is formed of a dielectric material (e.g., silicon) whose refractive index is less than that of the semiconductor substrate 100. The dielectric material may include a single or multiple dielectric layers. The pixel isolation structure may be formed of, for example, a silicon oxide layer, a silicon nitride layer, an undoped polysilicon layer, air, or a combination thereof.

[0036] For example, the pixel isolation structure PIS may include a linear dielectric pattern 105, a semiconductor pattern 103, and a top cover dielectric pattern 107. The pixel isolation structure may be formed by patterning the first surface 100a and / or the second surface 100b of the semiconductor substrate 100 to form deep trenches, and then filling the deep trenches with a linear dielectric layer and a doped semiconductor layer.

[0037] The pixel isolation structure PIS can penetrate the semiconductor substrate 100. For example, the pixel isolation structure PIS can have a first length in a direction perpendicular to the surface of the semiconductor substrate 100 (or the third direction D3), and the first length can be substantially the same as the vertical thickness of the semiconductor substrate 100. In another example, the pixel isolation structure PIS can extend vertically from the first surface 100a towards the second surface 100b of the semiconductor substrate 100, and can be spaced apart from the second surface 100b of the semiconductor substrate 100. For example, although FIG. 3A shows the bottom surface of the pixel isolation structure PIS in contact with the second surface 100b, in an alternative embodiment, the height of the pixel isolation structure PIS can be reduced such that it does not contact the second surface 100b.

[0038] The pixel isolation structure PIS has a first width adjacent to the first surface 100a of the semiconductor substrate 100 and a second width adjacent to the second surface 100b of the semiconductor substrate 100. In an embodiment, the first width is greater than the second width. The pixel isolation structure PIS can have a width that gradually increases in a direction from the second surface 100b towards the first surface 100a of the semiconductor substrate 100.

[0039] The pixel isolation structure PIS can prevent the photoelectric charges generated from the light incident on the pixel region PR from randomly floating into adjacent pixel regions PR. The pixel isolation structure PIS can help prevent crosstalk between adjacent pixel regions PR.

[0040] According to an embodiment, on each pixel region PR, a first photoelectric conversion region 110a and a second photoelectric conversion region 110b can be disposed in the semiconductor substrate 100. The first photoelectric conversion region 110a and the second photoelectric conversion region 110b can convert external incident light into an electrical signal.

[0041] The first photoelectric conversion region 110a and the second photoelectric conversion region 110b can be impurity regions in which each of them is doped with an impurity having a second conductivity type (e.g., n-type) opposite to the first conductivity type of the semiconductor substrate 100. The semiconductor substrate 100 of the first conductivity type and the first photoelectric conversion region 110a and the second photoelectric conversion region 110b of the second conductivity type can form a pair of photodiodes. For example, a photodiode can be formed by a junction between the semiconductor substrate 100 of the first conductivity type and one of the first photoelectric conversion region 110a and the second photoelectric conversion region 110b of the second conductivity type. The first photoelectric conversion region 110a and the second photoelectric conversion region 110b that each form a photodiode can generate and accumulate photoelectric charges proportional to the intensity of the incident light.

[0042] On each pixel region PR, a phase difference can be provided between the electrical signals output from the first photoelectric conversion region 110a and the electrical signals output from the second photoelectric conversion region 110b. The image sensor can compare the phase differences between the electrical signals output from a pair of the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, thereby measuring the distance to the target to determine whether the target is in focus and determining the degree of defocus of the target. As a result, the focus correction can be automatically performed.

[0043] Each of the first photoelectric conversion region 110a and the second photoelectric conversion region 110b has a first width in the first direction D1 and a first length in the second direction D2. In an embodiment, the first length is greater than the first width. For example, the first length can be approximately twice the first width.

[0044] According to some embodiments, the first photoelectric conversion region 110a and the second photoelectric conversion region 110b can be spaced apart from each other in the first direction D1 across the third part P3 of the pixel isolation structure PIS. The third part P3 of the pixel isolation structure PIS can physically reflect the incident light at the edge of each pixel region PR and can thus reduce the crosstalk between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b on each pixel region PR.

[0045] The device isolation layer STI can be positioned adjacent to the first surface 100a of the semiconductor substrate 100 on each pixel region PR. The device isolation layer STI can have a bottom surface spaced apart from the first photoelectric conversion region 110a and the second photoelectric conversion region 110b.

[0046] The device isolation layer STI can be disposed in a trench formed by recessing the first surface 100a of the semiconductor substrate 100. For example, the trench can be formed in the semiconductor substrate 100 by removing a part of the semiconductor substrate 100. In an embodiment, the device isolation layer STI is formed of a dielectric material. For example, the device isolation layer STI can include a linear oxide layer and a linear nitride layer that conformally cover the surface of the trench, and can also include a fill oxide layer that fills the trench in which the linear oxide layer and the linear nitride layer are formed. In an embodiment, the device isolation layer STI has a top surface that is substantially coplanar or precisely coplanar with the first surface 100a of the semiconductor substrate 100. Additionally, the top surface of the device isolation layer STI can be substantially coplanar with the top surface of the pixel isolation structure PIS.

[0047] According to some embodiments, the device isolation layer STI may define a first active portion ACT1, a second active portion ACT2, a third active portion ACT3, and a fourth active portion ACT4 on each pixel region PR. When viewed in a plan view, the first active portion ACT1 and the second active portion ACT2 may overlap with the first photoelectric conversion region 110a, and the third active portion ACT3 and the fourth active portion ACT4 may overlap with the second photoelectric conversion region 110b.

[0048] For example, the first active portion ACT1 and the second active portion ACT2 may be spaced apart from each other across the device isolation layer STI in the second direction D2 and may have different sizes and shapes. Additionally, the third active portion ACT3 and the fourth active portion ACT4 may be spaced apart from each other across the device isolation layer STI in the second direction D2 and may have different sizes and shapes.

[0049] The third portion P3 of the pixel isolation structure PIS may be located between the first active portion ACT1 and the third active portion ACT3 and between the second active portion ACT2 and the fourth active portion ACT4.

[0050] In an embodiment, the first active portion ACT1 and the third active portion ACT3 have substantially the same size and shape or exactly the same size and shape. In some embodiments, although the first active portion ACT1 and the third active portion ACT3 are shown as each having a quadrilateral shape, the inventive concept is not limited thereto, and the first active portion ACT1 and the third active portion ACT3 may each have various polygonal shapes.

[0051] In an embodiment, the second active portion ACT2 and the fourth active portion ACT4 have substantially the same size and shape or exactly the same size and shape. For example, each of the second active portion ACT2 and the fourth active portion ACT4 may have a major axis in the second direction D2 and a minor axis in the first direction D1. In an embodiment, each of the second active portion ACT2 and the fourth active portion ACT4 has a second width W2 in the first direction D1 that is less than a first width W1 of one of the first photoelectric conversion region 110a and the second photoelectric conversion region 110b in the first direction D1. Additionally, in an embodiment, each of the second active portion ACT2 and the fourth active portion ACT4 has a second length L2 in the second direction D2 that is less than a first length L1 of one of the first photoelectric conversion region 110a and the second photoelectric conversion region 110b in the second direction D2.

[0052] The readout circuit layer 20 may be disposed on the first surface 100a of the semiconductor substrate 100. The readout circuit layer 20 may include a readout circuit connected to the photoelectric conversion layer 10. For example, the readout circuit layer 20 may include a transfer gate electrode TG1 and a transfer gate electrode TG2, and pixel transistors (e.g., the reset transistor RX, source follower transistor SF, dual conversion gain transistor DCX, and selection transistor SX shown in FIGS. 1A or 1B).

[0053] For example, the first active portion ACT1 may be provided with a first transfer gate electrode TG1 thereon and a first floating diffusion region FD1 on one side of the first transfer gate electrode TG1. The third active portion ACT3 may be provided with a second transfer gate electrode TG2 thereon and a second floating diffusion region FD2 on one side of the second transfer gate electrode TG2.

[0054] Portions of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may be positioned in a trench formed by recessing the first surface 100a of the semiconductor substrate 100, and a gate dielectric layer may be inserted between the semiconductor substrate 100 and the first transfer gate electrode TG1 and the second transfer gate electrode TG2. In some embodiments, the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may vary in shape and position differently. The first transfer gate electrode TG1 and the second transfer gate electrode TG2 may have their flat bottom surfaces on the first surface 100a of the semiconductor substrate 100. For example, the height of the first transfer gate electrode TG1 and the second transfer gate electrode TG2 shown in FIG. 3C may be reduced such that their bottom surfaces are flush with the first surface 100a. The first active portion ACT1 may have different areas on opposite sides of each of the first transfer gate electrode TG1 and the second transfer gate electrode TG2. For example, the first transfer transistor and the second transfer transistor may each have source regions and drain regions with different widths from each other.

[0055] The first floating diffusion region FD1 and the second floating diffusion region FD2 may be formed by doping impurities having a conductivity type different from that of the semiconductor substrate 100. For example, the first floating diffusion region FD1 and the second floating diffusion region FD2 may be n-type impurity regions.

[0056] According to an embodiment and as illustrated in FIG. 3B, the first pixel gate electrode PG1 may be positioned on the second active portion ACT2, and the second pixel gate electrode PG2 may be positioned on the fourth active portion ACT4. For example, the first pixel gate electrode PG1 may overlap with the first photoelectric conversion region 110a, and the second pixel gate electrode PG2 may overlap with the second photoelectric conversion region 110b.

[0057] The first impurity region SDR1 may be disposed in the second active portion ACT2 on the opposite side surface of the first pixel gate electrode PG1, and the second impurity region SDR2 may be disposed in the fourth active portion ACT4 on the opposite side surface of the second pixel gate electrode PG2.

[0058] The first impurity regions SDR1 may be spaced apart from each other in the second direction D2, and the first pixel gate electrode PG1 may be disposed between the first impurity regions SDR1. Similarly, the second impurity regions SDR2 may be spaced apart from each other in the second direction D2, and the second pixel gate electrode PG2 may be disposed between the second impurity regions SDR2.

[0059] The first pixel gate electrode PG1 and the first impurity region SDR1 may constitute one of the pixel transistors, such as the reset transistor RX, the source follower transistor SF, the dual conversion gain transistor DCX, and the selection transistor SX discussed above with reference to FIGS. 1A and 1B. Similarly, the second pixel gate electrode PG2 and the second impurity region SDR2 may constitute the other of the pixel transistors, such as the reset transistor RX, the source follower transistor SF, the dual conversion gain transistor DCX, and the selection transistor SX discussed above with reference to FIGS. 1A and 1B.

[0060] In addition, a ground impurity region GR may be disposed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. The device isolation layer STI may separate the ground impurity region GR from the first active portion ACT1, the second active portion ACT2, the third active portion ACT3, and the fourth active portion ACT4. The ground impurity region GR may be formed by doping an impurity having the same conductivity type as the conductivity type of the semiconductor substrate 100.

[0061] As illustrated in FIG. 3A, the interlayer dielectric layer 210 may be stacked on the first surface 100a of the semiconductor substrate 100 and may cover the transfer gate electrode TG1 and the transfer gate electrode TG2 and the pixel transistors RX, SF, DCX, and SX constituting the readout circuit. The interlayer dielectric layer 210 may include one or more of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0062] The interlayer dielectric layer 210 may have wiring structures 221 and 223 connected to the readout circuit therein. The wiring structures 221 and 223 may include metal wires 223 and contact plugs 221 connecting the metal wires 223 to each other.

[0063] Referring to FIGS. 3A, 3B, and 3C, the optical transmission layer 30 may be positioned on the second surface 100b of the semiconductor substrate 100. The optical transmission layer 30 may include a planarized dielectric layer 310, a grating structure 320, a protective layer 330, a color filter 340, a microlens 350, and a passivation layer 360. The optical transmission layer 30 may focus and filter external incident light, and the photoelectric conversion layer 10 may be provided with the focused and filtered light.

[0064] The planarized dielectric layer 310 may cover the second surface 100b of the semiconductor substrate 100. In an embodiment, the planarized dielectric layer 310 is formed of a transparent material and may include multiple layers. In an embodiment, the planarized dielectric layer 310 is formed of a dielectric material whose refractive index is different from that of the semiconductor substrate 100. The planarized dielectric layer 310 may include one or more of metal oxides and silicon oxides.

[0065] The grating structure 320 may be positioned on the planarized dielectric layer 310. Similar to the pixel isolation structure PIS, the grating structure 320 may have a grating or grid shape when viewed in a plan view. When viewed in a plan view, the grating structure 320 may overlap with the pixel isolation structure PIS. For example, the grating structure 320 may include a first portion extending in a first direction D1, and may also include a second portion extending in a second direction D2 and passing through the first portion. The grating structure 320 may have a width substantially the same as or less than the minimum width of the pixel isolation structure PIS.

[0066] The grating structure 320 may include one or more of a conductive pattern and a low-refraction pattern. The conductive pattern may include a metal material such as titanium, tantalum, or tungsten. In an embodiment, the low-refraction pattern is formed of a material whose refractive index is less than that of the conductive pattern. The low-refraction pattern may be formed of an organic material and may have a refractive index of about 1.1 to about 1.3. For example, the grating structure 320 may be a polymer layer including silicon dioxide nanoparticles.

[0067] The planarized dielectric layer 310 may have a protective layer 330 with a substantially uniform thickness disposed on the surface thereof covering the grating structure 320. The protective layer 330 may be a single layer or multiple layers including at least one selected from, for example, aluminum oxide and silicon oxycarbide.

[0068] The color filter 340 may be formed to correspond to the pixel region PR. The color filter 340 may fill the pitch defined by the grating structure 320. Based on a unit pixel, the color filter 340 may include one of a red, green, and blue color filter or one of a magenta, cyan, and yellow color filter. Alternatively, one or some of the color filters 340 may include a white or infrared color filter.

[0069] The microlens 350 may be positioned on the color filter 340. The microlenses 350 may each have a convex shape with a certain radius of curvature. The microlenses 350 may be formed of a light-transmissive resin. The color filter 340 may have microlenses 350 disposed thereon corresponding to the pixel region PR. Alternatively, at least one of the microlenses 350 may be co-positioned on at least two pixel regions PR. For example, a single microlens 350 may overlap more than one of the pixel regions PR.

[0070] The passivation layer 360 may conformally cover the surface of the microlens 350. The passivation layer 360 may include, for example, an inorganic oxide.

[0071] An image sensor according to an embodiment of the present inventive concept will be described below, and for brevity of description, the description of technical features identical to those of the image sensor discussed with reference to FIGS. 2, 3A, 3B, and 3C will be omitted and the differences thereof will be explained.

[0072] FIGS. 4, 5, and 6 show cross-sectional views taken along line A-A' of FIG. 2 illustrating an image sensor according to some embodiments of the present inventive concept.

[0073] According to the embodiment illustrated in FIG. 4, the pixel isolation structure PIS may have a first lower width adjacent to its bottom surface near the first surface 100a of the semiconductor substrate 100, and may also have a first upper width adjacent to the second surface 100b of the semiconductor substrate 100, wherein the first upper width may be greater than the first lower width. For example, the pixel isolation structure PIS may have a width that gradually decreases in a direction from the second surface 100b toward the first surface 100a of the semiconductor substrate 100.

[0074] The pixel isolation structure PIS may have a top surface that is substantially coplanar with the second surface 100b of the semiconductor substrate 100. The pixel isolation structure PIS may have a first length in a direction (or third direction D3) perpendicular to the surface of the semiconductor substrate 100, and the first length may be substantially the same as or exactly the same as the vertical thickness of the semiconductor substrate 100.

[0075] The pixel isolation structure PIS may have a bottom surface that contacts a portion of the device isolation layer STI. Alternatively, the pixel isolation structure PIS may have a bottom surface that is vertically spaced apart from the device isolation layer STI. For example, the height of the pixel isolation structure PIS illustrated in FIG. 4 may be reduced such that it does not contact the device isolation layer STI.

[0076] The pixel isolation structure PIS may be formed by allowing a dielectric material to fill trenches recessed from the second surface 100b of the semiconductor substrate 100. In an embodiment, the pixel isolation structure PIS is formed of at least one high-k dielectric layer having a dielectric constant greater than that of a silicon oxide layer.

[0077] According to the embodiment illustrated in FIG. 5, the image sensor may include a first pixel isolation structure PIS1 and a second pixel isolation structure PIS2 that define a pixel region PR.

[0078] The first pixel isolation structure PIS1 may include features that are substantially the same as the features of the pixel isolation structure PIS discussed with reference to FIGS. 2, 3A, 3B, and 3C. For example, the first pixel isolation structure PIS1 may be disposed in the semiconductor substrate 100 and extend from the first surface 100a of the semiconductor substrate 100 in the vertical direction (or third direction D3).

[0079] The second pixel isolation structure PIS2 may be disposed in the semiconductor substrate 100 and extend from the second surface 100b of the semiconductor substrate 100 in the vertical direction (or third direction D3). The second pixel isolation structure PIS2 may be disposed in a trench recessed from the second surface 100b of the semiconductor substrate 100.

[0080] The second pixel isolation structure PIS2 may have a planar structure substantially the same as that of the first pixel isolation structure PIS1. When viewed in plan view, the second pixel isolation structure PIS2 may overlap with the first pixel isolation structure PIS1. For example, the second pixel isolation structure PIS2 may include a first portion extending in a first direction D1 (see P1 in FIG. 2), and may also include a second portion extending along a second direction D2 and intersecting the first portion P1 (see P2 in FIG. 2).

[0081] The second pixel isolation structure PIS2 may have a bottom surface between the first surface 100a and the second surface 100b of the semiconductor substrate 100. For example, the second pixel isolation structure PIS2 may be spaced apart from the first surface 100a of the semiconductor substrate 100. The second pixel isolation structure PIS2 may be in contact with the first pixel isolation structure PIS1.

[0082] The second pixel isolation structure PIS2 may have a second upper width at the second surface 100b of the semiconductor substrate 100 and a second lower width at the bottom surface of the second pixel isolation structure PIS2. The second lower width may be substantially the same as or smaller than the second upper width. In an embodiment, the second pixel isolation structure PIS2 has a width that gradually decreases in a direction from the second surface 100b toward the first surface 100a of the semiconductor substrate 100.

[0083] The second pixel isolation structure PIS2 may have a second length in a vertical direction (or a third direction D3), and the second length may be the same as or different from the first length of the first pixel isolation structure PIS1. For example, the second length of the second pixel isolation structure PIS2 may be substantially the same as the first length of the first pixel isolation structure PIS1.

[0084] In an embodiment, the second pixel isolation structure PIS2 is formed of at least one high-k dielectric layer having a dielectric constant greater than that of a silicon oxide layer.

[0085] According to the embodiment illustrated in FIG. 6, as discussed above with reference to FIG. 2, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may be located on the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, respectively. Each of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may be disposed in a trench formed by recessing the first surface 100a of the semiconductor substrate 100. For example, each of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may have a bottom surface at a horizontal height lower than the horizontal height of the first surface 100a of the semiconductor substrate 100. The bottom surfaces of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may be positioned at substantially the same or exactly the same horizontal height as the bottom surfaces of the first transfer gate electrode TG1 and the second transfer gate electrode TG2.

[0086] Since the first pixel gate electrode PG1 and the second pixel gate electrode PG2 are partially recessed into the semiconductor substrate 100, even when the area of the pixel region PR is reduced, the pixel transistor can reliably obtain an effective channel length in the second direction D2. For example, even if the pixel region PR has a reduced area, it is possible to optimize the electrical characteristics of the pixel transistor.

[0087] In some embodiments, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may have the same shape, but the inventive concept is not limited thereto. The same shape of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may be changed based on the function of the pixel transistor. For example, on each pixel region PR, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may have different shapes from each other. For example, the first pixel gate electrode PG1 may be a planar gate electrode, and the second pixel gate electrode PG2 may be a recessed gate electrode.

[0088] FIG. 7 shows a plan view of a unit pixel of an image sensor illustrating an embodiment according to the inventive concept. FIGS. 8A and 8B show cross-sectional views of the image sensor illustrating an embodiment according to the inventive concept taken along line A-A' and line B-B' of FIG. 7, respectively.

[0089] According to some embodiments, a fin-type transistor (e.g., FinFET) including a fin-type channel may be used as each of the pixel transistor, or the reset transistor RX, source follower transistor SF, dual conversion gain transistor DCX, and selection transistor SX discussed above with reference to FIGS. 1A and 1B.

[0090] For example, referring to FIGS. 7, 8A, and 8B, the semiconductor substrate 100 may include pixel regions PR defined by a pixel isolation structure PIS, and on each pixel region PR, a first photoelectric conversion region 110a and a second photoelectric conversion region 110b may be disposed in the semiconductor substrate 100.

[0091] The device isolation layer STI may be disposed adjacent to the first surface 100a of the semiconductor substrate 100 on each pixel region PR, and may define a first active portion ACT1 and a third active portion ACT3 spaced apart from each other in a first direction D1.

[0092] The first fin active pattern FP1 and the second fin active pattern FP2 may be located on the first surface 100a of the semiconductor substrate 100, and may overlap with the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, respectively. The first fin active pattern FP1 and the second fin active pattern FP2 may each have a strip shape and a major axis in a second direction D2. The first fin active pattern FP1 may be spaced apart from the first active portion ACT1 in the second direction D2, and the second fin active pattern FP2 may be spaced apart from the third active portion ACT3 in the second direction D2.

[0093] The first fin active pattern FP1 and the second fin active pattern FP2 may include a semiconductor material, such as silicon, germanium, or silicon-germanium. The first fin active pattern FP1 and the second fin active pattern FP2 may be epitaxial layers grown from the semiconductor substrate 100. Alternatively, the first fin active pattern FP1 and the second fin active pattern FP2 may be portions of the semiconductor substrate 100 formed by patterning the semiconductor substrate 100.

[0094] The first fin active pattern FP1 may include a first impurity region SDR1 spaced apart from each other in the second direction D2 and a first channel region between the first impurity regions SDR1. The first pixel gate electrode PG1 may be disposed to extend in the first direction D1 across the first channel region of the first fin active pattern FP1.

[0095] The second fin active pattern FP2 may include a second impurity region SDR2 spaced apart from each other in the second direction D2 and a second channel region between the second impurity regions SDR2. The second pixel gate electrode PG2 may be disposed to extend in the first direction D1 across the second channel region of the second fin active pattern FP2.

[0096] The first pixel gate electrode PG1 may surround the opposite sidewalls and the top surface of the first fin active pattern FP1, and the second pixel gate electrode PG2 may surround the opposite sidewalls and the top surface of the second fin active pattern FP2. The gate dielectric layer may be inserted between each of the first pixel gate electrode PG1 and the second pixel gate electrode PG2 and each of the first fin active pattern FP1 and the second fin active pattern FP2.

[0097] Due to the arrangement of the first fin active pattern FP1 and the second fin active pattern FP2 as discussed above, the pixel transistor can reliably obtain its effective channel width in the first direction D1 and its effective channel length in the second direction D2. Therefore, even if the pixel region PR has a reduced area, it is possible to optimize the electrical characteristics of the pixel transistor.

[0098] FIG. 9 shows a plan view of a unit pixel of an image sensor illustrating an embodiment according to the inventive concept. FIG. 10 shows a cross-sectional view of the image sensor taken along line B-B' of FIG. 9 illustrating an embodiment according to the inventive concept.

[0099] Referring to FIGS. 9 and 10, the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may be disposed on each pixel region PR, and the pixel transistor may be disposed on the first photoelectric conversion region 110a or the second photoelectric conversion region 110b. For example, the second active portion ACT2 and the first pixel gate electrode PG1 extending across the second active portion ACT2 may overlap with one of the first photoelectric conversion region 110a and the second photoelectric conversion region 110b.

[0100] FIG. 11 shows a plan view of a unit pixel of an image sensor illustrating an embodiment according to the inventive concept. FIGS. 12A and 12B show cross-sectional views of the image sensor taken along line B-B' of FIG. 11 illustrating an embodiment according to the inventive concept.

[0101] Referring to FIGS. 11 and 12A, the pixel isolation structure PIS defining the pixel region PR may include a first portion P1 extending in a first direction D1 and a second portion P2 extending in a second direction D2 and passing through the first portion P1. In an embodiment, the pixel isolation structure PIS does not include any protruding portions. For example, as shown in FIG. 12A, on each pixel region PR, a portion of the semiconductor substrate 100 may be present between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. Alternatively, referring to FIG. 12B, an isolation impurity region 110p may be disposed between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. The isolation impurity region 110p may be formed by implanting impurity ions having the same conductivity type (e.g., p-type) as that of the semiconductor substrate 100 into the semiconductor substrate 100. The isolation impurity region 110p may use a potential barrier to divide incident light into two or more light beams provided to the first photoelectric conversion region 110a and the second photoelectric conversion region 110b.

[0102] FIG. 13 shows a plan view of a unit pixel of an image sensor illustrating an embodiment according to the concept of the present invention.

[0103] According to the embodiment shown in FIG. 13, the pixel isolation structure PIS defining the pixel region PR may include: a first portion P1 extending in a first direction D1; a second portion P2 extending in a second direction D2 and intersecting the first portion P1; and a third portion P3 extending parallel to the second portion P2 and intersecting the pixel region PR between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. The third portion P3 may be connected to the first portion P1. On each pixel region PR, the third portion P3 of the pixel isolation structure PIS may allow the first photoelectric conversion region 110a and the second photoelectric conversion region 110b to be completely separated from each other in the first direction D1.

[0104] FIG. 14 shows a plan view of a unit pixel of an image sensor illustrating an embodiment according to the concept of the present invention. FIG. 15 shows a cross-sectional view of the image sensor taken along line B-B' of FIG. 14 illustrating an embodiment according to the concept of the present invention.

[0105] Referring to FIGS. 14 and 15, as discussed above, on each pixel region PR, the device isolation layer STI may define a first active portion ACT1, a second active portion ACT2, a third active portion ACT3, and a fourth active portion ACT4. The first active portion ACT1 and the second active portion ACT2 may overlap with the first photoelectric conversion region 110a, and the third active portion ACT3 and the fourth active portion ACT4 may overlap with the second photoelectric conversion region 110b.

[0106] According to an embodiment, each of the second active part ACT2 and the fourth active part ACT4 may have a major axis in a first direction D1 and a minor axis in a second direction D2. For example, each of the second active part ACT2 and the fourth active part ACT4 may have a second length L2 in the first direction D1 that is less than a first width W1 of the first photoelectric conversion region 110a or the second photoelectric conversion region 110b, and may also have a second width W2 in the second direction D2 that is less than the second length L2.

[0107] The first impurity regions SDR1 may be disposed spaced apart from each other in the first direction D1 in the second active part ACT2. The first pixel gate electrode PG1 may extend in the second direction D2 and pass through the second active part ACT2 between the first impurity regions SDR1.

[0108] The second impurity regions SDR2 may be disposed spaced apart from each other in the first direction D1 in the fourth active part ACT4. The second pixel gate electrode PG2 may extend in the second direction D2 and pass through the fourth active part ACT4 between the second impurity regions SDR2.

[0109] FIG. 16 shows a plan view of a unit pixel of an image sensor illustrating an embodiment according to the concept of the present invention.

[0110] According to the embodiment illustrated in FIG. 16, as discussed above, on each pixel region PR, the device isolation layer STI may define a first active part ACT1, a second active part ACT2, a third active part ACT3, and a fourth active part ACT4, and the second active part ACT2 and the fourth active part ACT4 may each have a polygonal shape.

[0111] For example, each of the second active part ACT2 and the fourth active part ACT4 may include a first part extending in the first direction D1, and may also include a second part intersecting the first part and extending in the second direction D2. The second active part ACT2 and the fourth active part ACT4 may overlap the first photoelectric conversion region 110a and the second photoelectric conversion region 110b, respectively. For example, the second active part ACT2 and the fourth active part ACT4 may be arranged mirror-symmetrically to each other.

[0112] The first pixel gate electrode PG1 may be positioned between a first portion and a second portion of the second active part ACT2. One of the first impurity regions SDR1 may be positioned adjacent to the first pixel gate electrode PG1 in a first direction D1, and the other of the first impurity regions SDR1 may be positioned adjacent to the first pixel gate electrode PG1 in a second direction D2.

[0113] Similarly, the second pixel gate electrode PG2 may be positioned between a first portion and a second portion of the fourth active part ACT4. One of the second impurity regions SDR2 may be positioned adjacent to the second pixel gate electrode PG2 in the first direction D1, and the other of the second impurity regions SDR2 may be positioned adjacent to the second pixel gate electrode PG2 in the second direction D2.

[0114] Figures 17 to 24 show enlarged plan views of a pixel array of an image sensor partially illustrating some embodiments according to the concepts of the present invention. For the sake of brevity of description, the technical features that are the same as those of the embodiments discussed above with reference to Figures 2 to 16 may be omitted.

[0115] According to the embodiment illustrated in Figure 17, the semiconductor substrate 100 may include a plurality of pixel regions PR defined by a pixel isolation structure PIS. The plurality of pixel regions PR may be arranged in a matrix shape along a first direction D1 and a second direction D2 that intersect each other.

[0116] For example, the plurality of pixel regions PR may include a first pixel region PR1, a second pixel region PR2, a third pixel region PR3, and a fourth pixel region PR4. The first pixel region PR1 and the second pixel region PR2 may be adjacent to each other in the first direction D1, and the first pixel region PR1 and the third pixel region PR3 may be adjacent to each other in the second direction D2. The second pixel region PR2 and the fourth pixel region PR4 may be adjacent to each other in the second direction D2, and the second pixel region PR2 and the third pixel region PR3 may be adjacent to each other in a diagonal direction.

[0117] When viewed in a plan view, each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4 may be surrounded by a pixel isolation structure PIS. Each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4 may be defined by a pair of first portions P1 extending in a first direction D1 and a pair of second portions P2 extending in a second direction D2. Additionally, the pixel isolation structure PIS may include a pair of third portions P3 on each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4. The third portion P3 may protrude from the first portion P1 in the second direction D2.

[0118] According to some embodiments, as discussed above with reference to FIGS. 2 and 3A to 3C, the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may be provided to each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4. On each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4, the third portion P3 of the pixel isolation structure PIS may be positioned between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b.

[0119] On each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4, the device isolation layer STI may define a first active portion ACT1 to a fourth active portion ACT4. On each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4, as discussed above, the first active portion ACT1 and the second active portion ACT2 may overlap with the first photoelectric conversion region 110a, and the third active portion ACT3 and the fourth active portion ACT4 may overlap with the second photoelectric conversion region 110b.

[0120] According to the embodiments of FIGS. 17 and 18, the first active portion ACT1 to the fourth active portion ACT4 of the third pixel region PR3 may be positioned symmetrically with respect to the first active portion ACT1 to the fourth active portion ACT4 of the first pixel region PR1 in a mirror image manner. The first active portion ACT1 to the fourth active portion ACT4 of the fourth pixel region PR4 may be positioned symmetrically with respect to the first active portion ACT1 to the fourth active portion ACT4 of the second pixel region PR2 in a mirror image manner.

[0121] For example, referring to FIG. 17, the first active portions ACT1 and the third active portions ACT3 of the first pixel region PR1 may be disposed adjacent to the first active portions ACT1 and the third active portions ACT3 of the third pixel region PR3 in the second direction D2. Additionally, the first active portions ACT1 and the third active portions ACT3 of the second pixel region PR2 may be disposed adjacent to the first active portions ACT1 and the third active portions ACT3 of the fourth pixel region PR4 in the second direction D2.

[0122] Alternatively, as shown in FIG. 18, the second active portions ACT2 and the fourth active portions ACT4 of the first pixel region PR1 may be disposed adjacent to the second active portions ACT2 and the fourth active portions ACT4 of the third pixel region PR3 in the second direction D2. Additionally, the second active portions ACT2 and the fourth active portions ACT4 of the second pixel region PR2 may be disposed adjacent to the second active portions ACT2 and the fourth active portions ACT4 of the fourth pixel region PR4 in the second direction D2.

[0123] On each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4, as discussed above, the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may be respectively positioned on the first active portions ACT1 and the third active portions ACT3.

[0124] On each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may be respectively positioned on the second active portions ACT2 and the fourth active portions ACT4. The first impurity regions SDR1 may be spaced apart from each other in the second direction D2 and positioned in the second active portions ACT2, and the second impurity regions SDR2 may be spaced apart from each other in the second direction D2 and positioned in the fourth active portions ACT4.

[0125] According to the embodiment shown in FIG. 17, the first pixel region PR1 and the third pixel region PR3 may form a first pixel group PX1, and the second pixel region PR2 and the fourth pixel region PR4 may form a second pixel group PX2.

[0126] Each of the first pixel gate electrodes PG1 and the second pixel gate electrodes PG2 on each of the first pixel region PR1 and the third pixel region PR3 can constitute one of the reset gate electrode RG, the dual conversion gain gate electrode DCG, the source follower gate electrode SFG, and the selection gate electrode SEL discussed with reference to FIG. 1A or FIG. 1B. Similarly, each of the first pixel gate electrodes PG1 and the second pixel gate electrodes PG2 on each of the second pixel region PR2 and the fourth pixel region PR4 can constitute one of the reset gate electrode RG, the dual conversion gain gate electrode DCG, the source follower gate electrode SFG, and the selection gate electrode SEL discussed with reference to FIG. 1A or FIG. 1B.

[0127] For example, the first pixel gate electrode PG1 of the first pixel region PR1 can be provided as the reset gate electrode RG discussed with reference to FIG. 1A or FIG. 1B, and the second pixel gate electrode PG2 of the first pixel region PR1 can be provided as the dual conversion gain gate electrode DCG discussed with reference to FIGS. 1A to 1B. The first pixel gate electrode PG1 of the third pixel region PR3 can be provided as the source follower gate electrode SFG discussed with reference to FIG. 1A or FIG. 1B, and the second pixel gate electrode PG2 of the third pixel region PR3 can be provided as the selection gate electrode SEL discussed with reference to FIG. 1A or FIG. 1B. Each of the first pixel gate electrodes PG1 and the second pixel gate electrodes PG2 on each of the first pixel region PR1 and the third pixel region PR3 can have various functions.

[0128] The first floating diffusion regions FD1 and the second floating diffusion regions FD2 of the first pixel region PR1 and the third pixel region PR3 can be commonly electrically connected via a conductive pattern CP. The first photoelectric conversion regions 110a and the second photoelectric conversion regions 110b of the first pixel region PR1 and the third pixel region PR3 can electrically share the reset gate electrode RG, the dual conversion gain gate electrode DCG, the source follower gate electrode SFG, and the selection gate electrode SEL.

[0129] Alternatively, one of the first pixel gate electrodes PG1 and the second pixel gate electrodes PG2 of the first pixel region PR1 and the third pixel region PR3 can be provided as the virtual gate electrode of a virtual transistor that is not electrically connected to the first photoelectric conversion region 110a and the second photoelectric conversion region 110b. For example, the first pixel region PR1 or the third pixel region PR3 can be provided with a virtual transistor instead of the dual conversion gain transistor DCX discussed with reference to FIG. 1A or FIG. 1B.

[0130] According to some embodiments, on each of the first pixel group PX1 and the second pixel group PX2, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may have their shapes varying differently as illustrated in FIGS. 3A, 6, 8A, and 8B.

[0131] For example, on the first pixel group PX1, the reset gate electrode RG and the select gate electrode SEL may be shaped similar to the recessed gate electrode illustrated in FIG. 6, and the source follower gate electrode SFG may be shaped similar to the planar gate electrode.

[0132] According to the embodiment illustrated in FIG. 19, the semiconductor substrate 100 may include a first pixel region PR1, a second pixel region PR2, a third pixel region PR3, and a fourth pixel region PR4 defined by a pixel isolation structure PIS.

[0133] According to this embodiment, on each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4, the device isolation layer STI may define a first active portion ACT1, a second active portion ACT2, and a third active portion ACT3. For example, on each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4, the first active portion ACT1 and the second active portion ACT2 may overlap with the first photoelectric conversion region 110a, and the third active portion ACT3 may overlap with the second photoelectric conversion region 110b. For example, the fourth active portion ACT4 may be omitted from this embodiment.

[0134] On each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4, the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may be respectively disposed on the first active portion ACT1 and the third active portion ACT3, and the first floating diffusion region FD1 and the second floating diffusion region FD2 may be respectively disposed on the sides of the first transfer gate electrode TG1 and the second transfer gate electrode TG2.

[0135] On each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4, the first pixel gate electrode PG1 may be disposed on the second active portion ACT2. The first impurity region SDR1 may be disposed in the second active portion ACT2 on the opposite side of the first pixel gate electrode PG1. As discussed above, the first impurity regions SDR1 may be spaced apart from each other in the second direction D2 and pass through the first pixel gate electrode PG1.

[0136] The first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4 can form a single pixel group PX. In this case, each of the first pixel gate electrodes PG1 of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4 can form one of the reset gate electrode RG, the source follower gate electrode SFG, the dual conversion gain gate electrode DCG, and the selection gate electrode SEL discussed with reference to FIG. 1A or FIG. 1B.

[0137] The first floating diffusion region FD1 and the second floating diffusion region FD2 of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4 can be commonly electrically connected to each other via a conductive pattern CP. The first photoelectric conversion region 110a and the second photoelectric conversion region 110b of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4 can electrically share the reset gate electrode RG, the dual conversion gain gate electrode DCG, the source follower gate electrode SFG, and the selection gate electrode SEL.

[0138] According to the embodiment illustrated in FIG. 20, on each of the first pixel region PR1 and the third pixel region PR3, the device isolation layer STI can define the first active portion ACT1 to the fourth active portion ACT4, and on each of the second pixel region PR2 and the fourth pixel region PR4, the device isolation layer STI can define the first active portion ACT1 to the third active portion ACT3.

[0139] On the first pixel region PR1 and the third pixel region PR3, the first active portion ACT1 to the fourth active portion ACT4 can be substantially the same as the embodiment discussed with reference to FIG. 17. For example, on each of the first pixel region PR1 and the third pixel region PR3, the first active portion ACT1 and the second active portion ACT2 can overlap with the first photoelectric conversion region 110a, and the third active portion ACT3 and the fourth active portion ACT4 can overlap with the second photoelectric conversion region 110b.

[0140] On the second pixel region PR2 and the fourth pixel region PR4, the first active portion ACT1, the second active portion ACT2, and the third active portion ACT3 may be substantially the same as the embodiments discussed with reference to FIG. 19. On each of the second pixel region PR2 and the fourth pixel region PR4, the first active portion ACT1 and the second active portion ACT2 may overlap with the first photoelectric conversion region 110a, and the third active portion ACT3 may overlap with the second photoelectric conversion region 110b.

[0141] In some embodiments, each of the first pixel region PR1 and the second pixel region PR2 may include the first active portion ACT1 to the fourth active portion ACT4, and each of the third pixel region PR3 and the fourth pixel region PR4 may include the first active portion ACT1 to the third active portion ACT3.

[0142] According to the embodiments illustrated in FIGS. 21 and 22, as discussed with reference to FIG. 17, the semiconductor substrate 100 may include a first pixel region PR1, a second pixel region PR2, a third pixel region PR3, and a fourth pixel region PR4 defined by a pixel isolation structure PIS.

[0143] According to the embodiment illustrated in FIG. 21, a plurality of sub-pixel regions SPR1, SPR2, SPR3, and SPR4 may constitute each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4. For example, four first sub-pixel regions SPR1 may constitute a single first pixel region PR1. The number of the first sub-pixel regions SPR1 may be changed, and this may be applicable to the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4.

[0144] For example, on each of the first sub-pixel region SPR1 and the fourth sub-pixel region SPR4, the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may be spaced apart from each other in the first direction D1, and on each of the second sub-pixel region SPR2 and the third sub-pixel region SPR3, the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may be spaced apart from each other in the second direction D2.

[0145] The pixel isolation structure PIS may include a third portion P3 protruding from a first portion P1 on each of the first sub-pixel region SPR1 and the fourth sub-pixel region SPR4 in the second direction D2, and may include a third portion P3 protruding from a second portion P2 on each of the second sub-pixel region SPR2 and the third sub-pixel region SPR3 in the first direction D1.

[0146] On each of the first sub-pixel region SPR1 and the fourth sub-pixel region SPR4, the second active portion ACT2 and the fourth active portion ACT4 may each have a major axis in the second direction D2, and the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may extend in the first direction D1 and pass through the second active portion ACT2 and the fourth active portion ACT4 respectively.

[0147] On each of the second sub-pixel region SPR2 and the third sub-pixel region SPR3, the second active portion ACT2 and the fourth active portion ACT4 may each have a major axis in the first direction D1, and the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may extend in the second direction D2 and pass through the second active portion ACT2 and the fourth active portion ACT4 respectively.

[0148] According to the embodiment illustrated in FIG. 22, on each of the first pixel region PR1 and the third pixel region PR3 adjacent to each other in the second direction D2, the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may be spaced apart from each other in the first direction D1.

[0149] On each of the second pixel region PR2 and the fourth pixel region PR4 adjacent to each other in the second direction D2, the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may be spaced apart from each other in the second direction D2.

[0150] The pixel isolation structure PIS may include a third portion P3 protruding from a first portion P1 on each of the first pixel region PR1 and the third pixel region PR3 in the second direction D2, and may include a third portion P3 protruding from a second portion P2 on each of the second pixel region PR2 and the fourth pixel region PR4 in the first direction D1.

[0151] On the first pixel region PR1 and the third pixel region PR3, the second active portion ACT2 and the fourth active portion ACT4 may each have a major axis in the second direction D2, and the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may extend in the first direction D1 and pass through the second active portion ACT2 and the fourth active portion ACT4 respectively.

[0152] On each of the second pixel region PR2 and the fourth pixel region PR4, the second active part ACT2 and the fourth active part ACT4 may each have a major axis in the first direction D1, and the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may extend in the second direction D2 and pass through the second active part ACT2 and the fourth active part ACT4 respectively.

[0153] According to the embodiment illustrated in FIG. 23, on each of the first pixel region PR1, the second pixel region PR2, the third pixel region PR3, and the fourth pixel region PR4, the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may be spaced apart from each other in the first direction D1.

[0154] The pixel isolation structure PIS may include a third portion P3 protruding from a first portion P1 on each of the first pixel region PR1 and the fourth pixel region PR4 in the second direction D2, and may be omitted between the first photoelectric conversion region 110a and the second photoelectric conversion region 110b on each of the second pixel region PR2 and the third pixel region PR3.

[0155] According to the embodiment illustrated in FIG. 24, on each of the first pixel region PR1 and the third pixel region PR3 adjacent to each other in the second direction D2, the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may be spaced apart from each other in the first direction D1.

[0156] On each of the second pixel region PR2 and the fourth pixel region PR4 adjacent to each other in the second direction D2, the first photoelectric conversion region 110a and the second photoelectric conversion region 110b may be spaced apart from each other in the second direction D2.

[0157] On each of the first pixel region PR1 and the third pixel region PR3, the second active part ACT2 and the fourth active part ACT4 may each have a major axis in the second direction D2. On each of the second pixel region PR2 and the fourth pixel region PR4, the second active part ACT2 and the fourth active part ACT4 may each have a major axis in the second direction D2.

[0158] On each of the first pixel region PR1 and the third pixel region PR3, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may extend in a first direction D1 and respectively pass through the second active portion ACT2 and the fourth active portion ACT4. On each of the second pixel region PR2 and the fourth pixel region PR4, the first pixel gate electrode PG1 and the second pixel gate electrode PG2 may extend in the first direction D1 and respectively pass through the second active portion ACT2 and the fourth active portion ACT4.

[0159] FIG. 25 shows a simplified plan view of an image sensor illustrating an embodiment according to the concept of the present invention. FIGS. 26 and 27 show cross-sectional views of an image sensor illustrating an embodiment according to the concept of the present invention taken along line I-I' of FIG. 25.

[0160] Referring to FIGS. 25 and 26, the image sensor may include a sensor chip 1 and a logic chip 2. The sensor chip 1 may include a pixel array region R1 and a pad region R2.

[0161] The pixel array region R1 may include a plurality of unit pixels P two-dimensionally arranged along a first direction D1 and a second direction D2. Each of the unit pixels P may include a photoelectric conversion element and a readout element. Each unit pixel P of the pixel array region R1 may output an electrical signal converted from incident light.

[0162] The pixel array region R1 may include a light receiving region AR and a light shielding region OB. When viewed in a plan view, the light shielding region OB may surround the light receiving region AR. For example, when viewed in a plan view, the light shielding region OB may be disposed on the upper side, lower side, left side, and right side of the light receiving region AR. The light shielding region OB may include reference pixels with little or no light incident thereon, and the amount of charge sensed in the unit pixels P of the light receiving region AR may be compared with a reference amount of charge appearing at the reference pixels, which may result in obtaining the amplitude of the electrical signal sensed in the unit pixels P.

[0163] The pad region R2 may include a plurality of conductive pads PAD for controlling the input and output of signals and photoelectric conversion signals. For easy connection to an external device, when viewed in a plan view, the pad region R2 may surround the pixel array region R1. The conductive pads PAD may allow the external device to receive the electrical signals generated from the unit pixels P.

[0164] When viewed in a vertical direction, as discussed above, the sensor chip 1 may include a photoelectric conversion layer 10 between a readout circuit layer 20 and an optical transmission layer 30.

[0165] As mentioned above, the photoelectric conversion layer 10 of the sensor chip 1 may include a semiconductor substrate 100, a pixel isolation structure PIS that defines a pixel region PR, and a photoelectric conversion region 110 disposed in the pixel region PR.

[0166] On the light receiving region AR, the sensor chip 1 may have the same technical characteristics as those of the image sensor discussed above.

[0167] The pixel isolation structure PIS may be located in the semiconductor substrate 100 on the light shielding region OB. A portion of the pixel isolation structure PIS may be electrically connected to a contact plug PLG on the light shielding region OB.

[0168] The planarization dielectric layer 310 may extend from the light receiving region AR toward the light shielding region OB and the pad region R2.

[0169] On the light shielding region OB, a light shielding pattern OBP may be located on the planarization dielectric layer 310. The light shielding pattern OBP may block light from entering the photoelectric conversion region 110 disposed on the light shielding region OB. On the reference pixel region PR of the light shielding region OB, the photoelectric conversion region 110 may output a noise signal without outputting a photoelectric signal. The noise signal may be generated by electrons generated from free heat or dark current. The light shielding pattern OBP may include a metal, such as tungsten, copper, aluminum, or any alloy thereof.

[0170] A filter layer 345 may be disposed on the light shielding pattern OBP. The filter layer 345 may block light having a wavelength different from the wavelength of the light generated from the color filter 340. For example, the filter layer 345 may block infrared rays. The filter layer 345 may include a blue filter, but the inventive concept is not limited thereto.

[0171] On the light shielding region OB, a first through-hole conductive pattern 511 may penetrate the semiconductor substrate 100 and may be electrically connected to the metal wire 223 of the readout circuit layer 20 and the wiring structure 1111 of the logic chip 2. The first through-hole conductive pattern 511 may have a first bottom surface and a second bottom surface located at different horizontal heights. A first filling pattern 521 may be disposed in the first through-hole conductive pattern 511. The first filling pattern 521 may include a material having a low refractive index and may have dielectric properties.

[0172] On the pad region R2, the conductive pad PAD can be disposed on the second surface 100b of the semiconductor substrate 100. The conductive pad PAD can be buried in the second surface 100b of the semiconductor substrate 100. For example, on the pad region R2, the conductive pad PAD can be disposed in a trench formed on the second surface 100b of the semiconductor substrate 100. The conductive pad PAD can include a metal, such as aluminum, copper, tungsten, titanium, tantalum, or any alloy thereof. In the mounting process of the image sensor, the bonding wire can be bonded to the conductive pad PAD. The conductive pad PAD can be electrically connected to an external device via the bonding wire.

[0173] In the pad region R2, the second via conductive pattern 513 can penetrate the semiconductor substrate 100 and can be electrically connected to the wiring structure 1111 of the logic chip 2. The second via conductive pattern 513 can extend to the second surface 100b of the semiconductor substrate 100 and can be electrically connected to the conductive pad PAD. A portion of the second via conductive pattern 513 can cover the bottom surface and sidewalls of the conductive pad PAD. The second filling pattern 523 can be disposed in the second via conductive pattern 513. In an embodiment, the second filling pattern 523 includes a material having a low refractive index and can have dielectric properties. On the pad region R2, the pixel isolation structure PIS can be disposed around the second via conductive pattern 513.

[0174] The logic chip 2 can include a logic semiconductor substrate 1000, logic circuits TR, a wiring structure 1111 connected to the logic circuits TR, and a logic interlayer dielectric layer 1100. The uppermost one of the logic interlayer dielectric layers 1100 can be coupled to the readout circuit layer 20 of the sensor chip 1. The logic chip 2 can be electrically connected to the sensor chip 1 via the first via conductive pattern 511 and the second via conductive pattern 513.

[0175] In some embodiments, it is interpreted that the sensor chip 1 and the logic chip 2 are electrically connected to each other via the first via conductive pattern 511 and the second via conductive pattern 513, but the inventive concept is not limited thereto.

[0176] According to the embodiment illustrated in FIG. 27, the first via conductive pattern 511 and the second via conductive pattern 513 illustrated in FIG. 26 can be omitted, and the sensor chip 1 and the logic chip 2 can be electrically connected to each other via direct contact between the bonding pads BP1 and the bonding pads BP2 disposed at the uppermost metal layers of the sensor chip 1 and the logic chip 2.

[0177] For example, the image sensor can be configured such that the sensor chip 1 can include a first bonding pad BP1 disposed at the uppermost metal layer of the readout circuit layer 20, and the logic chip 2 can include a second bonding pad BP2 disposed at the uppermost metal layer of the wiring structure 1111. The first bonding pad BP1 and the second bonding pad BP2 can include at least one selected from, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0178] Hybrid bonding technology can be used to directly and electrically connect the first bonding pad BP1 of the sensor chip 1 to the second bonding pad BP2 of the logic chip 2. In this specification, the term "hybrid bonding" can refer to a bonding method in which two components of the same type are combined at the interface therebetween. For example, when the first bonding pad BP1 and the second bonding pad BP2 are formed of copper, copper-copper bonding can be used to physically and electrically connect the first bonding pad BP1 and the second bonding pad BP2 to each other. In addition, dielectric-dielectric bonding can be used to couple the surface of the dielectric layer included in the sensor chip 1 to the surface of the dielectric layer included in the logic chip 2.

[0179] According to some embodiments of the inventive concept, the pixel transistors disposed on each pixel region can be arranged to overlap with the photoelectric conversion region, and thus the image sensor can have improved integration.

[0180] In addition, even if the unit pixel has a reduced size, the effective channel length of the pixel transistor can be reliably obtained to optimize the characteristics of the pixel transistor. Therefore, the image sensor can have improved electrical characteristics.

[0181] Although the inventive concept has been described in connection with some embodiments shown in the accompanying drawings, those of ordinary skill in the art should understand that various changes and modifications can be made without departing from the spirit and characteristics of the inventive concept. It will be obvious to those of ordinary skill in the art that various alternatives, modifications, and changes can be made without departing from the scope and spirit of the inventive concept.

[0182] 1: Sensor chip 2: Logic chip 10: Photoelectric conversion layer 20: Readout circuit layer 30: Optical transmission layer 100: Semiconductor substrate 100a: First surface / front surface 100b: Second surface / Rear surface 103: Semiconductor pattern 105: Linear dielectric pattern 107: Capping dielectric pattern 110: Photoelectric conversion region 110a: First photoelectric conversion region 110b: Second photoelectric conversion region 110p: Isolated impurity region 210: Interlayer dielectric layer 221: Wiring structure / Contact plug 223: Wiring structure / Metal wire 310: Planarization dielectric layer 320: Grating structure 330: Protection layer 340: Color filter 345: Filter layer 350: Microlens 360: Passivation layer 511: First via conductive pattern 513: Second via conductive pattern 521: First filling pattern 523: Second filling pattern 1000: Logic semiconductor substrate 1100: Logic interlayer dielectric layer 1111: Wiring structure A - A', B - B', C - C', I - I': Lines ACT1: First active part ACT2: Second active part ACT3: Third active part ACT4: Fourth active part AR: Light receiving area BP1, BP2: Bonding pads C FD1: First capacitor C FD2: Second capacitor CP: Conductive pattern D1: First direction D2: Second direction D3: Third direction DCG: Dual conversion gain gate electrode DCX: Dual conversion gain transistor / Pixel transistor FD: Charge detection node FD1: First Floating Diffusion Region FD2: Second Floating Diffusion Region FP1: First Fin Active Pattern FP2: Second Fin Active Pattern GR: Ground Impurity Region L1: First Length L2: Second Length OB: Light-Shielding Region OBP: Light-Shielding Pattern P: Unit Pixel P1: First Part P2: Second Part P3: Third Part PAD: Conductive Pad PD1: First Photoelectric Conversion Element PD2: Second Photoelectric Conversion Element PD3: Third Photoelectric Conversion Element PD4: Fourth Photoelectric Conversion Element PIS: Pixel Isolation Structure PIS1: First Pixel Isolation Structure PIS2: Second Pixel Isolation Structure PG1: First Pixel Gate Electrode PG2: Second Pixel Gate Electrode PLG: Contact Plug PR: Pixel Region PR1: First Pixel Region PR2: Second Pixel Region PR3: Third Pixel Region PR4: Fourth Pixel Region PX: Pixel Group PX1: First Pixel Group PX2: Second Pixel Group R1: Pixel Array Region R2: Pad Region RG: Reset Gate Electrode RX: Reset Transistor / Pixel Transistor SDR1: First Impurity Region SDR2: Second Impurity Region SEL: Select Gate Electrode SF: Source Follow Transistor / Pixel Transistor SFG: Source Follow Gate Electrode SPR1, SPR2, SPR3, SPR4: Sub-Pixel Region STI: Device isolation layer SX: Selection transistor / Pixel transistor TG1: First transfer gate electrode TG2: Second transfer gate electrode TG3: Third transfer gate electrode TG4: Fourth transfer gate electrode TR: Logic circuit TX1: First transfer transistor TX2: Second transfer transistor TX3: Third transfer transistor TX4: Fourth transfer transistor V OUT: Output line V PIX: Pixel power supply voltage W1: First width W2: Second width

Claims

1. An image sensor, comprising: A semiconductor substrate includes a first surface and a second surface disposed opposite to the first surface; A pixel separation structure is disposed in the semiconductor substrate and defines a pixel region, the pixel separation structure surrounding the pixel region in a plan view; A first photoelectric conversion region and a second photoelectric conversion region are disposed in the semiconductor substrate on the pixel region; a first transfer gate electrode is disposed on the first surface of the semiconductor substrate and between the first photoelectric conversion region and the first floating diffusion region; a second transfer gate electrode is disposed on the first surface of the semiconductor substrate and between the second photoelectric conversion region and the second floating diffusion region; a pixel gate electrode is disposed on the first surface of the semiconductor substrate and overlaps with one of the first photoelectric conversion region and the second photoelectric conversion region; an impurity region is disposed on the opposite side of the pixel gate electrode; and a microlens is disposed on the second surface of the semiconductor substrate and on the pixel region, wherein the microlens vertically overlaps with the first photoelectric conversion region and the second photoelectric conversion region, wherein the first photoelectric conversion region and the second photoelectric conversion region are spaced apart from each other in a first direction, wherein the first transfer gate electrode is spaced apart from the pixel gate electrode in a second direction, the second direction intersects the first direction, and wherein the first direction and the second direction are parallel to the first surface of the semiconductor substrate.

2. The image sensor as claimed in claim 1, wherein the impurity regions are spaced apart from each other in the second direction.

3. The image sensor of claim 1, wherein the pixel gate electrode has a bottom surface at a horizontal height below the first surface of the semiconductor substrate.

4. The image sensor as claimed in claim 1, further comprising a fin active pattern disposed on the first surface of the semiconductor substrate, wherein the pixel gate electrode surrounds the opposing sidewalls and top surface of the fin active pattern.

5. The image sensor as claimed in claim 1, wherein the pixel separation structure comprises: Multiple first parts extend in a first direction and are spaced apart from each other; Multiple second portions, passing through the first portion and extending in a second direction, the second portions being spaced apart from each other; And a plurality of third portions, each protruding from the first portion in the second direction, the third portions being opposite to each other.

6. The image sensor as claimed in claim 5, wherein the third portion is disposed in the plan view between the first photoelectric conversion region and the second photoelectric conversion region.

7. The image sensor of claim 1, wherein each of the first photoelectric conversion region and the second photoelectric conversion region has a first width in a first direction and a first length in a second direction, wherein the first length is greater than the first width.

8. An image sensor, comprising: A semiconductor substrate having a first surface and a second surface opposite to the first surface; A pixel separation structure is disposed in the semiconductor substrate and defines a pixel region, the pixel separation structure surrounding the pixel region in a plan view; A first photoelectric conversion region and a second photoelectric conversion region are disposed in the semiconductor substrate on the pixel region and spaced apart from each other in a first direction; a device isolation layer is disposed in the first surface of the semiconductor substrate, and from a plan view, the device isolation layer defines a first active portion and a second active portion overlapping with the first photoelectric conversion region, and a third active portion and a fourth active portion overlapping with the second photoelectric conversion region; a first transfer gate electrode and a second transfer gate electrode are respectively disposed on the first active portion and the third active portion; The first pixel gate electrode and the second pixel gate electrode extend in the first direction and pass through the second active portion and the fourth active portion, respectively; And a microlens disposed on the second surface of the semiconductor substrate and on the pixel region, wherein the microlens vertically overlaps with the first photoelectric conversion region and the second photoelectric conversion region, wherein the first photoelectric conversion region and the second photoelectric conversion region are spaced apart from each other in the first direction, wherein the first transfer gate electrode is spaced apart from the first pixel gate electrode in the second direction, the second direction intersects the first direction, wherein the second transfer gate electrode is spaced apart from the second pixel gate electrode in the second direction, and wherein the first direction and the second direction are parallel to the first surface of the semiconductor substrate.

9. The image sensor as claimed in claim 8, further comprising: The first impurity region is disposed in the second active portion on the opposite side of the first pixel gate electrode, and the first impurity regions are spaced apart from each other in the second direction; And a second impurity region, disposed in the fourth active portion on the opposite side of the second pixel gate electrode, the second impurity regions being spaced apart from each other in the second direction.

10. The image sensor as claimed in claim 8, wherein the pixel separation structure comprises: Multiple first portions extend in the first direction and are spaced apart from each other; Multiple second portions, passing through the first portion and extending in the second direction, are spaced apart from each other; And a plurality of third portions, each protruding from the first portion in the second direction, the third portions being opposite to each other, wherein the third portions are disposed between the first photoelectric conversion region and the second photoelectric conversion region.

11. The image sensor of claim 8, wherein each of the first photoelectric conversion region and the second photoelectric conversion region has a first width in the first direction and a first length in the second direction, the first length being greater than the first width, and each of the second active portion and the fourth active portion has a second width in the first direction and a second length in the second direction, the second width being less than the first width, and the second length being greater than the second width and less than the first length.

12. The image sensor of claim 8, wherein each of the first pixel gate electrode and the second pixel gate electrode has a bottom surface at a horizontal height below the first surface of the semiconductor substrate.

13. The image sensor of claim 12, wherein each of the first transfer gate electrode and the second transfer gate electrode has a bottom surface at a horizontal height below the horizontal height of the first surface of the semiconductor substrate, wherein the horizontal height of the bottom surface of the first transfer gate electrode and the second transfer gate electrode is substantially the same as the horizontal height of the bottom surface of the first pixel gate electrode and the second pixel gate electrode.

14. The image sensor as claimed in claim 8, further comprising: The first fin active pattern is placed on the second active part; And a second fin active pattern, disposed on the fourth active portion, wherein the first pixel gate electrode surrounds the opposite sidewalls and top surface of the first fin active pattern, and wherein the second pixel gate electrode surrounds the opposite sidewalls and top surface of the second fin active pattern.

15. An image sensor, comprising: A semiconductor substrate includes a first surface and a second surface disposed opposite to the first surface; A pixel separation structure extends vertically from the first surface of the semiconductor substrate and surrounds each of the first pixel region and the second pixel region; a first photoelectric conversion region and a second photoelectric conversion region are disposed in the semiconductor substrate on each of the first pixel region and the second pixel region, the first photoelectric conversion region and the second photoelectric conversion region being spaced apart from each other in a first direction; A device isolation layer is disposed adjacent to the first surface of the semiconductor substrate on each of the first pixel region and the second pixel region. From a plan view, the device isolation layer defines a first active portion and a second active portion overlapping the first photoelectric conversion region, and a third active portion and a fourth active portion overlapping the second photoelectric conversion region. A first transfer gate electrode is disposed on the first active portion on each of the first pixel region and the second pixel region. A first floating diffusion region is disposed in the first active portion on one side of the first transfer gate electrode. The second transfer gate electrode is disposed on the third active portion of each of the first pixel region and the second pixel region; The second floating diffusion region is disposed in the third active portion on one side of the second transfer gate electrode; The first pixel transistor is disposed on the second active portion of the first pixel region; The second pixel transistor is disposed on the fourth active portion of the first pixel region; The third pixel transistor is disposed on the second active portion of the second pixel region; The fourth pixel transistor is disposed on the fourth active portion of the second pixel region; A plurality of color filters are disposed on the second surface of the semiconductor substrate to correspond to the first pixel region and the second pixel region; a grid structure is disposed between the color filters and overlaps with the pixel separation structure; and a plurality of microlenses are disposed on the color filters, wherein the microlenses overlap vertically with the first photoelectric conversion region and the second photoelectric conversion region, wherein each of the first pixel transistor and the third pixel transistor includes a first pixel gate electrode extending in a second direction and passing through the second active portion, the second direction intersecting the first direction; each of the second pixel transistor and the fourth pixel transistor includes a second pixel gate electrode extending in the second direction and passing through the fourth active portion, wherein the first transfer gate electrode is spaced apart from the first pixel gate electrode in the second direction, wherein the second transfer gate electrode is spaced apart from the second pixel gate electrode in the second direction, and wherein the first direction and the second direction are parallel to the first surface of the semiconductor substrate.

16. The image sensor of claim 15, wherein in a plan view, the first active portion to the fourth active portion of the first pixel region is mirror-symmetric to the first active portion to the fourth active portion of the second pixel region.

17. The image sensor of claim 15 further includes a conductive pattern that electrically connects and co-connects the second floating diffusion region of the first pixel region and the second pixel region to the first floating diffusion region of the first pixel region and the second pixel region.

18. The image sensor of claim 15, wherein the pixel separation structure comprises: Multiple first portions extend in the first direction and are spaced apart from each other; Multiple second portions, passing through the first portion and extending in a second direction, the second portions being spaced apart from each other; And a plurality of third portions, each protruding from the first portion in the second direction, the third portions being opposite to each other, wherein the third portions are disposed between the first photoelectric conversion region and the second photoelectric conversion region.

Images