Semiconductor structure and method for manufacturing the same

Abstract

The semiconductor structure includes a first semiconductor device formed on a substrate and a second semiconductor device formed on a substrate. The first semiconductor device includes a first source / drain component on the substrate, a first gate structure on the substrate, a first conductive component on the first source / drain component, and a first insulating layer between the first gate structure and the first conductive component. The second semiconductor device includes a second source / drain component on the substrate, a second gate structure on the substrate, a second conductive component on the second source / drain component, and a second insulating layer between the second gate structure and the second conductive component. The width of the first conductive component is different from the width of the second conductive component, and the width of the first insulating layer is smaller than the width of the second insulating layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor manufacturing technology, and in particular to semiconductor structures and methods for forming them. Prior Technology

[0002] As the semiconductor industry introduces a new generation of integrated circuits (ICs) with higher performance and more functions, the density of components forming ICs is increasing, while the size, dimensions, and spacing between components are shrinking. The semiconductor industry continues to increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly shrinking the smallest component size, which allows more components to be integrated into a given area.

[0003] However, integrated manufacturing also makes it more difficult to adjust the characteristics of components between different devices. For example, it is difficult to compromise the parasitic resistance and / or parasitic capacitance between devices with different metal dimensions.

[0004] Therefore, there is a need in the art to provide an improved device that can solve the above problems. Summary of the Invention

[0005] A semiconductor structure is provided according to some embodiments. This semiconductor structure includes a first semiconductor device formed on a substrate and a second semiconductor device formed on the substrate. The first semiconductor device includes a first source / drain component on the substrate, a first gate structure on the substrate, a first conductive component on the first source / drain component, and a first insulating layer between the first gate structure and the first conductive component. The second semiconductor device includes a second source / drain component on the substrate, a second gate structure on the substrate, a second conductive component on the second source / drain component, and a second insulating layer between the second gate structure and the second conductive component. The width of the first conductive component is different from the width of the second conductive component, and the width of the first insulating layer is smaller than the width of the second insulating layer.

[0006] A semiconductor structure is provided according to some embodiments. This semiconductor structure includes a first semiconductor device formed over a substrate and a second semiconductor device formed over a substrate. The first semiconductor device includes a first source / drain component over the substrate, a first gate structure over the substrate, a first conductive component over the first source / drain component, and a first insulating layer between the first gate structure and the first conductive component. The second semiconductor device includes a second source / drain component over the substrate, a second gate structure over the substrate, a second conductive component over the second source / drain component, and a second insulating layer between the second gate structure and the second conductive component. The width of the first gate structure is approximately equal to the width of the second gate structure, and the width of the first insulating layer is less than the width of the second insulating layer.

[0007] A method for forming a semiconductor structure is provided according to some embodiments. This method includes forming a plurality of first dummy gate structures in a first region of a substrate and forming a plurality of second dummy gate structures in a second region of the substrate. A first gap is formed between adjacent first dummy gate structures, and a second gap is formed between adjacent second dummy gate structures, the first gap being smaller than the second gap. A spacer layer is formed over the plurality of first dummy gate structures, the plurality of second dummy gate structures, and the substrate. The spacer layer in the first region is thinned. First source / drain components are formed on the substrate between adjacent first dummy gate structures, and second source / drain components are formed on the substrate between adjacent second dummy gate structures. The plurality of first dummy gate structures are replaced with the plurality of first gate structures, and the plurality of second dummy gate structures are replaced with the plurality of second gate structures. A first conductive component is formed on the first source / drain component between adjacent first gate structures, and a second conductive component is formed on the second source / drain component between adjacent second gate structures. Simple Explanation of the Diagram

[0008] The aspects of embodiments of the present invention can be better understood through the following detailed description and accompanying drawings. It should be emphasized that, according to industry standard practice, many components are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of various components may be arbitrarily increased or decreased. Figures 1 to 13 are cross-sectional side views of various stages of manufacturing a semiconductor structure according to some embodiments. Figures 14-22 are cross-sectional side views of various stages of manufacturing another semiconductor structure according to some embodiments. Figures 23-26 are cross-sectional side views of various stages of manufacturing another semiconductor structure according to some embodiments. Figure 27 is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments. Figure 28 is a flowchart of another method for manufacturing a semiconductor structure according to some embodiments. Implementation

[0009] The following provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the description mentioning that a first component is formed on or above a second component may include embodiments in which the first and second components are in direct contact, or embodiments in which an additional component is formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in different examples of the embodiments of the present invention. This repetition is for simplification and clarity and does not represent a specific relationship between the different embodiments and / or configurations discussed.

[0010] Additionally, this document may use spatial relative terms such as "below," "under," "below," "above," "on," "top," "above," and similar terms. These spatial relative terms are used to facilitate the description of the relationship between one or more elements or components as shown in the figures. These spatial relative terms cover different orientations of the device in use or operation, as well as the orientations depicted in the figures. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatial relative adjectives used herein will also be interpreted according to the orientation after the turn.

[0011] Figures 1-13 are cross-sectional side views of various stages of manufacturing the semiconductor structure 100 according to some embodiments. The semiconductor structure 100 can be formed as various devices of electronic components. For example, the semiconductor structure 100 can be formed as a transistor, diode, image sensor, resistor, capacitor, inductor, memory cell, combination of the foregoing, and / or other suitable devices. In some embodiments, the semiconductor structure 100 can be formed as a transistor, such as a fin field-effect transistor (FinFET) or a nanostructure field-effect transistor (FET) having multiple channels surrounded by a gate electrode layer. Furthermore, in some embodiments, interconnect layers can be formed on or under the semiconductor structure 100 and are designed to connect various devices to form functional circuits. The interconnect layers can be formed from alternating layers of dielectric materials (e.g., low-dielectric-constant dielectric materials) in which conductive materials (e.g., copper) are embedded, and the formation of the conductive materials can be achieved via any suitable process (e.g., deposition, damascene, dual damascene, etc.).

[0012] As shown in Figure 1, the semiconductor structure 100 includes a substrate 106, on which a first region 102 and a second region 104 are defined. The first region 102 and the second region 104 may be spaced apart from each other by a distance "D1," which, according to this invention, can be any suitable distance. Although the first region 102 is shown as adjacent to the second region 104 along one direction (e.g., the X direction), the first region 102 may be located in different regions of the substrate 106 (e.g., in different regions along a Y direction perpendicular to the X direction). In some embodiments, the first region 102 and the second region 104 may be defined to form different components with different critical dimensions. The first region 102 and the second region 104 may be defined to form active and / or passive devices, such as transistors, capacitors, resistors, combinations thereof, or similar devices, which can be used to fulfill the structural and functional requirements of a semiconductor device. For example, the first region 102 may be used to manufacture transistors for a System-on-a-Chip (SOC) device, and the second region 104 may be used to manufacture transistors for an HPC device.

[0013] The substrate 106 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar substrate, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 106 may be a wafer, such as a silicon wafer. In some embodiments, the semiconductor material of the substrate 106 may comprise silicon, germanium, compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. In some embodiments, suitable wells may be formed in the substrate 106. For example, a p-type well may be formed in a first region 102 of the substrate 106, and an n-type well may be formed in a second region 104 of the substrate 106.

[0014] A dummy gate dielectric layer 108 and a dummy gate electrode layer 110 are formed on a substrate 106. A hard mask 112 is formed on the dummy gate electrode layer 110, and the hard mask 112 is patterned according to the width of the dummy gate electrode and the gap formed between adjacent dummy gate electrodes. The dummy gate dielectric layer 108 can be formed by thermal oxidation, chemical vapor deposition (CVD), sputtering, or any other suitable method for forming a gate dielectric layer. In some embodiments, the dummy gate dielectric layer 108 may comprise a dielectric material having a high dielectric constant (k value) of, for example, greater than 3.9. The dummy gate dielectric layer 108 may comprise silicon nitride, oxynitride, metal oxide, such as HfO2, HfZrOx, HfSiOx, HfTiOx, HfAlOx, similar materials, or combinations thereof and multilayer structures. A dummy gate electrode layer 110 may be formed over the dummy gate dielectric layer 108 and may contain a conductive material selected from polysilicon, poly-SiGe, metal nitrides, metal silicates, metal oxides, and metals. In some embodiments, amorphous silicon is deposited and recrystallized to produce polysilicon. The deposition of the dummy gate electrode layer 110 may be performed by physical vapor deposition (PVD), chemical vapor deposition, sputtering deposition, or other techniques known in the art and used for depositing conductive materials. After deposition, the top surface of the dummy gate electrode layer 110 may have a non-planar top surface and may be planarized, for example, by a chemical mechanical polishing (CMP) process before the dummy gate electrode layer 110 is patterned. A hard mask 112 is formed over the dummy gate electrode layer 110. The hard mask 112 can be made of SiN, SiON, SiO2, similar materials, or combinations thereof. The hard mask 112 is then patterned, as shown in Figure 1. For example, the hard mask 112 in the first region 102 is patterned based on a predetermined dummy gate structure width W2 and a gap W1 between adjacent dummy gate structures, and then the hard mask 112 in the second region 112 is patterned based on a predetermined dummy gate structure width W4 and a gap W3 between adjacent dummy gate structures.

[0015] As shown in Figure 2, the dummy gate dielectric layer 108 and the dummy gate electrode layer 110 are patterned to form a first dummy gate structure 114 in a first region 102 and a second dummy gate structure 116 in a second region 104, respectively. The dummy gate patterning process can be achieved by using a hard mask 112 as a mask to etch the dummy gate dielectric layer 108 and the dummy gate electrode layer 110 to form the first dummy gate structure 114 and the second dummy gate structure 116. The first dummy gate structure 114 has a width W2, and the gap between adjacent first dummy gate structures 114 is W1. The second dummy gate structure 116 has a width W4, and the gap between adjacent second dummy gate structures 116 is W3. In some embodiments, W2 is approximately equal to W4, and W1 is less than W3.

[0016] As shown in Figure 3, a spacer layer 118 can be conformally formed on the first dummy gate structure 114, the second dummy gate structure 116, and the substrate 106. The spacer layer 118 can be formed by blanket deposition on the first dummy gate structure 114, the second dummy gate structure 116, and the substrate 106. In some embodiments, the spacer layer 118 may comprise SiN, oxide nitride, SiC, SiON, oxides, combinations thereof, or similar materials, and the spacer layer 118 can be formed by methods for forming such layers, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), sputtering, similar methods, or combinations thereof. The spacer layer 118 formed in the first region 102 and the second region 104 can have approximately the same thickness W5.

[0017] As shown in Figure 4, a protective layer 120 is formed over the spacer layer 118 in the second region 104. In some embodiments, the protective layer 120 may be photoresist or other suitable material that can protect the spacer layer 118 during the etching process. Then, as shown in Figure 5, the spacer layer 118 is thinned. Since the spacer layer 118 in the second region 104 is covered by the protective layer 120, only the spacer layer 118 in the first region 102 is thinned. The thinning operation of the spacer layer 118 can be performed by dry etching, wet etching, or other suitable processes.

[0018] As shown in Figure 6, the protective layer 120 is removed. The spacer layer 118a in the first region 102 has a thickness W6, while the spacer layer 118b in the second region 104 has a thickness W7. W6 is less than W7. By covering or exposing the spacer layers 118 in different regions of the semiconductor structure 100 and performing a thinning operation, the thickness of the spacer layers 118 can be controlled to achieve predetermined parasitic resistances and / or parasitic capacitances of different devices formed on different regions of the semiconductor structure 100.

[0019] As shown in Figure 7, spacer layers 118a and 118b are patterned, for example, by anisotropic etching, to remove spacer layers 118a and 118b from horizontal surfaces (e.g., the top surfaces of the first dummy gate structure 114 and the second dummy gate structure 116, and the top surface of the substrate 106). Then, a first source / drain component 122 and a second source / drain component 124 are formed in the substrate 106 on either side of the first dummy gate structure 114 and the second dummy gate structure 116, respectively. The formation of the first source / drain component 122 and the second source / drain component 124 can be achieved by performing a implantation process to implant suitable dopants in the substrate 106. In some embodiments, the formation of the first source / drain component 122 and the second source / drain component 124 can be achieved by forming grooves in the substrate 106 and epitaxially growing material in the grooves.

[0020] The doping of the first source / drain component 122 and the second source / drain component 124 can be achieved by the implantation method described above or by in-situ doping during material growth. In some embodiments, the first source / drain component 122 and the second source / drain component 124 can comprise any suitable material, such as that suitable for n-type and / or p-type field-effect transistors. For example, in an n-type configuration, if the substrate 106 is silicon, the first source / drain component 122 and the second source / drain component 124 can comprise silicon, SiC, SiCP, SiP, or similar materials. As another example, in an n-type configuration, if the substrate 106 is silicon, the first source / drain component 122 and the second source / drain component 124 can comprise SiGe, SiGeB, Ge, GeSn, or similar materials. The first source / drain component 122 and the second source / drain component 124 may have a surface that protrudes above the top surface of the substrate 106 and may have facets.

[0021] In some embodiments, the first source / drain component 122 and the second source / drain component 124, as well as the subsequently formed gate structure, can be formed as a transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). In some embodiments, the MOSFET can be configured as a P-type field-effect transistor (PMOS) or an N-type field-effect transistor (NMOS). In a PMOS configuration, the substrate 106 can be doped with n-type dopant and the first source / drain component 122 and the second source / drain component 124 can be doped with p-type dopant. In an NMOS configuration, the substrate 106 can be doped with p-type dopant and the first source / drain component 122 and the second source / drain component 124 can be doped with n-type dopant.

[0022] As shown in Figure 8, a contact etching stop layer (CESL) 126 is compliantly formed over the first dummy gate structure 114, the second dummy gate structure 116, spacer layers 118a and 118b, the first source / drain component 122, and the second source / drain component 124. The CESL includes contact etch stop layer 126a and contact etch stop layer 126b. The CESL 126a in the first region 102 and the CESL 126b in the second region 104 can be formed using the same process. In some embodiments, the CESL 126a in the first region 102 and the CESL 126b in the second region 104 can have approximately the same thickness W8. In some embodiments, the contact etch stop layer 126a and the contact etch stop layer 126b may be silicon nitride, silicon carbide, silicon oxide, a low dielectric constant dielectric, such as a carbon-doped oxide, an extremely low dielectric constant dielectric, such as silicon dioxide doped with porous carbon, similar materials, or a combination thereof, and may be deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating dielectric process, similar methods, or a combination thereof.

[0023] As shown in Figure 9, an interlayer dielectric (ILD) 128 is deposited over the contact etch stop layer 126 (including contact etch stop layer 126a and contact etch stop layer 126b) and a planarization process is performed to remove the top of the interlayer dielectric 128 to form interlayer dielectric 128a in the first region 102 and interlayer dielectric 128b in the second region 104. In some embodiments, the interlayer dielectric 128 (interlayer dielectric 128a and interlayer dielectric 128b) is a flowable film formed by flowable chemical vapor deposition (CVD). In some embodiments, the interlayer dielectric 128 is formed of oxides, such as silicon oxide, phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), low dielectric constant dielectrics, such as carbon-doped oxides, very low dielectric constant dielectrics, such as carbon-doped porous silicon dioxide, polymers, such as polyimide, similar materials, or combinations thereof. The low dielectric constant dielectric material may have a dielectric constant value below 3.9. The interlayer dielectric 128 can be deposited by any suitable method, such as chemical vapor deposition, atomic layer deposition, spin-on-dielectric (SOD) processes, similar methods, or combinations thereof. A planarization process, such as chemical mechanical polishing, can be performed to make the top surface of the interlayer dielectric 128 flush with the top surfaces of the first dummy gate structure 114 and the second dummy gate structure 116, as well as the top surfaces of the contact etch stop layers 126a and 126b. In some embodiments, the chemical mechanical polishing process can also remove the hard mask 112.

[0024] As shown in Figure 10, the first dummy gate structure 114 and the second dummy gate structure 116 are removed. The dummy gate dielectric layer 108 and the dummy gate electrode layer 110 can be removed in one or more etching operations, thereby forming grooves 114a and 116a. Each groove 114a or 116a exposes a channel region of its respective field-effect transistor. Each channel region is disposed between adjacent first source / drain components 122 and second source / drain components 124. During removal, when etching the first dummy gate structure 114 and the second dummy gate structure 116, the dummy gate dielectric layer 108 can be used as an etch stop layer. The dummy gate dielectric layer 108 can then be removed after the dummy gate electrode layer 110 is removed. Grooves 114a and 116a are defined by the exposed surfaces of the substrate 106 and the exposed surfaces of spacer layers 118a and 118b.

[0025] As shown in Figure 11, a first gate structure 114b and a second gate structure 116b are formed in grooves 114a and 116a. A gate dielectric layer 130 and a gate electrode 132 are formed to replace the gate. The gate dielectric layer 130 is compliantly deposited in grooves 114a and 116a, for example, on the top surface of the substrate 106 and the sidewalls of spacer layers 118a and 118b, and on the top surface of interlayer dielectrics 128a and 128b. In some embodiments, the gate dielectric layer 130 may comprise silicon oxide, silicon nitride, or a multilayer structure as described above. In other embodiments, the gate dielectric layer 130 may comprise a high dielectric constant dielectric material. In some embodiments, the gate dielectric layer 130 may have a dielectric constant greater than about 7.0 and may comprise silicates or metal oxides of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate dielectric layer 130 can be formed by any suitable technique, such as molecular-beam deposition (MBD), atomic layer deposition, plasma-assisted chemical vapor deposition, or similar methods.

[0026] Then, gate electrode 132 is deposited over gate dielectric layer 130, filling the remaining portions of grooves 114a and 116a. Gate electrode 132 can be made of a metallic material, such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or the aforementioned multilayer structure. After filling gate electrode 132, a planarization process, such as chemical mechanical polishing, can be performed to remove the top of gate dielectric layer 130 and gate electrode 132 beyond the top surfaces of interlayer dielectrics 128a and 128b.

[0027] As shown in Figure 12, a hard masking layer 134 is formed on each of the first gate structure 114b and the second gate structure 116b. In some embodiments, the first gate structure 114b and the second gate structure 116b may be etched in one or more etching operations to form a groove on the top of the first gate structure 114b and the second gate structure 116b. The hard masking layer 134 is then formed within the groove to protect the first gate structure 114b and the second gate structure 116b. The bottom surface of the groove may have a flat surface, a convex surface, a concave surface, or a combination thereof, as shown in Figure 12. The etching of the first gate structure 114b and the second gate structure 116b can be performed by any suitable process, such as a process that is selective for the materials of the gate dielectric layer 130 and the gate electrode 132.

[0028] The hard masking layer 134 can be made of metal, metal oxide, metal nitride, pure silicon, similar materials, or combinations thereof. For example, the hard masking layer 134 can be made of SiN, SiON, SiO2, similar materials, or combinations thereof. In some embodiments, the hard masking layer 134 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating dielectric processes, similar methods, or combinations thereof. A planarization process, such as chemical mechanical polishing, can be performed to make the top surfaces of the interlayer dielectrics 128a and 128b flush with the top surface of the hard masking layer 134. The hard masking layer 134 provides protection for the first gate structure 114b and the second gate structure 116b during the subsequent self-aligned contact etching process to ensure that the self-aligned contact does not form a short circuit between one of the first gate structure 114b and the second gate structure 116b and the corresponding first source / drain component 122 or second source / drain component 124.

[0029] As shown in Figure 13, interlayer dielectric 128a and interlayer dielectric 128b are removed to form openings exposing the first source / drain component 122 and the second source / drain component 124, respectively. Interlayer dielectric 128a and interlayer dielectric 128b can be removed by wet etching, dry etching, or other suitable etching processes (e.g., anisotropic dry etching).

[0030] Then, after removing interlayer dielectric 128a and interlayer dielectric 128b, a first conductive component 136a and a second conductive component 136b are formed in the opening. The first conductive component 136a contacts the first source / drain component 122, and the second conductive component 136b contacts the second source / drain component 124. In some embodiments, the first conductive component 136a and the second conductive component 136b may further include a barrier layer (not shown). The first conductive component 136a and the second conductive component 136b may be made of tungsten, copper, aluminum, or other suitable materials. The first conductive component 136a and the second conductive component 136b may be formed via a deposition process, such as electrochemical plating, physical vapor deposition, chemical vapor deposition, similar methods, or combinations thereof. In some embodiments, the first conductive component 136a and the second conductive component 136b may be planarized by a grinding process, such as a chemical mechanical polishing process.

[0031] Figure 13 illustrates the thickness relationship of each layer in the first region 102 and the second region 104 of the semiconductor structure 100. The width of the first gate structure 114b is W2, and the width of the second gate structure 116b is W4, which are defined by the widths of the first dummy gate structure 114 and the second dummy gate structure 116, as shown in Figure 2. In some embodiments, W2 is approximately equal to W4. The thickness of the contact etch stop layer 126a is W8, and the thickness of the contact etch stop layer 126b is approximately equal to the thickness of the contact etch stop layer 126a, because the contact etch stop layers 126a and 126b are formed in the same process.

[0032] Spacer layer 118a in first region 102 has a thickness W6, and spacer layer 118b in second region 104 has a thickness W7. Because spacer layer 118a has been thinned, the thickness (W6) of spacer layer 118a is less than the thickness (W7) of spacer layer 118b. The gap W1 between adjacent first gate structures 114b is less than the gap W3 between adjacent second gate structures 116b. In some embodiments, W1 is about 60% to about 90% of W3, and it can vary depending on the different devices manufactured in the first region 102 and the second region 104 on the same substrate 106. In some embodiments, W1 is about 65% to about 80% of W3.

[0033] The width of the source / drain contacts (e.g., the first conductive member 136a and the second conductive member 136b) can be defined by the gaps between adjacent gate structures and insulating layers, such as spacer layers 118a, 118b, contact etch stop layers 126a and 126b. For example, the width of the first conductive member 136a can be approximately equal to (W1 - 2 * (W6 + W8)), while the width of the second conductive member 136b can be approximately equal to (W3 - 2 * (W7 + W8)). Generally, the larger the width of the first conductive member 136a and the second conductive member 136b, the lower the parasitic contact resistance (Rp) associated with them. Higher parasitic contact resistance limits device operation and degrades performance. In some embodiments, a device formed in the first region 102 may require increased parasitic capacitance and decreased parasitic resistance between the first gate structure 114b and the first conductive component 136a, compared to the parasitic capacitance and resistance between the second gate structure 116b and the second conductive component 136b. For example, when a SOC device is formed in the first region 102 and an HPC device is formed in the second region 104, the high parasitic capacitance and low parasitic resistance between the first gate structure 114b and the first conductive component 136a may be advantageous.

[0034] By covering the spacer layer 118 in the second region and thinning the spacer layer 118 in the first region 102 to form spacer layers 118a and 118b, the thickness W6 of spacer layer 118a can be controlled to be less than the thickness W7 of spacer layer 118b. Therefore, the total thickness of the insulating layer in the first region 102 (including spacer layer 118a and contact etch stop layer 126a) can be controlled to be thinner than the total thickness of the insulating layer in the second region 104 (including spacer layer 118b and contact etch stop layer 126b). The parasitic resistance between the first gate structure 114b and the first conductive member 136a is therefore less than the parasitic resistance between the second gate structure 116b and the second conductive member 136b, and the parasitic capacitance between the first gate structure 114b and the first conductive member 136a is therefore higher than the parasitic capacitance between the second gate structure 116b and the second conductive member 136b.

[0035] Furthermore, since the first gate structure 114b and the second gate structure 116b are formed in the same process, and the first conductive component 136a and the second conductive component 136b are formed in the same process, the steps for forming different devices with different insulating layer thicknesses in different regions of the same substrate can be further simplified. When the first gate structure 114b and the second gate structure 116b include self-aligned contacts (SACs) (e.g., hard masking layer 134), devices with different critical dimensions can be formed simultaneously with insulating layers of different thicknesses. Therefore, parasitic capacitance and parasitic resistance between devices using the self-aligned contact process can be optimized, and devices with a large process window are not limited to trade-offs with devices with a small process window.

[0036] Figures 14-22 are cross-sectional side views of various stages in the fabrication of another semiconductor structure 200 according to some embodiments. Semiconductor structure 200 is similar to semiconductor structure 100, except that the thickness of the spacer layers in the first region 102 and the second region 104 is approximately the same, and the thickness of the contact etch stop layers in the first region 102 and the second region 104 are different. As shown in Figure 14, a first dummy gate structure 114 is formed in the first region 102 and a second dummy gate structure 116 is formed in the second region 104.

[0037] Spacer layers 118 (118a, 118b) are conformally formed on the first dummy gate structure 114, the second dummy gate structure 116, and the substrate 106. Then, a portion of the spacer layers 118 is patterned, for example by anisotropic etching, to remove the spacer layers 118 from horizontal surfaces (e.g., the top surfaces of the first dummy gate structure 114 and the second dummy gate structure 116, and the top surface of the substrate 106) to form spacer layer 118a in the first region 102 and spacer layer 118b in the second region 104. A first source / drain component 122 and a second source / drain component 124 are formed in the substrate 106. The process for forming the structure shown in Figure 14 can be similar to the operations shown in Figures 1-7, but in Figure 14, the spacer layer 118a in the first region 102 is not thinned compared to the spacer layer 118b in the second region 104. The thickness of spacer layer 118a is W10, and the thickness of spacer layer 118b can be approximately equal to W10.

[0038] As shown in Figure 15, a contact etch stop layer 126 is compliantly formed over the first dummy gate structure 114, the second dummy gate structure 116, spacer layers 118a and 118b, the first source / drain component 122, and the second source / drain component 124, comprising contact etch stop layers 126a and 126b. The contact etch stop layer 126a in the first region 102 and the contact etch stop layer 126b in the second region 104 are formed by the same process. In some embodiments, the contact etch stop layer 126a in the first region 102 and the contact etch stop layer 126b in the second region 104 may have approximately the same thickness.

[0039] As shown in Figure 16, a protective layer 220 is formed over the contact etch stop layer 126b in the second region 104. In some embodiments, the protective layer 220 may be photoresist or other suitable material that can protect the contact etch stop layer 126b during the etching process. Then, as shown in Figure 17, the contact etch stop layer 126a is etched. Since the contact etch stop layer 126b in the second region 104 is covered by the protective layer 220, only the contact etch stop layer 126a in the first region 102 is thinned. The thinning operation of the contact etch stop layer 126a can be performed by dry etching, wet etching, or other suitable processes.

[0040] As shown in Figure 17, the protective layer 220 is removed. The contact etch stop layer 126a in the first region 102 has a thickness W12, while the contact etch stop layer 126b in the second region 104 has a thickness W13. W12 is less than W13. By covering or exposing the contact etch stop layer 126b in different regions of the semiconductor structure 200 and performing a thinning operation, the thickness of the contact etch stop layer 126a can be controlled to achieve predetermined parasitic resistance and / or parasitic capacitance of different devices formed on different regions of the semiconductor structure 200.

[0041] Then, as shown in Figure 18, an interlayer dielectric 128 is deposited on the contact etch stop layer 126 (including contact etch stop layers 126a and 126b), and a planarization process is performed to remove the top of the interlayer dielectric 128 to form interlayer dielectric 128a in the first region 102 and interlayer dielectric 128b in the second region 104. As shown in Figure 19, the first dummy gate structure 114 and the second dummy gate structure 116 are removed. The dummy gate dielectric layer 108 and the dummy gate electrode layer 110 can be removed in one or more etch operations to form recesses 114a and 116a. In this disclosure, each recess 114a or 116a exposes a channel region of a respective field-effect transistor, in which a MOSFET is formed. Each channel region is disposed between adjacent pairs of the first source / drain component 122 and the second source / drain component 124.

[0042] As shown in Figure 20, a first gate structure 114b and a second gate structure 116b are formed in grooves 114a and 116a. A gate dielectric layer 130 and a gate electrode 132 are formed to replace the gate. The gate dielectric layer 130 is compliantly deposited in the grooves 114a and 116a, for example on the top surface of the substrate 106 and the sidewalls of the spacer layers 118a and 118b, and on the top surfaces of the interlayer dielectrics 128a and 128b. Then, the gate electrode 132 is deposited over the gate dielectric layer 130 and fills the remaining portions of the grooves 114a and 116a. After filling the gate electrode 132, a planarization process, such as a chemical mechanical polishing process, can be performed to remove the top of the gate dielectric layer 130 and the gate electrode 132 that extends beyond the top surfaces of the interlayer dielectrics 128a and 128b.

[0043] As shown in Figure 21, a hard masking layer 134 is formed on each of the first gate structure 114b and the second gate structure 116b. The hard masking layer 134 provides protection for the first gate structure 114b and the second gate structure 116b during the subsequent self-aligned contact etching process to ensure that the self-aligned contact does not form a short circuit between one of the first gate structure 114b and the second gate structure 116b and the corresponding first source / drain component 122 or second source / drain component 124.

[0044] Then, as shown in Figure 22, the interlayer dielectric 128a and interlayer dielectric 128b are replaced with the first conductive component 136a and the second conductive component 136b. Figure 22 illustrates the thickness relationship of the layers in the first region 102 and the second region 104 of the semiconductor structure 200. The first region 102 and the second region 104 are defined to form active and / or passive devices, such as transistors, capacitors, resistors, combinations thereof, and similar devices, which can be used to meet the structural and functional requirements of semiconductor devices. For example, the first region 102 can be used to manufacture transistors for SOC devices and the second region 104 can be used to manufacture transistors for HPC devices. The width of the first gate structure 114b is W2, and the width of the second gate structure 116b is W4, which is defined by the widths of the first dummy gate structure 114 and the second dummy gate structure 116, as shown in Figure 2. In some embodiments, W2 is approximately equal to W4.

[0045] Spacer layer 118a in region 102 and spacer layer 118b in region 104 are formed in the same process, therefore spacer layer 118a and spacer layer 118b have approximately the same thickness, i.e., W10. Contact etch stop layer 126a in region 102 has a thickness W11, while contact etch stop layer 126b in region 104 has a thickness W12. Since contact etch stop layer 126a has been thinned, the thickness (W11) of contact etch stop layer 126a is less than the thickness (W12) of contact etch stop layer 126b.

[0046] The gap W1 between adjacent first gate structures 114b is smaller than the gap W3 between adjacent second gate structures 116b. In some embodiments, based on different devices manufactured in the first region 102 and the second region 104 on the same substrate 106, W1 is about 60% to about 90% of W3. In some embodiments, W1 is about 65% to about 80% of W3.

[0047] The width of the source / drain contacts (e.g., the first conductive member 136a and the second conductive member 136b) can be defined by the gaps between adjacent gate structures and insulating layers, such as spacer layers 118a, 118b, contact etch stop layers 126a and 126b. For example, the width of the first conductive member 136a can be approximately equal to (W1 - 2 * (W10 + W11)), while the width of the second conductive member 136b can be approximately equal to (W3 - 2 * (W10 + W12)). In some embodiments, the device formed in the first region 102 may require increased parasitic capacitance and decreased parasitic resistance between the first gate structure 114b and the first conductive member 136a, compared to the parasitic capacitance and resistance between the second gate structure 116b and the second conductive member 136b. For example, when a SOC device is formed in the first region 102 and an HPC device is formed in the second region 104, the high parasitic capacitance and low parasitic resistance between the first gate structure 114b and the first conductive component 136a may be beneficial.

[0048] By covering the contact etch stop layer 126b in the second region and thinning the contact etch stop layer 126a in the first region 102, the thickness W11 of the contact etch stop layer 126a can be controlled to be less than the thickness W12 of the contact etch stop layer 126b. Therefore, the total thickness of the insulating layer in the first region 102 (including the spacer layer 118a and the contact etch stop layer 126a) can be controlled to be thinner than the total thickness of the insulating layer in the second region 104 (including the spacer layer 118b and the contact etch stop layer 126b). The parasitic resistance between the first gate structure 114b and the first conductive member 136a is therefore less than the parasitic resistance between the second gate structure 116b and the second conductive member 136b, and the parasitic capacitance between the first gate structure 114b and the first conductive member 136a is therefore higher than the parasitic capacitance between the second gate structure 116b and the second conductive member 136b.

[0049] When the first gate structure 114b and the second gate structure 116b include self-aligned contacts (e.g., a hard masking layer 134), devices with different critical dimensions can be formed simultaneously with insulating layers of different thicknesses. Therefore, parasitic capacitance and resistance between devices using self-aligned contact processes can be optimized, and devices with large process margins are not limited to trade-offs with devices with small process margins.

[0050] Figures 23-26 are cross-sectional side views of various stages of manufacturing another semiconductor structure 300 according to some embodiments. Semiconductor structure 300 is similar to semiconductor structure 200. The structure shown in Figure 23 is similar to the structure shown in Figure 15, and the process for forming the structure shown in Figure 23 can be similar to the operation for forming the structure shown in Figure 15. Semiconductor structure 300 can be applied in situations where, compared to the parasitic capacitance and parasitic resistance between the second gate structure 116b and the second conductive component 136b, the device formed in the first region 102 may require a reduction in the parasitic capacitance between the first gate structure 114b and the first conductive component 136a and an increase in the parasitic resistance.

[0051] The thickness of spacer layer 118a is W15, and the thickness of spacer layer 118b can be approximately equal to W15. As shown in Figure 23, a contact etch stop layer 126, including contact etch stop layer 126a and contact etch stop layer 126b, is compliantly formed over the first dummy gate structure 114, the second dummy gate structure 116, spacer layer 118a, spacer layer 118b, the first source / drain component 122, and the second source / drain component 124. The contact etch stop layer 126a in the first region 102 and the contact etch stop layer 126b in the second region 104 are formed by the same process. In some embodiments, the contact etch stop layer 126a in the first region 102 and the contact etch stop layer 126b in the second region 104 can have approximately the same thickness W16.

[0052] As shown in Figure 24, an etching operation is performed on the semiconductor structure 300 to remove portions of the contact etch stop layer 126a in the first region 102 and the contact etch stop layer 126b in the second region 104. Because the gap W1 between two adjacent first dummy gate structures 114 is smaller than the gap W3 between two adjacent second dummy gate structures 116, the etching gas can have a higher etching rate at the opening between the two adjacent second dummy gate structures 116 during dry etching. Therefore, after the etching operation, as shown in Figure 25, the contact etch stop layer 126a in the first region 102 can have a thickness W17, and the contact etch stop layer 126b in the second region 104 can have a thickness W18 less than W17.

[0053] Then, the first dummy gate structure 114 and the second dummy gate structure 116 can be replaced by the first gate structure 114b and the second gate structure 116b. The first conductive component 136a and the second conductive component 136b can be formed on the first source / drain component 122 and the second source / drain component 124, as shown in Figure 26. The width of the first gate structure 114b is W2, and the width of the second gate structure 116b is W4, which is defined by the widths of the first dummy gate structure 114 and the second dummy gate structure 116, as shown in Figure 2. In some embodiments, W2 is approximately equal to W4.

[0054] Spacer layer 118a in first region 102 and spacer layer 118b in second region 104 are formed in the same process, so spacer layer 118a and spacer layer 118b have approximately the same thickness, i.e., W15. Due to the thinning operation (e.g., etching operation) performed on contact etch stop layer 126b, contact etch stop layer 126a in first region 102 has a thickness W17, while contact etch stop layer 126b in second region 104 has a thickness W18 that is less than W17.

[0055] The gap W1 between adjacent first gate structures 114b is smaller than the gap W3 between adjacent second gate structures 116b. In some embodiments, W1 is about 60% to about 90% of W3, which may vary depending on different devices manufactured in the first region 102 and the second region 104 on the same substrate 106. In some embodiments, W1 is about 65% to about 80% of W3.

[0056] The width of the first conductive member 136a can be approximately equal to (W1 - 2 * (W15 + W17)), and the width of the second conductive member 136b can be approximately equal to (W3 - 2 * (W15 + W17)). In some embodiments, compared to the parasitic capacitance and parasitic resistance between the second gate structure 116b and the second conductive member 136b, the device formed in the first region 102 may need to reduce the parasitic capacitance and increase the parasitic resistance between the first gate structure 114b and the first conductive member 136a. This embodiment can meet the requirements by thinning the contact etch stop layer 126b.

[0057] Figure 27 is a flowchart of a method 400 for manufacturing a semiconductor structure according to some embodiments. During operation 402, a first dummy gate structure 114 is formed on a first region 102 of a substrate 106 and a second dummy gate structure 116 is formed on a second region 104 of the substrate 106. A first gap W1 is formed between adjacent first dummy gate structures 114 and a second gap W3 is formed between adjacent second dummy gate structures 116, wherein the first gap W1 is smaller than the second gap W3.

[0058] During operation 404, a spacer layer 118 is formed over the first dummy gate structure 114, the second dummy gate structure 116, and the substrate 106. Then, during operation 406, a thinning operation is performed on the spacer layer 118 in the first region 102. In some embodiments, the thinning operation may include removing a portion of the spacer layer 118 in the first region 102 such that the thickness W6 of the spacer layer 118a in the first region 102 is less than the thickness W7 of the spacer layer 118b in the second region 104.

[0059] During operation 408, a first source / drain component 122 is formed on substrate 106 between adjacent first dummy gate structures 114, and a second source / drain component 124 is formed on substrate 106 between adjacent second dummy gate structures 116. A portion of spacer layers 118a and 118b on substrate 106, on the first dummy gate structure 114, and on the second dummy gate structure 116 are removed. Spacer layer 118a on the sidewall of the first gap is thinner than spacer layer 118b on the sidewall of the second gap. Then, an ion implantation operation is performed to form lightly doped drain (LDD) regions in substrate 106 between adjacent first dummy gate structures 114 and adjacent second dummy gate structures 116. Contact etch stop layers 126a and 126b can be formed over the first dummy gate structure 114, the second dummy gate structure 116, spacer layers 118a and 118b, the first source / drain component 122, and the second source / drain component 124.

[0060] During operation 410, the first dummy gate structure 114 can be replaced by the first gate structure 114b, and the second dummy gate structure 116 can be replaced by the second gate structure 116b. A first dielectric layer 128 is formed over the first source / drain component 122 between adjacent first dummy gate structures 114 and the second source / drain component 124 between adjacent second dummy gate structures 116. The width of the first dielectric layer 128a formed between adjacent first dummy gate structures 114 is smaller than the width of the first dielectric layer 128b formed between adjacent second dummy gate structures 116.

[0061] Then, the first dummy gate structure 114 and the second dummy gate structure 116 are removed, and the first gate structure 114b and the second gate structure 116b are formed on the substrate 106. In addition, the top of the first gate structure 114b and the second gate structure 116b are removed, and a hard masking layer 134 is formed on each of the first gate structure 114b and the second gate structure 116b.

[0062] During operation 412, a first conductive component 136a is formed on a first source / drain component 122 between adjacent first gate structures 114b, and a second conductive component 136b is formed on a second source / drain component 124 between adjacent second gate structures 116b. To form the first conductive component 136a and the second conductive component 136b, a second dielectric layer, such as an interlayer dielectric layer (not shown), may be formed first over the first gate structure 114b, the second gate structure 116b, the first dielectric layers 128a and 128b, and the spacer layers 118a and 118b. At least a portion of the first dielectric layer and the second dielectric layers 128a and 128b is removed to expose the first source / drain component 122 and the second source / drain component 124. Then, the first conductive component 136a is formed on the first source / drain component 122, and the second conductive component 136b is formed on the second source / drain component 124.

[0063] Figure 28 is a flowchart of another method 500 for manufacturing a semiconductor structure according to some embodiments.

[0064] During operation 502, a first dummy gate structure 114 is formed on a first region 102 of the substrate 106 and a second dummy gate structure 116 is formed on a second region 104 of the substrate 106. A first gap W1 is formed between adjacent first dummy gate structures 114 and a second gap W3 is formed between adjacent second dummy gate structures 116, wherein the first gap W1 is smaller than the second gap W3.

[0065] During operation 504, a spacer layer 118 is formed above the first dummy gate structure 114, the second dummy gate structure 116 and the substrate 106.

[0066] During operation 506, a first source / drain component 122 is formed on substrate 106 between adjacent first dummy gate structures 114, and a second source / drain component 124 is formed on substrate 106 between adjacent second dummy gate structures 116. A portion of spacer layers 118a and 118b on substrate 106, on the first dummy gate structures 114, and on the second dummy gate structures 116 are removed. Then, an ion implantation operation is performed to form lightly doped drain (LDD) regions in substrate 106 between adjacent first dummy gate structures 114 and between adjacent second dummy gate structures 116.

[0067] During operation 508, contact etch stop layers 126a and 126b may be formed over the first dummy gate structure 114, the second dummy gate structure 116, spacer layers 118a and 118b, the first source / drain component 122, and the second source / drain component 124.

[0068] During operation 510, the contact etch stop layer 126a in the first region 102 can be thinned. To perform the thinning operation, a protective layer 220 can first be formed over the contact etch stop layer 126b in the second region 104. Then, an etching operation is performed to remove a portion of the contact etch stop layer 126a in the first region 102. After the etching operation, the contact etch stop layer 126a on the sidewall of the first gap is thinner than the contact etch stop layer 126b on the sidewall of the second gap.

[0069] During operation 512, the first dummy gate structure 114 can be replaced by the first gate structure 114b, and the second dummy gate structure 116 can be replaced by the second gate structure 116b. A first dielectric layer 128 is formed over the first source / drain component 122 between adjacent first dummy gate structures 114 and the second source / drain component 124 between adjacent second dummy gate structures 116. The width of the first dielectric layer 128a formed between adjacent first dummy gate structures 114 is smaller than the width of the first dielectric layer 128b formed between adjacent second dummy gate structures 116.

[0070] Then, the first dummy gate structure 114 and the second dummy gate structure 116 are removed, and the first gate structure 114b and the second gate structure 116b are formed on the substrate 106. In addition, the top of the first gate structure 114b and the second gate structure 116b are removed, and a hard masking layer 134 is formed on each of the first gate structure 114b and the second gate structure 116b.

[0071] During operation 514, a first conductive component 136a is formed on a first source / drain component 122 between adjacent first gate structures 114b, and a second conductive component 136b is formed on a second source / drain component 124 between adjacent second gate structures 116b. To form the first conductive component 136a and the second conductive component 136b, a second dielectric layer, such as an interlayer dielectric layer (not shown), may be formed first over the first gate structure 114b, the second gate structure 116b, the first dielectric layers 128a and 128b, and the spacer layers 118a and 118b. At least a portion of the second dielectric layer and the first dielectric layers 128a and 128b is removed to expose the first source / drain component 122 and the second source / drain component 124. Then, the first conductive component 136a is formed on the first source / drain component 122, and the second conductive component 136b is formed on the second source / drain component 124.

[0072] In this disclosure, the spacer layer 118 or the contact etch stop layer 126 can be selectively removed depending on the different devices located in different regions of the substrate, thus allowing for variations in the thickness of the spacer layer 118 or the contact etch stop layer 126. By changing the total thickness of the insulating layer (including the spacer layer 118 and the contact etch stop layer 126), the parasitic capacitance and resistance between different predetermined devices formed on the same substrate can be optimized. Furthermore, since the first gate structure 114b and the second gate structure 116b are formed in the same process, and the first conductive component 136a and the second conductive component 136b are formed in the same process, the process of forming insulating layers of different thicknesses in different regions of the same substrate can be further simplified. Moreover, by removing a portion of the spacer layer 118 or the contact etch stop layer 126 to optimize the parasitic capacitance and resistance between devices with different critical dimensions, devices with large process margins are not limited to tradeoffs with devices with small process margins.

[0073] One embodiment is a semiconductor structure. This semiconductor structure includes a first semiconductor device formed on a substrate and a second semiconductor device formed on the substrate. The first semiconductor device includes a first source / drain component on the substrate, a first gate structure on the substrate, a first conductive component on the first source / drain component, and a first insulating layer between the first gate structure and the first conductive component. The second semiconductor device includes a second source / drain component on the substrate, a second gate structure on the substrate, a second conductive component on the second source / drain component, and a second insulating layer between the second gate structure and the second conductive component. The width of the first conductive component is different from the width of the second conductive component, and the width of the first insulating layer is smaller than the width of the second insulating layer.

[0074] In one embodiment, the first insulating layer includes a first spacer layer and a first contact etch stop layer (CESL) formed between the first conductive component and the first spacer layer, and the second insulating layer includes a second spacer layer and a second contact etch stop layer formed between the second conductive component and the second spacer layer. The first spacer layer and the second spacer layer are formed of the same material, and the first contact etch stop layer and the second contact etch stop layer are formed of the same material.

[0075] In one embodiment, the first insulating layer includes a first spacer layer and a first contact etch stop layer (CESL) formed between the first conductive component and the first spacer layer, the second insulating layer includes a second spacer layer and a second contact etch stop layer formed between the second conductive component and the second spacer layer, and the width of the first spacer layer is smaller than the width of the second spacer layer.

[0076] In one embodiment, the first spacer layer and the second spacer layer are formed on different regions of the substrate during the same process.

[0077] In one embodiment, the first insulating layer includes a first spacer layer and a first contact etch stop layer (CESL) formed between the first conductive component and the first spacer layer, the second insulating layer includes a second spacer layer and a second contact etch stop layer formed between the second conductive component and the second spacer layer, and the width of the first contact etch stop layer is smaller than the width of the second contact etch stop layer.

[0078] In one embodiment, the first contact etch stop layer and the second contact etch stop layer are formed on different regions of the substrate during the same process.

[0079] Another embodiment is a semiconductor structure. This semiconductor structure includes a first semiconductor device formed on a substrate and a second semiconductor device formed on the substrate. The first semiconductor device includes a first source / drain component on the substrate, a first gate structure on the substrate, a first conductive component on the first source / drain component, and a first insulating layer between the first gate structure and the first conductive component. The second semiconductor device includes a second source / drain component on the substrate, a second gate structure on the substrate, a second conductive component on the second source / drain component, and a second insulating layer between the second gate structure and the second conductive component. The width of the first gate structure is approximately equal to the width of the second gate structure, and the width of the first insulating layer is smaller than the width of the second insulating layer.

[0080] In one embodiment, the first conductive component and the second conductive component are formed on different regions of the substrate during the same process, and the first gate structure and the second gate structure are formed on different regions of the substrate during the same process.

[0081] In one embodiment, the width of the first conductive component is smaller than the width of the second conductive component.

[0082] In one embodiment, the width of the second conductive component is smaller than the width of the first conductive component.

[0083] In one embodiment, the first insulating layer includes a first spacer layer and a first contact etch stop layer (CESL) formed between the first conductive component and the first spacer layer, and the second insulating layer includes a second spacer layer and a second contact etch stop layer formed between the second conductive component and the second spacer layer. The first spacer layer and the second spacer layer contain the same material, and the first contact etch stop layer and the second contact etch stop layer contain the same material.

[0084] In one embodiment, the width of the first contact etch stop layer is smaller than the width of the second contact etch stop layer.

[0085] Another embodiment is a method for forming a semiconductor structure. A plurality of first dummy gate structures are formed in a first region of a substrate, and a plurality of second dummy gate structures are formed in a second region of the substrate. A first gap is formed between adjacent first dummy gate structures, and a second gap is formed between adjacent second dummy gate structures, the first gap being smaller than the second gap. A spacer layer is formed over the plurality of first dummy gate structures, the plurality of second dummy gate structures, and the substrate. The spacer layer in the first region is thinned. First source / drain components are formed on the substrate between adjacent first dummy gate structures, and second source / drain components are formed on the substrate between adjacent second dummy gate structures. The plurality of first dummy gate structures are replaced with the plurality of first gate structures, and the plurality of second dummy gate structures are replaced with the plurality of second gate structures. A first conductive component is formed on the first source / drain component between adjacent first gate structures, and a second conductive component is formed on the second source / drain component between adjacent second gate structures.

[0086] In one embodiment, thinning the spacer layer in the first region includes removing a portion of the spacer layer in the first region such that the thickness of the spacer layer in the first region is less than the thickness of the spacer layer in the second region.

[0087] In one embodiment, forming a first source / drain component on a substrate between adjacent first dummy gate structures and forming a second source / drain component on a substrate between adjacent second dummy gate structures includes: removing a portion of the spacer layer on the substrate, the plurality of first dummy gate structures, and the plurality of second dummy gate structures; and performing an ion implantation operation to form a lightly doped drain region (LDD) in the substrate between adjacent first dummy gate structures and between adjacent second dummy gate structures.

[0088] In one embodiment, after removing a portion of the spacer layer on the substrate, the plurality of first dummy gate structures, and the plurality of second dummy gate structures, the spacer layer on the sidewall of the first gap is thinner than the spacer layer on the sidewall of the second gap.

[0089] In one embodiment, replacing a plurality of first dummy gate structures with a plurality of first gate structures and replacing a plurality of second dummy gate structures with a plurality of second gate structures includes: forming a first dielectric layer over a first source / drain component between adjacent first dummy gate structures and a second source / drain component between adjacent second dummy gate structures, wherein the width of the first dielectric layer formed between adjacent first dummy gate structures is smaller than the width of the first dielectric layer formed between adjacent second dummy gate structures; removing the plurality of first dummy gate structures and the plurality of second dummy gate structures; and forming the plurality of first gate structures and the plurality of second gate structures on a substrate.

[0090] In one embodiment, the method further includes: removing the tops of a plurality of first gate structures and a plurality of second gate structures; and forming a hard masking layer on each of the plurality of first gate structures and the plurality of second gate structures.

[0091] In one embodiment, forming a first conductive component on a first source / drain component between adjacent first gate structures and forming a second conductive component on a second source / drain component between adjacent second gate structures includes: forming a second dielectric layer over a plurality of first gate structures, a plurality of second gate structures, a first dielectric layer, and a spacer layer; removing at least a portion of the first dielectric layer and the second dielectric layer to expose the first source / drain component and the second source / drain component; and forming the first conductive component on the first source / drain component and forming the second conductive component on the second source / drain component.

[0092] In one embodiment, the method further includes forming a contact etch stop layer over a plurality of first dummy gate structures, a plurality of second dummy gate structures, a spacer layer, a first source / drain component, and a second source / drain component.

[0093] The foregoing overview of components in several embodiments enables those skilled in the art to better understand various aspects of the embodiments of the present invention. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and that they can make various changes, substitutions, and adjustments without departing from the spirit and scope of the embodiments of the present invention.

[0094] 100, 200, 300: Semiconductor Structure 102: District 1 104: Second District 106: Base 108: Dummy gate dielectric layer 110: Dummy gate electrode layer 112: Hard mask 114: First Dummy Gate Structure 114a, 116a: Groove 114b: First gate structure 116: Second Virtual Gate Structure 116b: Second gate structure 118, 118a, 118b: Spacer layers 120, 220: Protective layer 122: First source / drain component 124: Second source / drain component 126a, 126b: Contact etch stop layer 128a, 128b: Interlayer dielectric 130: Gate dielectric layer 132: Gate electrode 134: Hard mask layer 136a: First conductive component 136b: Second conductive component 400, 500: Method 402,404,406,408,410,412,502,504,506,508,510,512,514: Operations D1: Distance W1, W3: Gap W2, W4: Width W5, W6, W7, W8, W10, W11, W12, W13, W15, W16, W17, W18: Thickness

Claims

1. A semiconductor structure, comprising: A first semiconductor device is formed on a substrate and includes: a first source / drain component on the substrate; a first gate structure on the substrate; a first conductive component on the first source / drain component; and a first insulating layer between the first gate structure and the first conductive component. A second semiconductor device is also formed on the substrate and includes: a second source / drain component on the substrate; a second gate structure on the substrate; a second conductive component on the second source / drain component; and a second insulating layer between the second gate structure and the second conductive component. The width of the first conductive component is greater than the width of the second conductive component, and the width of the first insulating layer is less than the width of the second insulating layer.

2. The semiconductor structure as claimed in claim 1, wherein the first insulating layer includes a first spacer layer and a first contact etch stop layer formed between the first conductive member and the first spacer layer, the second insulating layer includes a second spacer layer and a second contact etch stop layer formed between the second conductive member and the second spacer layer, the first spacer layer and the second spacer layer are formed of a first dielectric material, and the first contact etch stop layer and the second contact etch stop layer are formed of a second dielectric material.

3. A semiconductor structure, comprising: A first semiconductor device is formed on a substrate and includes: a first source / drain component on the substrate; a first gate structure on the substrate; a first conductive component on the first source / drain component; and a first insulating layer between the first gate structure and the first conductive component, wherein the first insulating layer includes a first contact etch stop layer contacting the first source / drain component; and a second semiconductor device is formed on the substrate and includes: a second source / drain component on the substrate; a second gate structure on the substrate; a second conductive component on the second source / drain component; and a second insulating layer between the second gate structure and the second conductive component, wherein the second insulating layer includes a second contact etch stop layer contacting the second source / drain component; wherein the width of the first gate structure is approximately equal to the width of the second gate structure, the width of the first conductive component is greater than the width of the second conductive component, and the thickness of the first contact etch stop layer is less than the thickness of the second contact etch stop layer.

4. The semiconductor structure as claimed in claim 3, wherein the first conductive component and the second conductive component are formed on different regions of the substrate during the same process, and the first gate structure and the second gate structure are formed on different regions of the substrate during the same process.

5. A method for manufacturing a semiconductor structure, comprising: A plurality of first dummy gate structures are formed in a first region of a substrate, and a plurality of second dummy gate structures are formed in a second region of the substrate. A first gap is formed between adjacent first dummy gate structures, and a second gap is formed between adjacent second dummy gate structures, wherein the first gap is smaller than the second gap. A spacer layer is formed above the sidewalls of the first dummy gate structures and the sidewalls of the second dummy gate structures. A first source / drain component is formed on the substrate between adjacent first dummy gate structures, and a second source / drain component is formed on the substrate between adjacent second dummy gate structures. A contact etch stop layer is compliantly formed on the spacer layer, the first source / drain component, and the second source / drain component. The contact etch stop layer is thinned such that the contact etch stop layer in the first region has a first thickness, and the contact etch stop layer in the second region has a second thickness smaller than the first thickness. The first dummy gate structures are replaced by a plurality of first gate structures, and the second dummy gate structures are replaced by a plurality of second gate structures; a first conductive member is formed on the first source / drain member between adjacent first gate structures, and a second conductive member is formed on the second source / drain member between adjacent second gate structures, wherein the width of the first conductive member is smaller than the width of the second conductive member.

6. A semiconductor structure, comprising: A first semiconductor device is formed on a substrate and includes: a first source / drain component on the substrate; a first gate structure on the substrate; a first conductive component on the first source / drain component; and a first insulating layer between the first gate structure and the first conductive component, wherein the first insulating layer includes a first contact etch stop layer contacting the first source / drain component; and a second semiconductor device is formed on the substrate and includes: a second source / drain component on the substrate; a second gate structure on the substrate; a second conductive component on the second source / drain component; and a second insulating layer between the second gate structure and the second conductive component, wherein the second insulating layer includes a second contact etch stop layer contacting the second source / drain component, wherein the width of the first conductive component is greater than the width of the second conductive component, and the thickness of the first contact etch stop layer is less than the thickness of the second contact etch stop layer.

7. A semiconductor structure comprising: A first gate structure is disposed between two first source / drain contacts in a first device region above a substrate, wherein each first source / drain contact has a first width; a second gate structure is disposed between two second source / drain contacts in a second device region above the substrate, wherein each second source / drain contact has a second width greater than the first width; a first contact etch stop layer is disposed between the first gate structure and the first source / drain contacts, wherein the first contact etch stop layer has a first thickness; and a second contact etch stop layer is disposed between the second gate structure and the second source / drain contacts, wherein the second contact etch stop layer has a second thickness less than the first thickness.

8. A method for manufacturing a semiconductor structure, comprising: A first source / drain contact opening is formed in a first region above a substrate, penetrating a dummy gate structure, and a second source / drain contact opening is formed in a second region above the substrate, penetrating the dummy gate structure. The first source / drain contact opening exposes a first source / drain component and a first spacer layer within the first source / drain contact opening. The second source / drain contact opening exposes a second source / drain component and a second spacer layer within the second source / drain contact opening. The first source / drain contact opening has a first width, and the second source / drain contact opening has a second width greater than the first width. A contact etch stop layer is formed on the exposed surfaces of the first spacer layer, the first source / drain component, the second spacer layer, and the second source / drain component. A thinning operation is performed such that the thickness of the contact etch stop layer within the first source / drain contact opening is greater than the thickness of the contact etch stop layer within the second source / drain contact opening. The first source / drain contact opening and the second source / drain contact opening are filled with an interlayer dielectric; the dummy gate structure is removed from the first region and the second region; a first gate structure and a second gate structure are formed in the regions formed by removing the dummy gate structure in the first region and the second region, respectively; and the interlayer dielectric in the first source / drain contact opening and the second source / drain contact opening is replaced with a conductive component, wherein the width of the conductive component in the first region is smaller than the width of the conductive component in the second region.

9. The method for manufacturing the semiconductor structure as described in claim 8 further includes: After the contact etch stop layer is formed and before the thinning operation is performed, a protective layer is formed over the contact etch stop layer in the second region.

10. A method of manufacturing a semiconductor structure as claimed in claim 8 or 9, wherein the width of the second gate structure is smaller than the second width of the second source / drain contact opening.

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