Microelectronic assemblies having topside power delivery structures

Abstract

This document discloses microelectronic assemblies, related devices, and methods. In some embodiments, a microelectronic assembly may include: a package substrate including a first conductive path electrically coupled to a power source; a mold material on the package substrate, the mold material including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV between the first microelectronic component and the second microelectronic component, the TMV being electrically coupled to the first conductive path; a redistribution layer (RDL) on the mold material, the redistribution layer including a second conductive path electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive path, wherein the second conductive path is electrically coupled to the TMV, the first microelectronic component, and the third microelectronic component.

Description

[Technical Field]

[0001] The present invention relates to a microelectronic assembly having a top-side power transmission structure. [Previous Technology]

[0002] Background of the Invention

[0003] An integrated circuit (IC) package may include a power delivery network having processing components, voltage regulators, and input / output (I / O) dies to manage power delivery to the IC components within the IC package. An IC package may include thousands of power interconnects to deliver low-voltage power to the IC components within the IC package. [Summary of the Invention]

[0004] According to one embodiment of the present invention, a microelectronic assembly is specifically provided, comprising: a packaging substrate having a surface including a first conductive path electrically coupled to a power source; a mold material on the surface of the packaging substrate, the mold material including a first microelectronic component having a first surface and an opposing second surface embedded in the mold material, a second microelectronic component embedded in the mold material, and a through-hole (TMV) between the first microelectronic component and the second microelectronic component, the TMV being electrically coupled to the first conductive path; a redistribution layer (RDL) having a first surface and an opposing second surface on the mold material, including a second conductive path electrically coupled to the TMV; and a third microelectronic component located on the second surface of the RDL and electrically coupled to the second conductive path, wherein the second conductive path is electrically coupled to the TMV, the third microelectronic component, and the second surface of the first microelectronic component.

Implementation Method

[0024] Detailed Description of Preferred Embodiments

[0025] This document discloses microelectronic assemblies, related apparatuses, and methods for top-side power delivery to microelectronic components. For example, in some embodiments, the microelectronic assembly may include: a package substrate having a surface including a first conductive path electrically coupled to a power source; an insulating material on the surface of the package substrate; a first microelectronic component having a first surface and an opposing second surface, embedded in the insulating material, the first surface facing the package substrate; a second microelectronic component having a first surface and an opposing second surface, embedded in the insulating material, the first surface facing the package substrate; a redistribution layer on the insulating material, the redistribution layer including a second conductive path electrically coupled to the second surface of the second microelectronic component and the second surface of the first microelectronic component; and bonding wires electrically coupled to the first conductive path and the second conductive path. In some embodiments, the microelectronic assembly may include: a package substrate having a surface including a first conductive path electrically coupled to a power source; an insulating material on the surface of the package substrate; a first microelectronic component having a first surface and an opposing second surface embedded in the insulating material, wherein the first surface faces the package substrate; a second microelectronic component having a first surface and an opposing second surface embedded in the insulating material, wherein the first surface faces the package substrate; a through-hole (TMV) positioned along the periphery of the insulating material, extending through the insulating material and electrically coupled to the first conductive path; and a redistribution layer on the mold material, the redistribution layer including a second conductive path electrically coupled to the TMV, the second microelectronic component, and the second surface of the first microelectronic component. In some embodiments, the microelectronic assembly may include: a package substrate having a surface including a first conductive path electrically coupled to a power source; a first microelectronic component having a first surface electrically coupled to the surface of the package substrate and an opposing second surface, embedded in an insulating material on the surface of the package substrate and including a through-substrate via (TSV) electrically coupled to the first conductive path; a second microelectronic component having a first surface electrically coupled to the surface of the package substrate and an opposing second surface, embedded in an insulating material; and a redistribution layer on the insulating material, the redistribution layer including a second conductive path electrically coupled to the TSV, the second surface of the second microelectronic component, and the second surface of the first microelectronic component. In some embodiments, the microelectronic assembly may include: a package substrate having a surface including a first conductive path electrically coupled to a power source; a first microelectronic component having a first surface electrically coupled to the surface of the package substrate and an opposing second surface, embedded in an insulating material on the surface of the package substrate and including a TSV electrically coupled to the first conductive path; a redistribution layer having a first surface and an opposing second surface on the insulating material, including a second conductive path electrically coupled to the TSV; and a second microelectronic component located at the second surface of the redistribution layer and electrically coupled to the second conductive path, wherein the second conductive path electrically couples the TSV, the second microelectronic component, and the second surface of the first microelectronic component.In some embodiments, the microelectronic assembly may include: a package substrate having a surface including a first conductive path electrically coupled to a power source; a mold material on the surface of the package substrate, the mold material including a first microelectronic component having a first surface and an opposing second surface embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV between the first microelectronic component and the second microelectronic component, the TMV being electrically coupled to the first conductive path; a redistribution layer having a first surface and an opposing second surface on the mold material, including a second conductive path electrically coupled to the TMV; and a third microelectronic component located on the second surface of the redistribution layer and electrically coupled to the second conductive path, wherein the second conductive path is electrically coupled to the TMV, the third microelectronic component, and the second surface of the first microelectronic component.

[0026] Due to the small size of such chips, the design challenges of routing a growing number of signals and power interconnects, and constraints associated with power delivery, it is difficult to transmit a large number of signals in a multi-chip IC package. Power delivery networks (PDNs) typically include voltage regulators (VRs), which are commonly used in electronic and communication applications to regulate voltage for power delivery. Conventional VRs, such as buck regulators, typically include a voltage input, a voltage output, an input capacitor, an output capacitor, an inductor, switching transistors and / or diodes, and control circuitry with multiple transistors to perform voltage regulation and control the switching transistors and / or diodes. Power delivery in integrated multi-chip IC packages becomes increasingly complex with different components having different functionalities and voltage requirements. For example, a high-power processing IC package may include multiple chips with multiple cores and multiple VRs associated with each chip and / or core, wherein each VR regulates power delivery at the same or different voltages / frequency. These cores typically require power delivery from an external power supply, which competes with a large number of power interconnects (e.g., approximately 7,000 power interconnects) for space on the IC package. The embodiments disclosed herein can improve IC package performance with greater design flexibility, lower cost, and / or smaller size compared to conventional methods by delivering power to the top surface of the component. The microelectronic assemblies disclosed herein exhibit superior power delivery while reducing the number of power interconnects required and the package size compared to conventional methods. The microelectronic assemblies disclosed herein are particularly advantageous for high-performance applications in computers, servers, deep learning, and artificial intelligence (AI) training.

[0027] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description, wherein similar numerals throughout the accompanying drawings refer to similar portions, and wherein feasible embodiments are illustrated by means of description. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be viewed in a limiting sense.

[0028] Various operations can be described in a manner most conducive to understanding the claimed subject matter as a series of discrete actions or operations arranged sequentially. However, the order of description should not be construed as implying that such operations must depend on the order. Specifically, such operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0029] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The drawings are not necessarily drawn to scale. Although many drawings illustrate cuboid structures with flat walls and right-angled corners, this is merely for ease of illustration, and actual devices manufactured using these techniques will exhibit rounded corners, surface roughness, and other morphologies.

[0030] The description uses the phrases "in one embodiment" or "in an embodiment," which may each refer to one or more of the same or different embodiments. Furthermore, as used with respect to embodiments of this disclosure, the terms "comprising," "including," "having," and the like are synonymous. As used herein, "package" and "IC package" are synonymous, as are "die" and "IC die." The terms "top" and "bottom" may be used herein to explain various shapes of the figures, but these terms are only for ease of discussion and to describe the relative orientation of one component to another, such that the relative orientation applies even when the figures are inverted. As used herein, unless otherwise specified, the term "insulating" means "electrically insulating." Throughout this specification and within the scope of the claims, the term "coupled" means a direct or indirect connection between things connected or indirectly via one or more passive or active intermediaries, such as a direct electrical, mechanical, or magnetic connection. The meanings of "a / an" and "the" include multiple references. The meaning of "in" includes both "in" and "on".

[0031] When used to describe a range of dimensions, the phrase "between X and Y" indicates a range including both X and Y. As used herein, the term "thickness" refers to the dimension of an element or layer as measured along the z-axis, the term "width" refers to the dimension of an element or layer as measured along the y-axis, and the term "length" refers to the dimension of an element or layer as measured along the x-axis. Although some elements may be mentioned in the singular form herein, such elements may include multiple sub-elements. For example, "insulating material" may include one or more insulating materials. As used herein, "conductive contact" may refer to a portion of a conductive material (e.g., metal) that serves as an electrical interface between different components; a conductive contact may be recessed into, flush with, or extend away from the surface of a component, and may take any suitable form (e.g., a conductive pad or socket, or a portion of a conductive wire or through-hole). For convenience, the phrase "Figure 5" can be used to refer to the set of diagrams from Figure 5A to Figure 5B, and the phrase "Figure 6" can be used to refer to the set of diagrams from Figure 6A to Figure 6G, etc.

[0032] FIG1 is a side cross-sectional view of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 of FIG1 may have a top-side power delivery path including TSVs 113, 119. The microelectronic assembly 100 may include: a circuit board 182 having a power supply 183 electrically coupled to a package substrate 150 having a first conductive path 109-1; a first microelectronic component 102 having a through-substrate via (TSV) 113; and a second microelectronic component 103 embedded in an insulating material 133 electrically coupled to the package substrate 150 at a first surface 170-1 and electrically coupled to a redistribution layer (RDL) 148 having a second conductive path 109-2 and a third conductive path 109-3 at a second surface 170-2. Specifically, the first conductive path 109-1 in the package substrate 150 is electrically coupled to the power supply 183, the first surface 170-1 of the TSV 113 is electrically coupled to the first conductive path 109-1, the second surface 170-2 of the TSV 113 and the second surface 170-2 of the second microelectronic component 103 are electrically coupled to the second conductive path 109-2, and the second surface 170-2 of the second microelectronic component 103 and the second surface 170-2 of the first microelectronic component 102 are electrically coupled to the third conductive path 109-3, so that power can be supplied from the power supply 183 to the second surface 170-2 of the first microelectronic component 102. In some embodiments, the second conductive path 190-2 and the third conductive path 109-3 are the same conductive path in the RDL 148.

[0033] The second microelectronic component 103 of the microelectronic assembly 100 may further include a TSV 117. Specifically, the first surface 170-1 of the TSV 117 may be electrically coupled to a first conductive path 109-1 in the package substrate 150, and the second surface 170-2 of the TSV 117 may be electrically coupled to a second conductive path 109-2 in the RDL 148, such that power can be supplied from the power supply 183 to the second surface 170-2 of the first microelectronic component 102.

[0034] TSVs 113 and 117 may be made of any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys. TSVs 113 and 117 may have any suitable dimensions; for example, the thickness (e.g., z-height) and / or width (e.g., y-dimension) of TSVs 113 and 117 used for power supply may be greater than the thickness or width of TSVs used for signal transmission. In some embodiments, TSVs 113 and 117 used for power supply may have the same thickness and / or width as TSVs used for signal transmission. In some embodiments, a plurality of TSVs 113 and 117 may be coupled to individual conductive contacts on the bottom surface 170-1 and / or top surface 170-2 of each microelectronic component 102, 103.

[0035] The microelectronic assembly 100 of FIG1 may also include: a third microelectronic component 105 embedded in an insulating material 133 of a package substrate 150 at a first surface 170-1; and a fourth microelectronic component 101 mounted on the top surface of an RDL 148 and electrically coupled to the second surface of a second microelectronic component 103 via a conductive path in the RDL 148 (e.g., electrically coupled to a top-side power delivery path).

[0036] Microelectronic components 101, 102, 103, and 105 may include any suitable components configured to supply or be supplied with power. In some embodiments, the first microelectronic component 102 is a central processing unit, graphics processing unit, digital signal processor, special application integrated circuit, server processor, or cryptographic processor. In some embodiments, the second microelectronic component 103 is a VR. In some such embodiments, the VR is configured to convert a low-current high-voltage signal into a low-voltage high-current signal. In some embodiments, the third microelectronic component 105 is a die having an I / O circuit system. In some embodiments, the fourth microelectronic component 101 is an inductor.

[0037] In some embodiments, the microelectronic component 102 may include IC dies (packaged or unpackaged) or stacks of IC dies (e.g., high-bandwidth memory die stacks). In some such embodiments, the insulating material of the microelectronic component 102 may include silicon dioxide, silicon nitride, oxynitride, polyimide materials, glass-reinforced epoxy matrix materials, or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photoimageable dielectrics, and / or benzocyclobutene polymers). In some other embodiments, the insulating material of the microelectronic component 102 may include semiconductor materials such as silicon, germanium, or III-V materials (e.g., gallium nitride) and one or more additional materials. For example, the insulating material of the microelectronic component 102 may include silicon oxide or silicon nitride. Conductive paths in microelectronic component 102 may include conductive lines and / or conductive vias, and any of the conductive contacts in microelectronic component 102 may be connected in any suitable manner (e.g., connecting multiple conductive contacts on the same or different surfaces of microelectronic component 102). Example structures that may be included in the microelectronic component 102 disclosed herein are discussed below with reference to FIG16. Specifically, microelectronic component 102 may include active and / or passive circuitry (e.g., transistors, diodes, resistors, inductors, capacitors, and others).

[0038] The first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 include an active surface 123 and an opposing back surface (not labeled), the active surface being a surface containing one or more active devices and a majority of interconnects. As shown in FIG1, the active surface 123 of the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 is located at the first surface 170-1 (e.g., the active surface faces the package substrate 150). Although FIG1 shows the first microelectronic component 102 and the second microelectronic component 103 as dual-sided components and the third microelectronic component 105 as a single-sided component, the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 can be single-sided or dual-sided components, and can be single-pitch components or mixed-pitch components. In this context, a dual-sided component refers to a microelectronic component with connections on both surfaces (e.g., the first surface 170-1 and the second surface 170-2). In some embodiments, the dual-sided components (e.g., the first microelectronic component 102 and the second microelectronic component 103) may include TSVs (e.g., TSVs 113, 117) to form a connection on two surfaces. In such embodiments, the dual-sided components may include TSVs configured to transmit signal data and / or TSVs configured to deliver power. The active surfaces of the dual-sided components may face either direction depending on design and electrical requirements (as described in more detail below with reference to Figures 2 and 3). In some embodiments of the microelectronic assembly 100 disclosed herein, the microelectronic components 102, 103, and / or 105 embedded in the insulating material 133 may have different thicknesses. The fourth microelectronic component 101 further includes an active surface (not shown) electrically coupled at its bottom surface to the top surface of the RDL 148. In some embodiments, additional components may be disposed on the top surface of the RDL 148. Additional passive components, such as surface-mount resistors, capacitors, and / or additional inductors, may be disposed on the top or bottom surface of the package substrate 150, or may be embedded in the package substrate 150.

[0039] The insulating material 133 may include any suitable material. In some embodiments, the insulating material 133 is a mold material, such as an organic polymer containing inorganic silica particles. In some embodiments, the insulating material 133 is a dielectric material. In some embodiments, the dielectric material may include organic dielectric materials, flame retardant grade 4 materials (FR-4), BT resin, polyimide materials, glass-reinforced epoxy resin matrix materials, or low-K and ultra-low-K dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymer dielectrics). The insulating material 133 may be formed using any suitable process, including lamination or gap coating and curing.

[0040] RDL 148 may include an insulating material (e.g., a dielectric material formed in a multilayer form, as known in the art) and one or more conductive paths for conducting electricity (e.g., second conductive path 109-2 and third conductive path 109-3), grounding, and signal transmission through the dielectric material (e.g., including conductive traces and / or conductive vias, as shown). The insulating material 133 may extend around or therebetween one or more of the microelectronic components 102, 103, 105 on the package substrate 150. In some embodiments, the insulating material 133 may extend over one or more of the microelectronic components 102, 103, 105 on the package substrate 150 (not shown). The conductive paths including the second conductive path 109-2 and the third conductive path 109-3 may be made of any suitable conductive material, for example, copper, silver, nickel, gold, aluminum, or other metals or alloys. The conductive paths can have any suitable dimensions. For example, the thickness (e.g., z-height) and / or width (e.g., y-dimension) of the second conductive path 109-2 and the third conductive path 109-3 used for supplying power can be greater than the thickness or width of the conductive path used for transmitting signals. For example, in some embodiments, the thickness and / or width of the second conductive path 109-2 and the third conductive path 109-3 can be between 5 micrometers and 25 micrometers. In some embodiments, the thickness and / or width of the second conductive path 109-2 and the third conductive path 109-3 can be between 5 micrometers and 15 micrometers. Any suitable technique can be used to fabricate the RDL 148, such as standard printed circuit board (PCB) technology or redistribution technology. Any of the microelectronic assemblies 100 disclosed herein may include any number of RDLs and may be located at the first surface 170-1 and / or the second surface 170-2 of the insulating material 133.

[0041] In some embodiments, the package substrate 150 may include a power source (not shown) electrically coupled to the first conductive path 109-1. Conductive contacts on the first surfaces 170-1 of the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 may be coupled to conductive contacts on the top surface of the package substrate 150 via a first level interconnect (FLI) 151. The FLI 151 disclosed herein may take any suitable form. In some embodiments, the FLI 151 may include small conductive bumps (e.g., copper bumps) attached by solder. In some embodiments, the FLI 151 may include anisotropic conductive material. In some embodiments, some or all of the FLI 151 may be intermetallic interconnects (e.g., copper interconnects or plated interconnects). In some embodiments, the FLI 151 may be hybrid bonding interconnects.

[0042] The package substrate 150 may include an insulating material (e.g., a dielectric material formed in a multilayer form, as known in the art) and one or more conductive paths to conduct power, grounding, and signals through the dielectric material (e.g., including conductive traces and / or conductive vias, as shown). In some embodiments, the insulating material of the package substrate 150 may be a dielectric material, such as an organic dielectric material, a flame retardant grade 4 material (FR-4), bismaleimide triterpenoid (BT) resin, a polyimide material, a glass-reinforced epoxy matrix material, an organic dielectric containing inorganic fillers, or low-k and ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymer dielectrics). Specifically, when the package substrate 150 is formed using a standard PCB process, the package substrate 150 may include FR-4, and the conductive paths in the package substrate 150 may be formed by patterned copper sheets separated by a stack of FR-4. The conductive paths within the package substrate 150 may be interfaced by lining materials, such as adhesive liners and / or barrier liners, where appropriate. The first conductive path 109-1 may be made of any suitable conductive material, for example, copper, silver, nickel, gold, aluminum, or other metals or alloys. The first conductive path 109-1 may have any suitable dimensions; for example, the thickness (e.g., z-height) and / or width (e.g., y-dimension) of the first conductive path 109-1 used for power supply may be greater than the thickness or width of the conductive path used for signal transmission. In some embodiments, the first conductive path 109-1 used for power supply may have the same thickness and / or width as the conductive path used for signal transmission. In some embodiments, a plurality of first conductive paths 109-1 may be coupled to individual conductive contacts on the bottom and / or top surfaces of the package substrate 150.

[0043] In some embodiments, the encapsulation substrate 150 may be formed using an encapsulation process defined by lithography. In some embodiments, the encapsulation substrate 150 may be manufactured using standard organic encapsulation manufacturing processes, and therefore the encapsulation substrate 150 may be in the form of an organic encapsulation. In some embodiments, the encapsulation substrate 150 may be a set of redistribution layers formed on a panel carrier by laminating or spinning on a dielectric material and creating conductive vias and lines by laser drilling and electroplating. In some embodiments, the encapsulation substrate 150 may be formed on a removable carrier using any suitable technique such as redistribution technology. Any method known in the art for manufacturing the encapsulation substrate 150 may be used, and for the sake of brevity, such methods will not be discussed further in detail herein. In other embodiments, the encapsulation substrate may be a silicon or glass insert.

[0044] In some embodiments, the package substrate 150 may be a lower-density dielectric, and the first microelectronic component 102, the second microelectronic component 103, and / or the third microelectronic component 105 may be a higher-density dielectric or regions having a higher-density dielectric. As used herein, the terms "lower density" and "higher density" are relative terms indicating that conductive paths (e.g., including conductive interconnects, conductive lines, and conductive vias) in the lower-density dielectric are larger and / or have greater spacing than conductive paths in the higher-density dielectric. In some embodiments, the higher-density dielectric may be manufactured using a modified semi-additive process or semi-additive stacking process incorporating advanced lithography (where a smaller vertical interconnect topology is formed by advanced laser or lithography processes), while the lower-density dielectric may be a printed circuit board (PCB) manufactured using standard PCB processes (e.g., a standard removal process that uses etch chemicals to remove areas of non-desired copper, where a coarse vertical interconnect topology is formed by a standard laser process). In other embodiments, the higher density dielectric can be manufactured using semiconductor manufacturing processes, such as single-metal damascene processes or bimetal damascene processes.

[0045] The microelectronic assembly 100 of FIG1 may also include a circuit board 182. In some embodiments, the circuit board 182 may include a power supply 183. In some embodiments, the power supply 183 may be a component attached to the surface of the circuit board 182. In some embodiments, the power supply 183 may be an integrated power supply; for example, the circuit board 182 may include a power plane and a ground plane, the power plane including an input voltage and an output voltage. The power plane may be a high-voltage power plane, a low-voltage power plane, or a high / low power plane, wherein the input voltage is high and the output voltage is low. As used herein, a power plane may refer to a conductive structure that transmits power and may refer to an electrical plane structure or a linear conductive structure (e.g., a corridor). As used herein, a ground plane may refer to a conductive structure connected to ground and may refer to an electrical plane structure or a linear conductive structure (e.g., a corridor). The power supply 183 may be electrically coupled to a first conductive path 109-1 in the package substrate 150 via a second-level interconnect (SLI) 181 at the bottom surface of the package substrate 150. SLI 181 can be any suitable second-level interconnect, including solder balls for a ball grid array arrangement (as shown), pins in a pin grid array arrangement, or pads in a pad grid array arrangement. Circuit board 182 can be, for example, a motherboard and may have other components attached thereto. Circuit board 182 may include conductive paths and other conductive contacts for guiding power, ground, and signals through the circuit board, as known in the art. In some embodiments, the second-level interconnect 181 may not couple the package substrate 150 to circuit board 182, but may instead couple the package substrate 150 to another IC package, through-hole, or any other suitable component.

[0046] The microelectronic assembly 100 of FIG1 may also include a heat transfer structure 135, such as a heat sink. The heat transfer structure 135 may be used to remove heat from the microelectronic components 102, 103, 105 (e.g., to make the heat more easily dissipated by a heat sink or other thermal management device). The heat transfer structure 135 may include any suitable thermally conductive material (e.g., metal, suitable ceramic, etc.) and may include any suitable morphology (e.g., heat sink). In some embodiments, the heat transfer structure 333 may be an integrated heat transfer structure. The microelectronic assembly 100 of FIG1 may also include a highly thermally conductive mold material or thermal interface material (TIM) (not shown) between the top surface of the RDL 148 and the bottom surface of the heat transfer structure 135. The TIM may include a thermally conductive material (e.g., metal particles) in a polymer or other binder. The TIM may be a thermal interface material paste or a thermally conductive epoxy resin (which may be fluid when applied and harden upon curing, as known in the art). The TIM provides a path for heat generated by microelectronic components 102, 103, 105 to flow easily to the heat transfer structure 135, wherein the heat can diffuse and / or dissipate.

[0047] The microelectronic assembly 100 of FIG1 may also include an underfill material (not shown). In some embodiments, the underfill material may extend between and around FLI 151 and / or SLI 181. The underfill material may be an insulating material, such as a suitable epoxy resin material. In some embodiments, the underfill material may include capillary underfill, non-conductive film (NCF), or molded underfill. In some embodiments, the underfill material may include epoxy resin flux. The underfill material may be selected to have a coefficient of thermal expansion (CTE) that can mitigate or minimize stress between the insulating material 133 and the package substrate 150 around the embedded microelectronic components 102, 103, 105 caused by uneven thermal expansion in the microelectronic assembly 100. In some embodiments, the CTE value of the underfill material may be between the CTE of the package substrate 150 (e.g., the CTE of the dielectric material of the package substrate 150) and the CTE of the insulating material 133.

[0048] Although Figure 1 shows a specific number of microelectronic assemblies 100 and their arrangement, which include multiple embedded first microelectronic components 102, second microelectronic components and third microelectronic components 103, 105, a single RDL 148 and multiple fourth microelectronic components 101 mounted on the top surface of the RDL 148, the microelectronic assembly 100 may include any number of microelectronic components 102, 103, 105, 101 and the RDL 148 and its arrangement having conductive paths electrically coupled to a power source to deliver power to the top surface of the microelectronic components.

[0049] Several components are shown in FIG1 as included in the microelectronic assembly 100, but several of these components may not be present in the microelectronic assembly 100. For example, in various embodiments, the support component 182, underfill material, heat transfer structure 135, and / or TIM may not be included. Furthermore, FIG1 shows several components omitted from subsequent figures for ease of illustration but which may be included in any of the microelectronic assemblies 100 disclosed herein. Examples of such components include the support component 182, underfill material, heat transfer structure 135, and / or TIM. Many components of the microelectronic assembly 100 of FIG1 are included in other figures accompanying the drawings; when discussing these figures, the discussion of these components will not be repeated, and any of these components may be in any of the forms disclosed herein. In some embodiments, individual microelectronic assemblies in the microelectronic assembly 100 disclosed herein may serve as system-in-package (SiP), including multiple microelectronic components 102 with different functionalities. In such embodiments, the microelectronic assembly 100 may be referred to as SiP.

[0050] FIG2 is a side cross-sectional view of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 of FIG2 may include the elements of FIG1 and may further include a second microelectronic component 103 having an active surface 123 at a second surface 170-2.

[0051] FIG3 is a side cross-sectional view of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 of FIG3 may have a top-side power delivery path including TSVs 113, 117. The microelectronic assembly 100 of FIG3 may include the elements of FIG2 and may further include a first microelectronic component 102 having an active surface 123 at a second surface 170-2. The microelectronic assembly 100 may further include a capacitor element 107 electrically coupled to the top-side power delivery path. Specifically, the microelectronic assembly 100 may further include a capacitor element 107A electrically coupled to the bottom surface of the package substrate 150 and / or a capacitor element 107B between the top surface of RDL 148 and the fourth microelectronic component 101 and electrically coupled to the top surface and the component.

[0052] FIG4 is a side cross-sectional view of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 of FIG4 may have a top-side power delivery path including TSVs 113 and 119. The microelectronic assembly 100 of FIG4 may include: a circuit board 182 having a power supply 183 electrically coupled to a package substrate 150 having a first conductive path 109-1; a first microelectronic component 102 having a TSV 113; and a third microelectronic component 105 having a TSV 119 embedded in an insulating material 133 electrically coupled to the package substrate 150 at a first surface 170-1 and electrically coupled to an RDL 148 having a second conductive path 109-2 and a third conductive path 109-3 at a second surface 170-2. Specifically, the first conductive path 109-1 in the package substrate 150 is electrically coupled to the power supply 183, the first surface 170-1 of TSVs 113 and 119 is electrically coupled to the first conductive path 109-1, the second surface 170-2 of TSVs 113 and 119 is electrically coupled to the second conductive path 109-2, and the second surface 170-2 of the first microelectronic component 102 and the second surface 170-2 of the third microelectronic component 105 are electrically coupled to the third conductive path 109-3, so that power can be supplied from the power supply 183 to the second surface 170-2 of the first microelectronic component 102. In some embodiments, the second conductive path 190-2 and the third conductive path 109-3 are the same conductive path in RDL 148. Conductive path 109 can be coupled to other components (e.g., package substrate 150 and microelectronic components 101, 102, 103, 105) via interconnects (e.g., conductive contacts, such as pads and / or bumps and solder) in interfaces between other components. TSV 119 can be made of any suitable conductive material and can have any suitable size, as described above with reference to TSV 113 in Figure 1.

[0053] The microelectronic assembly 100 of FIG4 may also include a second microelectronic component 103 and a fourth microelectronic component 101, which are mounted on the top surface of RDL 148 and electrically coupled to a second conductive path 109-2 and / or a third conductive path 109-3 in RDL 148 (e.g., electrically coupled to a top-side power delivery path). In some embodiments, the fourth microelectronic component 101A may be mounted on the top surface of the second microelectronic component 103 and electrically coupled to the second microelectronic component 103 via a conductive path in RDL 148 (as shown) or via conductive contacts (not shown) on the top and bottom surfaces of the second microelectronic component 103 and the fourth microelectronic component 101, respectively. In some embodiments, the fourth microelectronic component 101B may be mounted adjacent to the second microelectronic component 103 (e.g., side-by-side with it) on the top surface of RDL 148 and electrically coupled to the second microelectronic component 103 via a conductive path in RDL 148.

[0054] FIG. 5A is a side cross-sectional view of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 of FIG. 5A and FIG. 5B may have a top-side power delivery path including TSVs 113, 117. The microelectronic assembly 100 of FIG. 5A may include the components of FIG. 1 and may further include a first microelectronic component 102 and a second microelectronic component 103 having an active surface 123 at a second surface 170-2. The microelectronic assembly 100 may further include a plurality of capacitor elements 107 embedded in an insert 185 electrically coupled to the top-side power delivery path. Specifically, the microelectronic assembly 100 may include a plurality of capacitor elements 107 embedded in an insert 185 having a TSV 108, the insert 185 being located between the top surface of the package substrate 150 and the bottom surface (e.g., the first surface 170-1) of the microelectronic components 102, 103, 105 embedded in the insulating material 133. The plurality of capacitive elements 107 embedded in the insert 185 are electrically coupled to a first conductive path 109-1 in the package substrate 150 and to TSVs 113, 117 in the first microelectronic assembly 102 and the second microelectronic assembly 103. The capacitive elements 107 may include any suitable element having capacitance, such as a capacitor, a digitally tunable capacitor (DTC), or a metal-insulator-metal (MIM) capacitor, and others. The insert 185 may include any suitable material, such as silicon dioxide, silicon nitride, oxynitride, polyimide materials, glass-reinforced epoxy matrix materials, or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photoimageable dielectrics, and / or benzocyclobutene polymers). In some other embodiments, the material of insert 185 may include semiconductor materials such as silicon, germanium, or III-V materials (e.g., gallium nitride) and one or more additional materials, such as silicon oxide or silicon nitride.

[0055] FIG. 5B is a side cross-sectional view of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 of FIG. 5B may include the components of FIG. 1 other than the package substrate 150, and may further include a first microelectronic component 102 and a second microelectronic component 103 having an active surface 123 at a second surface 170-2. The microelectronic assembly 100 may further include a plurality of capacitor elements 107 embedded in an insert 185 electrically coupled to a top-side power delivery path. Specifically, the microelectronic assembly 100 may include a plurality of capacitor elements 107 embedded in an insert 185 having a TSV 108, the insert 185 being located between the top surface of the circuit board 182 and the bottom surface (e.g., the first surface 170-1) of the microelectronic components 102, 103, 105 embedded in an insulating material 133. Multiple capacitor elements 107 embedded in the insert 185 can be electrically coupled to a power supply 183 on the circuit board 182 and electrically coupled to TSVs 113 and 117 in the first microelectronic assembly 102 and the second microelectronic assembly 103 via pad grid array (LGA) interconnects 187. The microelectronic assembly 100 of FIG. 5B may also include a mold material 189. The mold material 189 may extend around the insert 185, the insulating material 133, and the RDL 148 on the circuit board 182. The mold material 189 may include any suitable material. In some embodiments, the mold material 189 is an organic polymer containing inorganic silica particles. In some embodiments, the mold material 189 is a dielectric material, as described above with reference to the insulating material 133 of FIG. 1. The microelectronic assembly 100 of FIG. 5B may also include conductive pillars 186 having solder 188 on the bottom surface and coupled to the TSV 108 on the top surface. The conductive post 186 may be surrounded by mold material 189 and may act as a stress buffer for LGA interconnect 187.

[0056] Any suitable technique can be used to manufacture the microelectronic assembly 100 disclosed herein. For example, Figures 6A to 6G are side cross-sectional views of various stages in an example process for manufacturing the microelectronic assembly 100 of Figure 1 according to various embodiments. Although the operations described below with reference to Figures 6A to 6G (and others in the accompanying drawings illustrating the manufacturing process) are described in a particular order, these operations can be performed in any suitable order.

[0057] Figure 6A illustrates the first microelectronic component 102 with TSV 113 and the second microelectronic component 103 with TSV 117 after removing non-electrical materials from the back surface (e.g., the back surface opposite the active surface 123), exposing the top surfaces of TSVs 113 and 117, and forming conductive contacts 122 on the top surfaces of the first microelectronic component 102 and the second microelectronic component 103. Non-electrical materials for the non-functional portions of microelectronic components 102 and 103 may include silicon, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, other materials classified as Group III-V, or insulating materials such as silicon dioxide (glass), ceramics, or quartz, as well as other materials. Any suitable technique can be used to remove the non-active materials, including, for example, grinding, etching, such as reactive ion etching (RIE), or chemical etching. In some embodiments, the back surface may be polished to expose the top surfaces of TSVs 113 and 117. In some embodiments, a back RDL may be formed on the back side of the first microelectronic component 102 and the second microelectronic component 103, and the conductive contact 122 may be formed by applying copper / tin bumps. In some embodiments, the first microelectronic component 102 and the second microelectronic component 103 may be processed at the wafer level and subsequently monolithized. FIG6A further illustrates the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 having conductive contacts 121 at the active surface 123.

[0058] Figure 6B illustrates the assembly after the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 are placed on the first carrier 604-1 and an insulating material 133 is deposited on and around the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105, wherein the active surface 123 faces away from the first carrier 604-1. The carrier 604 may include any suitable material and, in some embodiments, may include a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel). The first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 may be attached to the first carrier 604-1 using any suitable technique, including a temporary adhesive layer or a die attachment film (DAF). In some embodiments, insulating material 133 may be initially deposited on and above the top surfaces 170-2 of the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 (as shown), and then polished again to expose the conductive contacts 122 at the top surfaces of the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105. Insulating material 133 may be formed using any suitable process, including lamination or gap coating and curing. If insulating material 133 is formed to completely cover the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105, insulating material 133 may be removed using any suitable technique to expose the conductive contacts 122 at the top surfaces of the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105, including grinding or etching such as wet etching, dry etching (e.g., plasma etching), wet blasting, or laser ablation (e.g., using an excimer laser). In some embodiments, the thickness of the insulating material 133 may be minimized to reduce the required etching time.

[0059] FIG6C shows the assembly after a package substrate 150 is formed on the top surface 170-2 of the assembly of FIG6B and the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 are electrically coupled to the package substrate 150 via FLI 151. The package substrate 150 may include a first conductive path 109-1, and the first microelectronic component 102 and the second microelectronic component 103 may be electrically coupled to the first conductive path 109-1 via FLI 151. In some embodiments, the third microelectronic component 105 may also be electrically coupled to the first conductive path 109-1 via FLI 151. The package substrate 150 may be formed using any suitable technique, such as any of the techniques discussed above regarding the formation of the package substrate 150 with reference to FIG1.

[0060] Figure 6D shows the assembly after the second carrier 604-2 is mounted to the top surface of the package substrate 150, the assembly is inverted, and the first carrier 604-1 is removed from the assembly in Figure 6C.

[0061] FIG6E shows the assembly after RDL 148 is formed on the top surface of the assembly of FIG6D. RDL 148 may include a second conductive path 109-2 and a third conductive path 109-3. RDL 148 may include conductive contacts on the bottom surface and conductive contacts on the top surface of RDL 148. The first microelectronic component 102 and the second microelectronic component 103 may be electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 via conductive contacts on the bottom surface of RDL 148. Any suitable technology can be used to manufacture RDL 148, such as PCB technology or redistribution technology.

[0062] FIG. 6F illustrates the assembly after the fourth microelectronic component 101 has been placed and electrically coupled to the top surface of the RDL 148. The fourth microelectronic component 101 can be placed and electrically coupled using any suitable technique. For example, in some embodiments, solder paste can be printed onto conductive contacts on the top surface of the RDL 148, and the fourth microelectronic component 101 can be placed onto the solder paste using a pick-and-place tool. The solder paste can be heat-reflowed and cleaned. The fourth microelectronic component 101 can be electrically coupled to a second conductive path 109-2 and / or a third conductive path 109-3 via conductive contacts on the top surface of the RDL 148. The assembly of FIG. 6F can itself be a microelectronic assembly 100, as shown. Other manufacturing operations can be performed on the microelectronic assembly 100 of FIG. 6F to form other microelectronic assemblies 100, such as those shown in FIG. 6G.

[0063] Figure 6G shows an assembly similar to the microelectronic assembly 100 of Figure 1 after the removal of the second carrier 604-2, the deposition of solder mask, the attachment of solder balls, the electrical coupling of the circuit board 182 to the package substrate 150 via SLI 181, and the provision of a heat transfer structure 135 on the top surface of the assembly of Figure 6F. The first conductive path 109-1 can be electrically coupled to a power supply 183 on the circuit board 182 via SLI 181. If multiple microelectronic assemblies 100 are fabricated together, the microelectronic assembly 100 can be monolithically assembled after the removal of the second carrier 604-2.

[0064] Additionally, although a particular microelectronic assembly 100 is shown in Figures 6A through 6G (and others in the accompanying drawings illustrating the manufacturing process), the operations discussed below with reference to Figures 6A through 6G can be used to form any suitable microelectronic assembly 100. For example, the operations discussed above with reference to Figures 6A through 6G can be used to form the microelectronic assemblies 100 of Figures 2, 3, and 4 by placing a first microelectronic component 102 and / or a second microelectronic component 103 on a first carrier 604-1 and by placing and coupling additional components (e.g., capacitor element 107B of Figure 3 and second microelectronic component 103 of Figure 4) on the top surface of RDL 148 as described in Figure 6F, wherein the active surface 123 faces the first carrier 604-1, as described in Figure 6B. The capacitor element 107 of Figure 4 can be coupled to the bottom surface of the package substrate 150, as described below with reference to Figure 11E.

[0065] Figures 7A to 7G are side cross-sectional views of various stages in a process for manufacturing the microelectronic assembly 100 of Figure 1 according to various embodiments. Figure 7A shows the first microelectronic assembly 102 having TSV 113 and the second microelectronic assembly 103 having TSV 117 after removing non-electrical material from the back surface (e.g., the back surface opposite the active surface 123), exposing the top surface of TSVs 113 and 117, and forming conductive contacts 122 on the top surfaces of the first microelectronic assembly 102 and the second microelectronic assembly 103. Figure 7A further shows the first microelectronic assembly 102, the second microelectronic assembly 103, and the third microelectronic assembly 105 having conductive contacts 121 at the active surface 123. The first microelectronic assembly 102, the second microelectronic assembly 103, and the third microelectronic assembly 105 may be processed as described above with reference to Figure 6A.

[0066] FIG. 7B illustrates the assembly after the encapsulation substrate 150 is formed on the surface of the first carrier 704-1. The encapsulation substrate 150 may include a first conductive path 109-1. The encapsulation substrate 150 may be formed using any suitable technique, such as any of the techniques discussed above regarding the formation of the encapsulation substrate 150 with reference to FIG. 1. The carrier 704 may include any suitable material and, in some embodiments, may include a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel).

[0067] FIG7C illustrates the assembly after a first microelectronic component 102, a second microelectronic component 103, and a third microelectronic component 105 are placed on a package substrate 150, an insulating material 133 is deposited on and around the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 are electrically coupled to the package substrate 150 via an FLI 151, wherein the active surface 123 faces the package substrate 150 (e.g., the active surface 123 faces the first surface 170-1). The first microelectronic component 102 and the second microelectronic component 103 may be electrically coupled to a first conductive path 109-1 via an FLI 151. In some embodiments, the third microelectronic component 105 may also be electrically coupled to the first conductive path 109-1 via an FLI 151. The insulating material 133 may be deposited using any suitable technique, as described above with reference to FIG6.

[0068] FIG7D shows the assembly after mounting the second carrier 704-2 to the top surface of the assembly of FIG7C, inverting the assembly, removing the first carrier 704-1, forming conductive contacts, and performing surface treatment on the surface of the package substrate 150.

[0069] FIG7E shows the assembly after mounting the third carrier 704-3 to the top surface of the assembly of FIG7C, inverting the assembly, removing the second carrier 704-2, and forming RDL 148 on the top surface of the insulating material 133. RDL 148 may include a second conductive path 109-2 and a third conductive path 109-3. RDL 148 may include conductive contacts on the bottom surface and conductive contacts on the top surface of RDL 148. The first microelectronic component 102 and the second microelectronic component 103 may be electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 via conductive contacts on the bottom surface of RDL 148. Any suitable technology can be used to manufacture RDL 148, such as PCB technology or redistribution technology.

[0070] Figure 7F shows the assembly after the fourth microelectronic component 101 has been placed and electrically coupled to the top surface of RDL 148. The fourth microelectronic component 101 can be placed and electrically coupled using any suitable technique, such as that described above with reference to Figure 6. The fourth microelectronic component 101 can be electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 via conductive contacts on the top surface of RDL 148. The assembly of Figure 7F can itself be a microelectronic assembly 100, as shown. Other manufacturing operations can be performed on the microelectronic assembly 100 of Figure 7F to form other microelectronic assemblies 100, such as those shown in Figure 7G.

[0071] Figure 7G shows an assembly similar to the microelectronic assembly 100 of Figure 1 after the removal of the third carrier 704-3, the deposition of solder resist, the attachment of solder balls to the bottom surface of the package substrate 150, the electrical coupling of the bottom surface of the package substrate 150 to the circuit board 182 via SLI 181, and the provision of a heat transfer structure 135 on the top surface of the assembly of Figure 7F. The first conductive path 109-1 can be electrically coupled to a power supply 183 on the circuit board 182 via SLI 181. If multiple microelectronic assemblies 100 are fabricated together, the microelectronic assembly 100 can be monolithically assembled after the removal of the third carrier 704-3.

[0072] Figures 8A to 8H are side cross-sectional views of various stages in a process for manufacturing the microelectronic assembly 100 of Figure 5A according to various embodiments. Figure 8A shows the first microelectronic assembly 102 having TSV 113 and the second microelectronic assembly 103 having TSV 117 after removing non-electrical material from the back surface (e.g., the back surface opposite the active surface 123), exposing the top surface of TSVs 113 and 117, and forming conductive contacts 122 on the top surfaces of the first microelectronic assembly 102 and the second microelectronic assembly 103. Figure 8A further shows the first microelectronic assembly 102, the second microelectronic assembly 103, and the third microelectronic assembly 105 having conductive contacts 121 at the active surface 123. The first microelectronic assembly 102, the second microelectronic assembly 103, and the third microelectronic assembly 105 may be processed as described above with reference to Figure 6A.

[0073] FIG8B shows an insert 185 including a TSV 108 and an embedded capacitor element 107. In some embodiments, the insert 185 may include a passive or active wafer.

[0074] FIG8C illustrates the assembly after placing the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 on the insert 185, depositing insulating material 133 on and around the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105, and electrically coupling the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 to the insert 185. The first microelectronic component 102 and the second microelectronic component 103 may be placed on the insert 185 with the active surface 123 facing away from the insert (e.g., the active surface 123 facing the second surface 170-2), and the third microelectronic component 105 may be placed with the active surface 123 facing the insert 185 (e.g., the active surface 123 facing the first surface 170-1). The insulating material 133 may be deposited using any suitable technique, as described above with reference to FIG6.

[0075] FIG8D illustrates the assembly after RDL 148 is formed on the top surface of insulating material 133 (e.g., on the top surface of the assembly of FIG8C). RDL 148 may include a second conductive path 109-2 and a third conductive path 109-3. RDL 148 may include conductive contacts on the bottom surface and conductive contacts on the top surface of RDL 148. First microelectronic component 102 and second microelectronic component 103 may be electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 via conductive contacts on the bottom surface of RDL 148. Any suitable technology may be used to manufacture RDL 148, such as PCB technology or redistribution technology.

[0076] Figure 8E shows the assembly in the inverted Figure 8D, after material removal from insert 185, exposure of the top surface of TSV 108, and formation of conductive contacts on the top surface of TSV 108 for coupling to package substrate 150. Insert material can be removed using any suitable technique, including grinding.

[0077] FIG8F illustrates the assembly after isomorphizing the assembly of FIG8E and reconstructing it on the carrier 804, forming the package substrate 150 on the surface of the insert 185, forming conductive contacts, attaching solder balls, and performing surface treatment on the surface of the package substrate 150. The package substrate 150 may include a first conductive path 109-1. The package substrate 150 may be formed using any suitable technique, such as any of the techniques discussed above regarding the formation of the package substrate 150 with reference to FIG1. ​​The carrier 804 may include any suitable material and in some embodiments may include a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel).

[0078] FIG8G shows the assembly in the inverted FIG8F, after removing the carrier 804, placing and electrically coupling the fourth microelectronic component 101 to the top surface of RDL 148, and providing the heat transfer structure 135 on the top surface of RDL 148. The fourth microelectronic component 101 can be placed and electrically coupled using any suitable technique, such as that described above with reference to FIG6. The fourth microelectronic component 101 can be electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 via conductive contacts on the top surface of RDL 148.

[0079] Figure 8H shows an assembly after the assembly of Figure 8F is monolithized and the bottom surface of the package substrate 150 is electrically coupled to the circuit board 182 via SLI 181, which is similar to the microelectronic assembly 100 of Figure 5A. The first conductive path 109-1 can be electrically coupled to the power supply 183 on the circuit board 182 via SLI 181.

[0080] Figures 9A to 9I are side cross-sectional views of various stages in a process for manufacturing the microelectronic assembly 100 of Figure 5B according to various embodiments. Figure 9A shows the first microelectronic assembly 102 having TSV 113 and the second microelectronic assembly 103 having TSV 117 after removing non-electrical material from the back surface (e.g., the back surface opposite the active surface 123), exposing the top surface of TSVs 113 and 117, and forming conductive contacts 122 on the top surfaces of the first microelectronic assembly 102 and the second microelectronic assembly 103. Figure 9A further shows the first microelectronic assembly 102, the second microelectronic assembly 103, and the third microelectronic assembly 105 having conductive contacts 121 at the active surface 123. The first microelectronic assembly 102, the second microelectronic assembly 103, and the third microelectronic assembly 105 may be processed as described above with reference to Figure 6A.

[0081] FIG9B shows an insert 185 including a TSV 108 and an embedded capacitor element 107. In some embodiments, the insert 185 may include a passive or active wafer.

[0082] FIG9C illustrates the assembly after material removal from insert 185, exposure of TSV 108, formation of conductive contacts (e.g., conductive pillars 186) on the surface of TSV 108, and mounting of the assembly to the first carrier 904-1, with capacitor element 107 facing away from carrier 904-1. Insert material can be removed using any suitable technique, including grinding. Conductive contacts can be formed on TSV 108 using any suitable technique, including, for example, copper pillar bump bonding. Carrier 904 can include any suitable material and, in some embodiments, can include semiconductor wafers (e.g., silicon wafers) or glass (e.g., glass panels). In some embodiments, when solder 188 is used, solder 188 can be deposited on the surface of the conductive contacts before mounting the assembly to carrier 904-1.

[0083] FIG9D shows the assembly after placing the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 on the insert 185, depositing insulating material 133 on and around the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105, and electrically coupling the first microelectronic component 102, the second microelectronic component 103, and the third microelectronic component 105 to the insert 185. The first microelectronic component 102 and the second microelectronic component 103 may be placed on the insert 185 with the active surface 123 facing away from the insert (e.g., the active surface 123 facing the second surface 170-2), and the third microelectronic component 105 may be placed with the active surface 123 facing the insert 185 (e.g., the active surface 123 facing the first surface 170-1). In some embodiments, the first microelectronic component 102 and the second microelectronic component 103 may be disposed on the insert 185, wherein the active surface 123 faces the insert (e.g., the active surface 123 faces the first surface 170-1). The insulating material 133 may be deposited using any suitable technique, as described above with reference to FIG6.

[0084] FIG9E illustrates the assembly after RDL 148 is formed on the top surface of insulating material 133 (e.g., on the top surface of the assembly of FIG9D). RDL 148 may include a second conductive path 109-2 and a third conductive path 109-3. RDL 148 may include conductive contacts on the bottom surface and conductive contacts on the top surface of RDL 148. First microelectronic component 102 and second microelectronic component 103 may be electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 via conductive contacts on the bottom surface of RDL 148. Any suitable technology may be used to manufacture RDL 148, such as PCB technology or redistribution technology.

[0085] Figure 9F shows the assembly after inverting the assembly of Figure 9E and removing the first carrier 904-1.

[0086] Figure 9G shows the assembly after it has been monolithized and reassembled on the second carrier 904-2. In some embodiments, a mold material 189 (not shown) may be used, which may be disposed on and around the assembly of Figure 9F. The mold material 189 may be formed using any suitable process, including compression molding or lamination.

[0087] Figure 9H shows the assembly in the inverted Figure 9G, after removing the second carrier 904-2, placing and electrically coupling the fourth microelectronic component 101 to the top surface of RDL 148, and providing the heat transfer structure 135 on the top surface of RDL 148. The fourth microelectronic component 101 can be placed and electrically coupled using any suitable technique, such as that described above with reference to Figure 6. The fourth microelectronic component 101 can be electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 via conductive contacts on the top surface of RDL 148.

[0088] Figure 9I shows an assembly after the assembly of Figure 9H is monolithized and the bottom surface of the insert 185 is electrically coupled to the circuit board 182 by means of LGA interconnect 187, which is similar to the microelectronic assembly 100 of Figure 5B.

[0089] FIG10 is a side cross-sectional view of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 of FIG10 may have a top-side power delivery path including a TMV 111. The microelectronic assembly 100 of FIG10 may include: a circuit board 182 having a power supply 183 electrically coupled to a package substrate 150 having a first conductive path 109-1; an insulating material 133 on the package substrate having a through-hole (TMV) 111 and a first microelectronic component 102 and a third microelectronic component 105 embedded therein; an RDL 148 on the insulating material 133 having a second conductive path 109-2 and a third conductive path 109-3; and a second microelectronic component 103 mounted on the top surface of the RDL 148. Specifically, the first conductive path 109-1 in the package substrate 150 may be electrically coupled to the power supply 183. TMV 111 is electrically coupled at a first surface 170-1 to a first conductive path 109-1 in the package substrate 150 and at a second surface 170-2 to a second conductive path 109-2 and / or a third conductive path 109-3 in the RDL 148. The first microelectronic component 102 is electrically coupled at a first surface 170-1 to the package substrate 150 and at a second surface 170-2 (e.g., active surface 123) to the second conductive path 109-2 and the third conductive path 109-3 in the RDL 148, such that power can be supplied from the power source 183 to the second surface 170-2 of the first microelectronic component 102. The second microelectronic component 103 is electrically coupled to the first microelectronic component 102 via the second conductive path 109-2 and the third conductive path 109-3 in the RDL 148. In some embodiments, the second conductive path 190-2 and the third conductive path 109-3 are the same conductive path in RDL 148. The third microelectronic component 105 may be electrically coupled to the package substrate 150 at the first surface 170-1 (e.g., active surface 123) and may also be electrically coupled to the first conductive path 109-1. TMV 111 may be made of any suitable conductive material, for example, such as copper, silver, nickel, gold, aluminum or other metals or alloys. TMV 111 may have any suitable dimensions. In some embodiments, TMV 111 may have a diameter (e.g., cross-sectional dimension) between 5 micrometers and 20 micrometers and a thickness (e.g., z-height) between 40 micrometers and 100 micrometers.

[0090] The microelectronic assembly 100 of FIG10 may also include a fourth microelectronic component 101, which is mounted on the top surface of RDL 148 and electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 in RDL 148 (e.g., electrically coupled to the top-side power delivery path). In some embodiments, the fourth microelectronic component 101A may be mounted on the top surface of the second microelectronic component 103 and electrically coupled to the second microelectronic component 103 via a conductive path in RDL 148 (as shown) or via conductive contacts (not shown) on the top and bottom surfaces of the second microelectronic component 103 and the fourth microelectronic component 101, respectively. In some embodiments, the fourth microelectronic component 101B may be mounted adjacent to the second microelectronic component 103 (e.g., side-by-side with it) on the top surface of RDL 148 and electrically coupled to the second microelectronic component 103 via a conductive path in RDL 148. The microelectronic assembly 100 of Figure 10 may further include a capacitor element 107 electrically coupled to a top-side power delivery path. Specifically, the microelectronic assembly 100 may further include a capacitor element 107 electrically coupled to the bottom surface of the package substrate 150 and electrically coupled to a power supply 183 via a first conductive path 109-1.

[0091] Figures 11A to 11G are side cross-sectional views of various stages in a process for manufacturing the microelectronic assembly 100 of Figure 10 according to various embodiments. Figure 11A shows the first microelectronic assembly 102 and the second microelectronic assembly 103 after non-electrical material is removed from the back surface (e.g., the back surface is opposite to the active surface 123) and conductive contacts 122 are formed on the top surfaces of the first microelectronic assembly 102 and the second microelectronic assembly 103. Figure 11A further shows the first microelectronic assembly 102, the second microelectronic assembly 103, and the third microelectronic assembly 105 having conductive contacts 121 at the active surface 123. The first microelectronic assembly 102, the second microelectronic assembly 103, and the third microelectronic assembly 105 may be processed as described above with reference to Figure 6A.

[0092] FIG11B illustrates the assembly after the encapsulation substrate 150 is formed on the surface of the first carrier 1104-1. The encapsulation substrate 150 may include a first conductive path 109-1. The encapsulation substrate 150 may be formed using any suitable technique, such as any of the techniques discussed above regarding the formation of the encapsulation substrate 150 with reference to FIG1. ​​The carrier 1104 may include any suitable material, and in some embodiments may include a semiconductor wafer (e.g., a silicon wafer), a metal (e.g., stainless steel), or glass (e.g., a glass panel).

[0093] FIG11C illustrates the assembly after placing a first microelectronic component 102 on a package substrate 150 (with the active surface 123 facing away from the package substrate 150 (e.g., the active surface 123 facing the second surface 170-2)), placing a third microelectronic component 105 on the package substrate 150 (with the active surface 123 facing the package substrate 150 (e.g., the active surface 123 facing the first surface 170-1)), forming a TMV 111 on a first conductive path 109-1, depositing an insulating material 133 on and around the TMV 111 and the first microelectronic component 102 and the third microelectronic component 105, and electrically coupling the first microelectronic component 102 and the third microelectronic component 105 to the package substrate 150 via an FLI 151. The insulating material 133 can be deposited using any suitable technique, as described above with reference to FIG6. TMV 111 can be formed using any suitable technique, including lithography or additive processes such as cold spraying or 3D printing. For example, TMV 111 can be formed by depositing, exposing, and developing a photoresist layer on the top surface of the first conductive path 109-1. The photoresist layer can be patterned to form cavities in the shape of TMV 111. A conductive material, such as copper, can be deposited in the openings in the patterned photoresist layer to form TMV 111. Any suitable process can be used to deposit the conductive material, such as electroplating, sputtering, or electrodeless plating. The photoresist can be removed to expose TMV 111. In another example, a photoimageable dielectric can be used to form TMV 111. In some embodiments, a seed layer (not shown) can be formed on the top surface of the first conductive path 109-1 before the deposition of the photoresist and conductive material. The seed layer can be any suitable conductive material, including copper. The seed layer can be removed using any suitable process after the photoresist layer is removed, including chemical etching and other processes. In some embodiments, the seed layer may be omitted.

[0094] FIG11D shows the assembly after the second carrier 1104-2 is mounted to the top surface of the assembly of FIG11C, the assembly is inverted, the first carrier 1104-1 is removed, conductive contacts are formed, capacitor element 107 is attached, solder ball 181 is attached, and surface treatment is performed on the bottom surface of the package substrate 150.

[0095] Figure 11E illustrates the assembly of the inverted Figure 11D, after the removal of the second carrier 704-2 and the formation of RDL 148 on the top surface of the insulating material 133. RDL 148 may include a second conductive path 109-2 and a third conductive path 109-3. RDL 148 may include conductive contacts on the bottom surface and conductive contacts on the top surface of RDL 148. The first microelectronic component 102 and the second microelectronic component 103 may be electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 via conductive contacts on the bottom surface of RDL 148. Any suitable technology may be used to manufacture RDL 148, such as PCB technology or redistribution technology.

[0096] FIG11F illustrates the assembly after the second microelectronic component 103 and the fourth microelectronic component 101 are placed and electrically coupled to the top surface of RDL 148. The second microelectronic component 103 and the fourth microelectronic component 101 can be placed and electrically coupled using any suitable technique, such as that described above with reference to FIG6. The second microelectronic component 103 and the fourth microelectronic component 101 can be electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 via conductive contacts on the top surface of RDL 148. In some embodiments, the fourth microelectronic component 101A can be mounted on the top surface of the second microelectronic component 103 and electrically coupled to the second microelectronic component 103 via conductive paths in RDL 148 (as shown) or via conductive contacts (not shown) on the top and bottom surfaces of the second microelectronic component 103 and the fourth microelectronic component 101, respectively. In some embodiments, the fourth microelectronic component 101B may be mounted adjacent to (e.g., alongside) the second microelectronic component 103 on the top surface of the RDL 148 and electrically coupled to the second microelectronic component 103 via conductive paths in the RDL 148. The assembly of FIG11F may itself be a microelectronic assembly 100, as shown. Other manufacturing operations may be performed on the microelectronic assembly 100 of FIG11F to form other microelectronic assemblies 100, such as those shown in FIG11G.

[0097] Figure 11G shows the assembly after the bottom surface of the package substrate 150 is electrically coupled to the circuit board 182 via SLI 181 and the heat transfer structure 135 is disposed on the top surface of the assembly of Figure 11F, which is similar to the microelectronic assembly 100 of Figure 10. The first conductive path 109-1 can be electrically coupled to the power supply 183 on the circuit board 182 via SLI 181.

[0098] Figures 12A and 12B are side cross-sectional views of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 of Figures 12A and 12B may have a top-side power delivery path including a TMV 111 along the periphery. The microelectronic assembly 100 of Figure 12A may include: a circuit board 182 having a power supply 183 electrically coupled to a package substrate 150 having a first conductive path 109-1; an insulating material 133 on the package substrate having a through-hole (TMV) 111 and embedded therein a first microelectronic component 102, a second microelectronic component 103, and a third microelectronic component 105; and an RDL 148 on the insulating material 133 having a second conductive path 109-2 and a third conductive path 109-3. Specifically, the first conductive path 109-1 in the package substrate 150 may be electrically coupled to the power supply 183. The TMV 111 is electrically coupled at a first surface 170-1 to a first conductive path 109-1 in the package substrate 150 and at a second surface 170-2 to a second conductive path 109-2 and / or a third conductive path 109-3 in the RDL 148. The TMV 111 can be positioned along the periphery (e.g., outer edge) of the insulating material 133. The first microelectronic component 102 and the second microelectronic component 103 are electrically coupled at a first surface 170-1 (e.g., active surface 123) to the package substrate 150 and at a second surface 170-2 to the second conductive path 109-2 and the third conductive path 109-3 in the RDL 148, such that power can be supplied from the power source 183 to the second surface 170-2 of the first microelectronic component 102. The second surface of the second microelectronic component 103 can be electrically coupled to the second surface of the first microelectronic component 102 via the second conductive path 109-2 and the third conductive path 109-3 in RDL 148. In some embodiments, the second conductive path 190-2 and the third conductive path 109-3 are the same conductive path in RDL 148. The third microelectronic component 105 can be electrically coupled to the package substrate 150 at the first surface 170-1 (e.g., active surface 123) and can also be electrically coupled to the first conductive path 109-1. In some embodiments, the third microelectronic component 105 can be electrically coupled to the package substrate 150 at the first surface 170-1 and electrically coupled to RDL 148 at the second surface 170-2 (e.g., active surface 123). The microelectronic assembly 100 of Figure 12A may also include a fourth microelectronic component 101, which is mounted on the top surface of the RDL 148 and electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 in the RDL 148 (e.g., electrically coupled to the top-side power delivery path).

[0099] FIG12B is a side cross-sectional view of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 of FIG12B may include: a circuit board 182 having a power supply 183 electrically coupled to a package substrate 150 having a first conductive path 109-1; an insulating material 133 on the package substrate having a through-hole (TMV) 111 and a first microelectronic component 102 and a third microelectronic component 105 embedded therein; an RDL 148 on the insulating material 133 having a second conductive path 109-2 and a third conductive path 109-3; and a second microelectronic component 103 mounted on the top surface of the RDL 148. Specifically, the first conductive path 109-1 in the package substrate 150 is electrically coupled to the power supply 183. The TMV 111 is electrically coupled at a first surface 170-1 to a first conductive path 109-1 in the package substrate 150 and at a second surface 170-2 to a second conductive path 109-2 and / or a third conductive path 109-3 in the RDL 148. The TMV 111 can be positioned along the periphery (e.g., outer edge) of the insulating material 133. The first microelectronic component 102 is electrically coupled at a first surface 170-1 to the package substrate 150 and at a second surface 170-2 (e.g., active surface 123) to the second conductive path 109-2 and the third conductive path 109-3 in the RDL 148, such that power can be supplied from the power source 183 to the second surface 170-2 of the first microelectronic component 102. The second microelectronic component 103 can be electrically coupled to the first microelectronic component 102 via a second conductive path 109-2 and / or a third conductive path 109-3 in RDL 148. In some embodiments, the second conductive path 109-2 and the third conductive path 109-3 are the same conductive path in RDL 148. The third microelectronic component 105 can be electrically coupled to the package substrate 150 at a first surface 170-1 (e.g., active surface 123) and can also be electrically coupled to the first conductive path 109-1. In some embodiments, the third microelectronic component 105 can be electrically coupled to the package substrate 150 at the first surface 170-1 and electrically coupled to RDL 148 at a second surface 170-2 (e.g., active surface 123). The microelectronic assembly 100 of Figure 12B may also include a fourth microelectronic component 101, which is mounted on the top surface of the RDL 148 and electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 in the RDL 148 (e.g., electrically coupled to the top-side power delivery path).In some embodiments, the fourth microelectronic component 101A may be mounted on the top surface of the second microelectronic component 103 and electrically coupled to the second microelectronic component 103 via a conductive path in RDL 148 (as shown) or via conductive contacts (not shown) on the top and bottom surfaces of the second and fourth microelectronic components 103, respectively. In some embodiments, the fourth microelectronic component 101B may be mounted adjacent to (e.g., side-by-side with) the second microelectronic component 103 on the top surface of RDL 148 and electrically coupled to the second microelectronic component 103 via a conductive path in RDL 148. The microelectronic assemblies 100 of Figures 12A and 12B may be manufactured using any suitable technology, including, for example, the process described above with reference to Figure 11.

[0100] Figures 13A and 13B are side cross-sectional views of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 of Figures 13A and 13B may have a top-side power delivery path including a bonding wire 112. The microelectronic assembly 100 of Figure 13A may include: a circuit board 182 having a power supply 183 electrically coupled to a package substrate 150 having a first conductive path 109-1; an insulating material 133 on the package substrate having a first microelectronic component 102, a second microelectronic component 103, and a third microelectronic component 105 embedded therein; an RDL 148 on the insulating material 133 having a second conductive path 109-2 and a third conductive path 109-3; and bonding wires electrically coupled to the first conductive path 109-1, the second conductive path 109-2, and / or the third conductive path 109-3. Specifically, the first conductive path 109-1 in the package substrate 150 is electrically coupled to the power supply 183. The bonding wire 112 is electrically coupled to the first conductive path 109-1 in the package substrate 150 and to the second conductive path 109-2 and / or the third conductive path 109-3 in the RDL 148. The bonding wire 112 can be positioned along the periphery (e.g., outer edge) of the package substrate 150 and the RDL 148. The first microelectronic component 102 and the second microelectronic component 103 are electrically coupled to the package substrate 150 at a first surface 170-1 (e.g., active surface 123) and electrically coupled to the second conductive path 109-2 and the third conductive path 109-3 in the RDL 148 at a second surface 170-2, such that power can be supplied from the power supply 183 to the second surface 170-2 of the first microelectronic component 102. The second surface of the second microelectronic component 103 can be electrically coupled to the second surface of the first microelectronic component 102 via the second conductive path 109-2 and / or the third conductive path 109-3 in RDL 148. In some embodiments, the second conductive path 190-2 and the third conductive path 109-3 are the same conductive path in RDL 148. The third microelectronic component 105 can be electrically coupled to the package substrate 150 at the first surface 170-1 (e.g., active surface 123) and can also be electrically coupled to the first conductive path 109-1. In some embodiments, the third microelectronic component 105 can be electrically coupled to the package substrate 150 at the first surface 170-1 and electrically coupled to RDL 148 at the second surface 170-2 (e.g., active surface 123). The microelectronic assembly 100 of Figure 13A may also include a fourth microelectronic component 101, which is mounted on the top surface of the RDL 148 and electrically coupled to a second conductive path 109-2 and / or a third conductive path 109-3 in the RDL 148 (e.g., electrically coupled to a top-side power delivery path). The microelectronic assembly 100 of Figure 13A may also include mold material 189.The mold material 189 may include any suitable material. In some embodiments, the mold material 189 is an organic polymer containing inorganic silica particles. In some embodiments, the mold material 189 is a dielectric material, as described above with reference to the insulating material 133 of FIG1. ​​The mold material 189 may extend around the bonding wire 112, the insulating material 133, the RDL 148, the second microelectronic component 103, and the fourth microelectronic component 101 and extend on the surface of the package substrate 150.

[0101] FIG13B is a side cross-sectional view of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 of FIG13B may have a top-side power delivery path including: a circuit board 182 having a power supply 183 electrically coupled to a package substrate 150 having a first conductive path 109-1; an insulating material 133 on the package substrate having a first microelectronic component 102 and a third microelectronic component 105 embedded therein; an RDL 148 on the insulating material 133 having a second conductive path 109-2 and a third conductive path 109-3; and bonding wires electrically coupled to the first conductive path 109-1, the second conductive path 109-2, and / or the third conductive path 109-3; and a second microelectronic component 103 mounted on the top surface of the RDL 148. Specifically, the first conductive path 109-1 in the package substrate 150 is electrically coupled to the power supply 183. The TMV 111 is electrically coupled at a first surface 170-1 to the first conductive path 109-1 in the package substrate 150 and at a second surface 170-2 to the second conductive path 109-2 and / or the third conductive path 109-3 in the RDL 148. The bonding wire 112 is electrically coupled to the first conductive path 109-1 in the package substrate 150 and to the second conductive path 109-2 and / or the third conductive path 109-3 in the RDL 148. The bonding wire 112 can be positioned along the periphery (e.g., outer edge) of the package substrate 150 and the RDL 148. The first microelectronic component 102 is electrically coupled to the package substrate 150 at a first surface 170-1 and electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 in the RDL 148 at a second surface 170-2 (e.g., active surface 123), so that power can be supplied from the power source 183 to the second surface 170-2 of the first microelectronic component 102. The second microelectronic component 103 is electrically coupled to the first microelectronic component 102 via the second conductive path 109-2 and / or the third conductive path 109-3 in the RDL 148. In some embodiments, the second conductive path 100-2 and the third conductive path 109-3 are the same conductive path in the RDL 148. The third microelectronic component 105 is electrically coupled to the package substrate 150 at the first surface 170-1 (e.g., active surface 123) and is also electrically coupled to the first conductive path 109-1. In some embodiments, the third microelectronic component 105 may be electrically coupled to the package substrate 150 at a first surface 170-1 and electrically coupled to the RDL 148 at a second surface 170-2 (e.g., active surface 123).The microelectronic assembly 100 of Figure 13B may also include a fourth microelectronic component 101, which is mounted on the top surface of RDL 148 and electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 in RDL 148 (e.g., electrically coupled to the top-side power delivery path). In some embodiments, the fourth microelectronic component 101A may be mounted on the top surface of the second microelectronic component 103 and electrically coupled to the second microelectronic component 103 via a conductive path in RDL 148 (as shown) or via conductive contacts (not shown) on the top and bottom surfaces of the second and fourth microelectronic components 101, respectively. In some embodiments, the fourth microelectronic component 101B may be mounted adjacent to (e.g., side-by-side with) the second microelectronic component 103 on the top surface of RDL 148 and electrically coupled to the second microelectronic component 103 via a conductive path in RDL 148. The microelectronic assembly 100 of Figure 13B may also include a mold material 189. The mold material 189 may extend around the bonding wire 112, the insulating material 133, the RDL 148, the second microelectronic component 103 and the fourth microelectronic component 101 and extend on the surface of the package substrate 150.

[0102] Figures 14A to 14I are side cross-sectional views of various stages in an example manufacturing process for the microelectronic assembly 100 of Figure 13B according to various embodiments. Figure 6A shows a first microelectronic component 102, a second microelectronic component 103, and a third microelectronic component 105 having a conductive contact 121 at an active surface 123 and a conductive contact 122 at a back surface.

[0103] FIG14B illustrates the assembly after the first microelectronic component 102 and the third microelectronic component 105 are placed on the first carrier 1404-1 and the insulating material 133 is deposited on and around the first microelectronic component 102 and the third microelectronic component 105, wherein the active surface 123 faces away from the first carrier 1404-1. The carrier 1404 may include any suitable material and in some embodiments may include a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel). The first microelectronic component 102 and the third microelectronic component 105 may be attached to the first carrier 1404-1, and the insulating material 133 may be deposited using any suitable technique as described above with reference to FIG6.

[0104] Figure 14C shows the assembly after RDL 148 is formed on the top surface of the assembly of Figure 14B. RDL 148 may include a second conductive path 109-2 and a third conductive path 109-3. RDL 148 may include conductive contacts on the bottom surface and conductive contacts on the top surface of RDL 148. The first microelectronic component 102 and the third microelectronic component 105 may be electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 via conductive contacts on the bottom surface of RDL 148. Any suitable technology can be used to manufacture RDL 148, such as PCB technology or redistribution technology.

[0105] FIG14D shows the assembly after the encapsulation substrate 150 is formed on the surface of the second carrier 1404-2. The encapsulation substrate 150 may include a first conductive path 109-1. The encapsulation substrate 150 may be formed using any suitable technique, such as any of the techniques discussed above regarding the formation of the encapsulation substrate 150 with reference to FIG1.

[0106] Figure 14E shows the assembly after the first carrier 1402-1 is removed from the assembly of Figure 14C, the first microelectronic component 102 and the third microelectronic component 105 are electrically coupled to the package substrate 150 via FLI 151, and the second carrier 1404-2 is removed from the assembly of Figure 14D.

[0107] Figure 14F shows the assembly after attaching and electrically coupling the bonding wire 112 to the first conductive path 109-1 in the package substrate 150 and the second conductive path 109-2 and / or the third conductive path 109-3 in the RDL 148.

[0108] FIG14G illustrates the assembly after the second microelectronic component 103 and the fourth microelectronic component 101 are placed and electrically coupled to the top surface of RDL 148. The second microelectronic component 103 and the fourth microelectronic component 101 can be placed and electrically coupled using any suitable technique as described above with reference to FIG6. The second microelectronic component 103 and the fourth microelectronic component 101 can be electrically coupled to the second conductive path 109-2 and / or the third conductive path 109-3 via conductive contacts on the top surface of RDL 148. In some embodiments, the fourth microelectronic component 101A can be mounted on the top surface of the second microelectronic component 103 and electrically coupled to the second microelectronic component 103 via conductive paths in RDL 148 (as shown) or via conductive contacts (not shown) on the top and bottom surfaces of the second microelectronic component 103 and the fourth microelectronic component 101, respectively. In some embodiments, the fourth microelectronic component 101B may be mounted adjacent to the second microelectronic component 103 (e.g., side by side) on the top surface of the RDL 148 and electrically coupled to the second microelectronic component 103 via conductive paths in the RDL 148.

[0109] Figure 14H shows the assembly after the mold material 189 has been placed on and around the assembly of Figure 14G. The mold material 189 may extend around the bonding wire 112, the insulating material 133, the RDL 148, the second microelectronic component 103, and the fourth microelectronic component 101 and extend on the surface of the package substrate 150. The mold material 189 may be formed using any suitable process, including lamination or compression molding. The assembly of Figure 14H may itself be a microelectronic assembly 100, as shown. Other manufacturing operations may be performed on the microelectronic assembly 100 of Figure 14H to form other microelectronic assemblies 100, such as those shown in Figure 14I.

[0110] Figure 14I shows an assembly after depositing a solder resist layer and attaching solder balls to the bottom surface of the package substrate 150, electrically coupling the bottom surface of the package substrate 150 to the circuit board 182 via SLI 181, and providing a heat transfer structure 135 on the top surface of the assembly of Figure 14H, which is similar to the microelectronic assembly 100 of Figure 13B.

[0111] The microelectronic assembly 100 disclosed herein can be used in any suitable application. For example, in some embodiments, the microelectronic assembly 100 can be used to implement very small form factor voltage regulation, particularly in mobile devices and small form factor devices, in field programmable gate arrays (FPGAs) or processing units (e.g., central processing units, graphics processing units, FPGAs, modems, application processors, etc.).

[0112] The microelectronic assembly 100 disclosed herein may be included in any suitable electronic component. Figures 15 to 18 illustrate various examples of devices that may include or be included in any of the microelectronic assemblies 100 disclosed herein.

[0113] FIG. 15 is a top view of a wafer 1500 and a die 1502 that may be included in any of the microelectronic components 101, 102, 103, and 105 disclosed herein. For example, the die 1502 may serve as a microelectronic component or may be included in a microelectronic component. The wafer 1500 may be composed of semiconductor material and may include one or more dies 1502 having an IC structure formed on the surface of the wafer 1500. Each of the dies 1502 may be a repeating unit of a semiconductor product including any suitable IC. After the semiconductor product is manufactured, the wafer 1500 may undergo a monolithic process in which the dies 1502 are separated from each other to obtain discrete "wafers" of the semiconductor product. The die 1502 may be any of the microelectronic components 101, 102, 103, and 105 disclosed herein. Die 1502 may include one or more transistors (e.g., some of the transistors 1640 in FIG. 16, discussed below) for sending electrical signals to transistors, supporting circuitry of passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other IC components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM), magnetic RAM (MRAM), resistive RAM (RRAM), conductive-bridged RAM (CBRAM), etc.), logic devices (e.g., AND gate, OR gate, inverse AND gate, or inverse OR gate), or any other suitable circuit element. Many of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on the same die 1502 as a processing device (e.g., processing device 1802 of FIG. 18) or other logic configured to store information in the memory devices or execute instructions stored in the memory array. In some embodiments, die 1502 (e.g., microelectronic component 102) may be a central processing unit, a radio frequency chip, a power converter, or a network processor. The various microelectronic assemblies in the microelectronic assembly 100 disclosed herein may be manufactured using a die-to-wafer assembly technique, in which some dies 114 are attached to a wafer 1500 including others among the dies 114 and the wafer 1500 is subsequently monolithized.

[0114] FIG. 16 is a side cross-sectional view of an IC device 1600 that may be included in any of the microelectronic components 101, 102, 103, and 105 disclosed herein. For example, an IC device 1600 (e.g., as part of a die 1502, as described above with reference to FIG. 15) may function as a microelectronic component or may be included in a microelectronic component. One or more of the IC devices 1600 may be included in one or more dies 1502 (FIG. 15). The IC device 1600 may be formed on a die substrate 1602 (e.g., wafer 1500 of FIG. 15) and may be included in a die (e.g., die 1502 of FIG. 15). The die substrate 1602 may be a semiconductor substrate comprising a semiconductor material system including, for example, an n-type or p-type material system (or a combination of both). For example, the grain substrate 1602 may include a crystalline substrate formed, for example, using bulk silicon or silicon-on-insulator (SOI) substructures. In some embodiments, the grain substrate 1602 may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the grain substrate 1602. Although several examples of materials that can form the grain substrate 1602 are described herein, any material that can serve as the basis of the IC device 1600 may be used. The grain substrate 1602 may be a portion of a monomerized grain (e.g., grain 1502 of FIG. 15) or a wafer (e.g., wafer 1500 of FIG. 15).

[0115] The IC device 1600 may include one or more device layers 1604 disposed on a die substrate 1602. Device layer 1604 may include features of one or more transistors 1640 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1602. Device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, gates 1622 for controlling current in the transistors 1640 between S / D regions 1620, and one or more S / D contacts 1624 for sending / receiving electrical signals to / from the S / D regions 1620. Transistors 1640 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, and the like. Transistors 1640 are not limited to the types and configurations depicted in FIG. 16 and may include a variety of other types and configurations, such as planar transistors, non-planar transistors, or combinations thereof. Non-planar transistors may include FinFET transistors, such as dual-gate transistors and tri-gate transistors, and all-around or fully enclosed gate transistors, such as nanoband and nanowire transistors.

[0116] Each transistor 1640 may include a gate 1622 formed of at least two layers (gate dielectric and gate electrode). The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may include elements such as: hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using a high-k material, the gate dielectric may be subjected to an annealing process to improve its quality.

[0117] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or an n-type work function metal, depending on whether the transistor 1640 is a PMOS or NMOS transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a filler metal layer. Other metal layers, such as barrier layers, may be included for other purposes. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below regarding NMOS transistors (e.g., for work function regulation). For NMOS transistors, the metals that can be used as gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of such metals, carbides of such metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide) and any of the metals discussed above for PMOS transistors (e.g., for work function regulation).

[0118] In some embodiments, when a cross-section of the transistor 1640 is viewed along the source-channel-drain direction, the gate electrode may be formed of a U-shaped structure, including a bottom portion substantially parallel to the surface of the grain substrate 1602 and two sidewall portions substantially perpendicular to the top surface of the grain substrate 1602. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the grain substrate 1602 and excluding the sidewall portions substantially perpendicular to the top surface of the grain substrate 1602. In other embodiments, the gate electrode may be formed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be formed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0119] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack supported by a bracket. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. The process for forming the sidewall spacers is well known in the art and typically includes deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0120] The S / D region 1620 may be formed adjacent to the gate 1622 of each transistor 1640 within the grain substrate 1602. The S / D region 1620 may be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic may be implanted into the grain substrate 1602 to form the S / D region 1620. An annealing process to activate the dopant and further diffuse it into the grain substrate 1602 may be performed after the ion implantation process. In the latter process, the grain substrate 1602 may first be etched to form a recess at the location of the S / D region 1620. An epitaxial deposition process may then be performed to fill the recess with the material used to manufacture the S / D region 1620. In some embodiments, the S / D region 1620 may be manufactured using a silicon alloy such as silicon-germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials, such as germanium or group III-V materials or alloys, may be used to form the S / D region 1620. In other embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D region 1620.

[0121] Electrical signals, such as power and / or input / output (I / O) signals, may be transmitted to or from devices of device layer 1604 (e.g., transistor 1640) via one or more interconnect layers (shown as interconnect layers 1606 to 1610 in FIG. 16) disposed on device layer 1604. For example, conductive features of device layer 1604 (e.g., gate 1622 and S / D contact 1624) may be electrically coupled to interconnect structures 1628 of interconnect layers 1606 to 1610. One or more interconnect layers 1606 to 1610 may form a metallization stack (also referred to as an "ILD stack") 1619 of IC device 1600.

[0122] The interconnect structure 1628 may be arranged within the interconnect layers 1606 to 1610 according to various designs to transmit electrical signals; specifically, the arrangement is not limited to the specific configuration of the interconnect structure 1628 depicted in FIG16. Although a specific number of interconnect layers 1606 to 1610 are depicted in FIG16, embodiments of this disclosure include IC devices having more or fewer interconnect layers than depicted.

[0123] In some embodiments, the interconnect structure 1628 may include lines 1628a and / or vias 1628b filled with a conductive material such as metal. Lines 1628a may be arranged to transmit electrical signals in a direction substantially parallel to the plane of the die substrate 1602 on which the device layer 1604 is formed. For example, lines 1628a may transmit electrical signals in directions both inside and outside the page as viewed from FIG. 16. Vias 1628b may be arranged to transmit electrical signals in a direction substantially perpendicular to the plane of the die substrate 1602 on which the device layer 1604 is formed. In some embodiments, vias 1628b may electrically couple lines 1628a of different interconnect layers 1606 to 1610 together.

[0124] Interconnect layers 1606 to 1610 may include dielectric material 1626 disposed between interconnect structures 1628, as shown in FIG16. In some embodiments, the dielectric material 1626 disposed between interconnect structures 1628 in different interconnect layers 1606 to 1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606 to 1610 may be the same.

[0125] A first interconnect layer 1606 (referred to as metal 1 or "M1") may be formed directly above the device layer 1604. In some embodiments, the first interconnect layer 1606 may include a line 1628a and / or a via 1628b, as shown. The line 1628a of the first interconnect layer 1606 may be coupled to a contact (e.g., an S / D contact 1624) of the device layer 1604.

[0126] A second interconnect layer 1608 (referred to as metal 2 or "M2") may be formed directly above the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b for coupling lines 1628a of the second interconnect layer 1608 to lines 1628a of the first interconnect layer 1606. Although for clarity, lines 1628a and vias 1628b are structurally demarcated within each interconnect layer (e.g., within the second interconnect layer 1608), lines 1628a and vias 1628b may be structurally and / or materially continuous in some embodiments (e.g., simultaneously filled during a bimetallic damascene process).

[0127] The third interconnect layer 1610 (referred to as metal 3 or "M3") (and additional interconnect layers, as needed) may be continuously formed on the second interconnect layer 1608 according to similar techniques and configurations described in conjunction with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers "higher up" (i.e., farther from the device layer 1604) in the metallization stack 1619 in the IC device 1600 may be thicker.

[0128] The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or a similar material) and one or more conductive contacts 1636 formed on interconnect layers 1606 to 1610. In FIG. 16, the conductive contacts 1636 are shown in the form of bonding pads. The conductive contacts 1636 may be electrically coupled to interconnect structure 1628 and configured to transmit electrical signals of one or more transistors 1640 to another external device. For example, solder bonding may be formed on one or more conductive contacts 1636 to mechanically and / or electrically couple a chip including the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 may include additional or alternative structures for transmitting electrical signals from interconnect layers 1606 to 1610; for example, the conductive contacts 1636 may include other similar morphologies (e.g., pillars) for transmitting electrical signals to external components.

[0129] In some embodiments of the IC device 1600 with dual-sided dies (e.g., similar to microelectronic component 102-1), the IC device 1600 may include another metallization stack (not shown) on the opposite side of the device layer 1604. This metallization stack may include multiple interconnect layers as discussed above with reference to interconnect layers 1606 to 1610 to provide a conductive path (e.g., including conductive lines and vias) between the device layer 1604 and an additional conductive contact (not shown) on the side of the IC device 1600 opposite to the conductive contact 1636.

[0130] In other embodiments of the IC device 1600 with a dual-sided die (e.g., similar to microelectronic component 102-1), the IC device 1600 may include one or more TSVs passing through the die substrate 1602; these TSVs may contact one or more device layers 1604 and provide a conductive path between the device layer 1604 and additional conductive contacts (not shown) on the side of the IC device 1600 opposite to the conductive contact 1636.

[0131] FIG17 is a cross-sectional side view of an IC device assembly 1700 that may include any of the microelectronic components 101, 102, 103, 105 and / or microelectronic assemblies 100 disclosed herein. In some embodiments, the IC device assembly 1700 may be a microelectronic assembly 100. The IC device assembly 1700 includes several components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first surface 1740 and an opposite second surface 1742 of the circuit board 1702; generally, components may be disposed on one or both of surfaces 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 may take the form of any suitable embodiment of the microelectronic assembly 100 disclosed herein.

[0132] In some embodiments, the circuit board 1702 may be a PCB comprising a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers may be patterned to transmit electrical signals between components coupled to the circuit board 1702 (optionally combined with other metal layers). In other embodiments, the circuit board 1702 may be a non-PCB substrate. In some embodiments, the circuit board 1702 may be, for example, a circuit board.

[0133] The IC device assembly 1700 shown in FIG17 includes a package-on-interposer structure 1736 coupled to a first side 1740 of a circuit board 1702 via a coupling assembly 1716. The coupling assembly 1716 can electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702, and may include solder balls (as shown in FIG17), male and female portions of the socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0134] The on-mount package structure 1736 may include an IC package 1720 coupled to the insert 1704 via a coupling component 1718. The coupling component 1718 may be in any suitable form for the application, such as the form discussed above with reference to coupling component 1716. Although a single IC package 1720 is shown in FIG. 17, multiple IC packages may be coupled to the insert 1704; in fact, additional inserts may be coupled to the insert 1704. The insert 1704 may provide an interposer substrate for bridging the circuit board 1702 and the IC package 1720. The IC package 1720 may be or include, for example, a die (die 1502 of FIG. 15), an IC device (e.g., IC device 1600 of FIG. 16), or any other suitable component. Generally, the insert 1704 may be extended to a wider pitch or redirected to different connections. For example, insert 1704 can couple IC package 1720 (e.g., a die) to a set of ball grid array (BGA) conductive contacts of coupling assembly 1716 for coupling to circuit board 1702. In the embodiment shown in FIG. 17, IC package 1720 and circuit board 1702 are attached to opposite sides of insert 1704; in other embodiments, IC package 1720 and circuit board 1702 may be attached to the same side of insert 1704. In some embodiments, three or more components may be interconnected by means of insert 1704.

[0135] In some embodiments, the insert 1704 may be formed as a PCB comprising a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the insert 1704 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin containing inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, the insert 1704 may be formed of an alternative rigid or flexible material that may include the same materials used in semiconductor substrates (such as silicon, germanium, and other Group III-V and Group IV materials). The insert 1704 may include metal interconnects 1708 and vias 1710, including but not limited to TSV 1706. The insert 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, can also be formed on the insert 1704. The on-insert package structure 1736 can take the form of any of the on-insert package structures known in the art.

[0136] The IC device assembly 1700 may include an IC package 1724 coupled to a first side 1740 of the circuit board 1702 via a coupling component 1722. The coupling component 1722 may take the form of any of the embodiments described above with reference to the coupling component 1716, and the IC package 1724 may take the form of any of the embodiments described above with reference to the IC package 1720.

[0137] The IC device assembly 1700 shown in FIG. 17 includes a stacked package structure 1734 coupled to a second side 1742 of a circuit board 1702 via a coupling component 1728. The stacked package structure 1734 may include an IC package 1726 and an IC package 1732, which are coupled together via a coupling component 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may be in the form of any of the embodiments of the coupling component 1716 discussed above, and the IC packages 1726 and 1732 may be in the form of any of the embodiments of the IC package 1720 discussed above. The stacked package structure 1734 may be configured according to any of the stacked package structures known in the art.

[0138] FIG18 is a block diagram of an example electrical device 1800 that may include any of the microelectronic components 101, 102, 103, 105 and / or microelectronic assemblies 100 disclosed herein. For example, any suitable component of the electrical device 1800 may include one or more of the IC device assembly 1700, IC device 1600 or die 1502 disclosed herein, and may be arranged in any of the microelectronic assemblies 100 disclosed herein. FIG18 shows a plurality of components, such as those included in the electrical device 1800, but any one or more of these components may be omitted or copied as applicable to this application. In some embodiments, some or all of the components included in the electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-a-chip (SoC) die.

[0139] Additionally, in various embodiments, electrical device 1800 may not include one or more of the components shown in FIG. 18, but electrical device 1800 may include interface circuitry systems for coupling to one or more components. For example, electrical device 1800 may not include display device 1806, but may include display device interface circuitry systems (e.g., connector and driver circuitry systems) to which display device 1806 may be coupled. In another set of examples, electrical device 1800 may not include audio input device 1824 or audio output device 1808, but may include audio input or output device interface circuitry systems (e.g., connector and support circuitry systems) to which audio input device 1824 or audio output device 1808 may be coupled.

[0140] Electrical device 1800 may include processing device 1802 (e.g., one or more processing devices). As used herein, the terms "processing device" or "processor" may refer to any device or part of a device that processes electronic data from a register and / or memory to convert that electronic data into other electronic data that can be stored in the register and / or memory. Processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing device. Electrical device 1800 may include memory 1804, which itself may include one or more memory devices, such as electrically dependent memory (e.g., dynamic random access memory (DRAM)), non-electrically dependent memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives. In some embodiments, memory 1804 may include memory that shares a die with processing device 1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0141] In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communications for transmitting data from and to the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., which may transmit data by using modulated electromagnetic radiation that passes through a non-solid medium. This term does not imply that the associated device does not contain any wires, although in some embodiments such devices may not contain wires.

[0142] The communication chip 1812 can implement any of several wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) initiatives, and any amendments, updates, and / or revisions (e.g., Advanced LTE initiatives, Ultra Mobile Broadband (UMB) initiatives (also known as "3GPP2"), etc.). IEEE 802.16 compliant broadband wireless access (BWA) networks are commonly referred to as WiMAX networks (an acronym for Global Microwave Access), which is a mark of a product that has passed the conformance and interoperability testing of the IEEE 802.16 standard. The communication chip 1812 may operate according to Global System for Mobile Communications (GSM), Universal Packet Radio Service (GPRS), Global System for Mobile Telecommunications (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 1812 may operate according to Enhanced GSM Evolved Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Wireless Telecommunications (DECT), Evolved Data Optimization (EV-DO), its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the communication chip 1812 may operate according to other wireless protocols. The electrical device 1800 may include an antenna 1822 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0143] In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As mentioned above, the communication chip 1812 may include multiple communication chips. For example, a first communication chip 1812 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to long-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or other long-range wireless communications. In some embodiments, the first communication chip 1812 may be dedicated to wireless communications, and the second communication chip 1812 may be dedicated to wired communications.

[0144] Electrical device 1800 may include a battery / power circuit system 1814. The battery / power circuit system 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of electrical device 1800 to one or more energy sources (e.g., AC line power) that are separate from electrical device 1800.

[0145] Electrical device 1800 may include display device 1806 (or a corresponding interface circuit system, as discussed above). Display device 1806 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0146] The electrical device 1800 may include an audio output device 1808 (or a corresponding interface circuit system, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as a speaker, headphones, or earphones.

[0147] Electrical device 1800 may include audio input device 1824 (or a corresponding interface circuit system, as discussed above). Audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0148] The electrical device 1800 may include a GPS device 1818 (or a corresponding interface circuit system, as discussed above). The GPS device 1818 may communicate with a satellite-based system and may receive the location of the electrical device 1800, as is known in the art.

[0149] The electrical device 1800 may include another output device 1810 (or a corresponding interface circuit system, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0150] Electrical device 1800 may include another input device 1820 (or a corresponding interface circuit system, as discussed above). Examples of another input device 1820 may include an accelerometer, gyroscope, compass, image capturing device, keyboard, cursor control device such as a mouse, stylus, touchpad, barcode reader, quick-response (QR) code reader, any sensor, or radio frequency identification (RFID) reader.

[0151] The electrical device 1800 may have desired form factors, such as a computing device or a handheld, portable, or mobile computing device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, notebook computer, mini-notebook computer, ultrabook computer, personal digital assistant (PDA), super mobile personal computer, etc.), a desktop electrical device, a server or other network-connected computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the electrical device 1800 may be any other electronic device for processing data.

[0152] The following paragraphs provide various examples of the embodiments disclosed herein.

[0153] Embodiment 1 is a microelectronic assembly, comprising: a package substrate having a surface including a first conductive path electrically coupled to a power source; an insulating material on the surface of the package substrate; a first microelectronic component having a first surface and an opposing second surface, embedded in the insulating material, the first surface facing the package substrate; a second microelectronic component having a first surface and an opposing second surface, embedded in the insulating material, the first surface facing the package substrate; a redistribution layer (RDL) on the insulating material, including a second conductive path electrically coupled to the second surface of the second microelectronic component and the second surface of the first microelectronic component; and bonding wires electrically coupled to the first conductive path and the second conductive path.

[0154] Example 2 may include the object of Example 1, and may further specify the first surface of the first microelectronic component as the active side and the second surface of the first microelectronic component as the back side.

[0155] Example 3 may include the object of Example 1, and may further specify the first surface of the first microelectronic component as the back side and the second surface of the first microelectronic component as the active side.

[0156] Example 4 may include the object of Example 1, and may further specify the first surface of the second microelectronic component as the active side and the second surface of the second microelectronic component as the back side.

[0157] Example 5 may include the object of Example 4, and may further specify the first surface of the second microelectronic component as the back side and the second surface of the second microelectronic component as the active side.

[0158] Example 6 may include the object of Example 1, and may further specify that the RDL has a first surface and an opposite second surface and an insulating material at the first surface of the RDL, and may further include an inductor at the second surface of the RDL and electrically coupled to a second conductive path.

[0159] Example 7 may include the object of Example 6, and may further include a capacitor element between the inductor and the second surface of the RDL, wherein the capacitor element is electrically coupled to the inductor and electrically coupled to the second conductive path.

[0160] Example 8 may include the object of Example 6 and may further include a capacitor element having a first surface and an opposite second surface, located between the inductor and the second surface of RDL, wherein the capacitor element is electrically coupled to a second conductive path at the first surface and electrically coupled to the inductor at the second surface.

[0161] Example 9 may include the object of Example 1, and may further specify that the surface of the package substrate is a second surface and the package substrate further includes a surface opposite to the first surface, and may further include a circuit board electrically coupled to the first surface of the package substrate, wherein the power supply is on the circuit board.

[0162] Example 10 may include the object of Example 9, and may further include a capacitor element located on a first surface of the package substrate and electrically coupled to a first conductive path.

[0163] Example 11 may include the object of Example 1 and may further include a heat transfer structure at the second surface of the RDL.

[0164] Example 12 may include the object of Example 1, and may further specify that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

[0165] Example 13 may include the object of Example 1, and may further specify a second microelectronic component as a voltage regulator.

[0166] Example 14 may include the object of Example 13, and may further specify that the voltage regulator is configured to convert a low current high voltage signal into a low voltage high current signal.

[0167] Example 15 is a microelectronic assembly comprising: a circuit board including a power supply; a package substrate having a first surface and an opposing second surface, situated on the circuit board and including a first conductive path electrically coupled to the power supply, wherein the first surface faces the circuit board; a first microelectronic component having a first surface and an opposing second surface, embedded in a mold material on the second surface of the package substrate; a redistributable layer (RDL) having a first surface and an opposing second surface, situated on the mold material, including a second conductive path, wherein the first surface faces the mold material; a second microelectronic component situated on the second surface of the RDL and electrically coupled to the second conductive path, wherein the conductive path electrically couples the second microelectronic component and the second surface of the first microelectronic component; and a bonding wire electrically coupled to the first conductive path and the second conductive path.

[0168] Example 16 may include the object of Example 15, and may further specify the first surface of the first microelectronic component as the active side and the second surface of the first microelectronic component as the back side.

[0169] Example 17 may include the object of Example 15, and may further specify the first surface of the first microelectronic component as the back side and the second surface of the first microelectronic component as the active side.

[0170] Example 18 may include the object of Example 15 and may further include a third microelectronic component, which is adjacent to the second microelectronic component at the second surface of the RDL and electrically coupled to the second conductive path.

[0171] Example 19 may include the object of Example 15, and may further specify that the second microelectronic component has a first surface and an opposite second surface at the second surface of the RDL, and may further include a third microelectronic component at the second surface of the second microelectronic component and electrically coupled to the second conductive path.

[0172] Example 20 may include the object of Example 15, and may further specify that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

[0173] Example 21 may include the object of Example 15, and may further specify a second microelectronic component as a voltage regulator.

[0174] Example 22 may include the object of Example 21, and may further specify that the voltage regulator is configured to convert a low current high voltage signal into a low voltage high current signal.

[0175] Example 23 may include the object of Example 18, and may further specify a third microelectronic component system inductor.

[0176] Example 24 may include the object of Example 19 and may further specify a third microelectronic component system inductor.

[0177] Example 25 may include the object of Example 15 and may further include a capacitor element located on a first surface of the package substrate and electrically coupled to a first conductive path.

[0178] Example 26 may include the object of Example 15 and may further include a heat transfer structure at the second surface of the RDL.

[0179] Example 27 is a microelectronic assembly comprising: a package substrate having a surface including a first conductive path electrically coupled to a power source; an insulating material on the surface of the package substrate; a first microelectronic component having a first surface and an opposing second surface embedded in the insulating material, wherein the first surface faces the package substrate; a second microelectronic component having a first surface and an opposing second surface embedded in the insulating material, wherein the first surface faces the package substrate; a through-hole (TMV) positioned along the periphery of the insulating material, extending through the insulating material and electrically coupled to the first conductive path; and a redistribution layer (RDL) on the insulating material, the redistribution layer including a second conductive path electrically coupled to the TMV, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.

[0180] Example 28 may include the object of Example 27, and may further specify the first surface of the first microelectronic component as the active side and the second surface of the first microelectronic component as the back side.

[0181] Example 29 may include the object of Example 27, and may further specify the first surface of the first microelectronic component as the back side and the second surface of the first microelectronic component as the active side.

[0182] Example 30 may include the object of Example 27, and may further specify the first surface of the second microelectronic component as the active side and the second surface of the second microelectronic component as the back side.

[0183] Example 31 may include the object of Example 30, and may further specify the first surface of the second microelectronic component as the back side and the second surface of the second microelectronic component as the active side.

[0184] Example 32 may include the object of Example 27, and may further specify that the RDL has a first surface and an opposite second surface and an insulating material at the first surface of the RDL, and may further include an inductor at the second surface of the RDL and electrically coupled to a second conductive path.

[0185] Example 33 may include the object of Example 32, and may further include: a capacitor element between the inductor and the second surface of the RDL, wherein the capacitor element is electrically coupled to the inductor and electrically coupled to the second conductive path.

[0186] Example 33B may include the object of Example 32 and may further include a capacitor element having a first surface and an opposite second surface, located between the inductor and the second surface of RDL, wherein the capacitor element is electrically coupled to a second conductive path at the first surface and electrically coupled to the inductor at the second surface.

[0187] Example 34 may include the object of Example 27, and may further specify that the surface of the package substrate is a second surface and the package substrate further includes a surface opposite to the first surface, and may further include a circuit board electrically coupled to the first surface of the package substrate, wherein the power supply is on the circuit board.

[0188] Example 35 may include the object of Example 34, and may further include a capacitor element located on a first surface of the package substrate and electrically coupled to a first conductive path.

[0189] Example 36 may include the object of Example 27 and may further include a heat transfer structure at the second surface of the RDL.

[0190] Example 37 may include the object of Example 27, and may further specify that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

[0191] Example 38 may include the object of Example 27, and may further specify the second microelectronic component as a voltage regulator configured to convert a low-current high-voltage signal into a low-voltage high-current signal.

[0192] Example 39 is a microelectronic assembly comprising: a circuit board including a power supply; a package substrate having a first surface and an opposing second surface, situated on the circuit board and including a first conductive path electrically coupled to the power supply, wherein the first surface faces the circuit board; a first microelectronic component having a first surface and an opposing second surface, embedded in a mold material on the second surface of the package substrate; a through-mold via (TMV) positioned along the periphery of the mold material, extending through the mold material and electrically coupled to the first conductive path; a redistribution layer (RDL) having a first surface and an opposing second surface, situated on the mold material, including a second conductive path electrically coupled to the TMV, wherein the first surface faces the mold material; and a second microelectronic component situated on the second surface of the RDL and electrically coupled to the second conductive path, wherein the second conductive path electrically couples the TMV, the second microelectronic component, and the second surface of the first microelectronic component.

[0193] Example 40 may include the object of Example 39, and may further specify the first surface of the first microelectronic component as the active side and the second surface of the first microelectronic component as the back side.

[0194] Example 41 may include the object of Example 39, and may further specify the first surface of the first microelectronic component as the back side and the second surface of the first microelectronic component as the active side.

[0195] Example 42 may include the object of Example 39 and may further include a third microelectronic component, which is adjacent to the second microelectronic component at the second surface of the RDL and electrically coupled to the second conductive path.

[0196] Example 43 may include the object of Example 39, and may further specify that the second microelectronic component has a first surface and an opposite second surface at the second surface of the RDL, and may further include a third microelectronic component at the second surface of the second microelectronic component and electrically coupled to the second conductive path.

[0197] Example 44 may include the object of Example 39, and may further specify that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

[0198] Example 45 may include the object of Example 39, and may further specify a second microelectronic component as a voltage regulator.

[0199] Example 46 may include the object of Example 45, and may further specify that the voltage regulator is configured to convert a low-current high-voltage signal into a low-voltage high-current signal.

[0200] Example 47 may include the object of Example 42, and may further specify a third microelectronic component system inductor.

[0201] Example 48 may include the object of Example 43, and may further specify a third microelectronic component system inductor.

[0202] Example 49 may include the object of Example 39 and may further include a capacitor element located on a first surface of the package substrate and electrically coupled to a first conductive path.

[0203] Example 50 may include the object of Example 39 and may further include a heat transfer structure at the second surface of the RDL.

[0204] Example 51 is a microelectronic assembly comprising: a package substrate having a surface including a first conductive path electrically coupled to a power source; a first microelectronic component having a first surface electrically coupled to the surface of the package substrate and an opposing second surface, embedded in an insulating material on the surface of the package substrate and including a through-substrate via (TSV) electrically coupled to the first conductive path; a second microelectronic component having a first surface electrically coupled to the surface of the package substrate and an opposing second surface, embedded in an insulating material; and a redistribution layer (RDL) on the insulating material including a second conductive path electrically coupled to the TSV, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.

[0205] Example 52 may include the object of Example 51, and may further specify the first surface of the first microelectronic component as the active side and the second surface of the first microelectronic component as the back side.

[0206] Example 53 may include the object of Example 1, and may further specify the first surface of the first microelectronic component as the back side and the second surface of the first microelectronic component as the active side.

[0207] Example 54 may include the object of Example 51, and may further specify that the TSV is a first TSV, and may further include a second TSV in a second microelectronic component, the second TSV being electrically coupled to a first conductive path in the package substrate and electrically coupled to a second conductive path in the RDL.

[0208] Example 55 may include the object of Example 54, and may further specify the first surface of the second microelectronic component as the active side and the second surface of the second microelectronic component as the back side.

[0209] Example 56 may include the object of Example 54, and may further specify the first surface of the second microelectronic component as the back side and the second surface of the second microelectronic component as the active side.

[0210] Example 57 may include the object of Example 51, and may further specify that the insulating material is a first insulating material, and may further include a capacitor element embedded in a second insulating material between the package substrate and the first insulating material and electrically coupled to the first conductive path and TSV.

[0211] Example 58 may include the object of Example 51, and may further specify that the RDL has a first surface and an opposite second surface and an insulating material at the first surface of the RDL, and may further include an inductor at the second surface of the RDL and electrically coupled to a second conductive path.

[0212] Example 59 may include the object of Example 58 and may further include a capacitor element between the inductor and the second surface of the RDL, wherein the capacitor element is electrically coupled to the inductor and electrically coupled to the second conductive path.

[0213] Example 60 may include the object of Example 51, and may further specify that the surface of the package substrate is a second surface and the package substrate further includes a surface opposite to the first surface, and may further include a circuit board electrically coupled to the first surface of the package substrate, wherein the power supply is on the circuit board.

[0214] Example 61 may include the object of Example 60, and may further include a capacitor element located on a first surface of the package substrate and electrically coupled to a first conductive path.

[0215] Example 62 may include the object of Example 51 and may further include a heat transfer structure on the RDL.

[0216] Example 63 may include the object of Example 51, and may further specify that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

[0217] Example 64 may include the object of Example 51, and may further specify the second microelectronic component as a voltage regulator configured to convert a low-current high-voltage signal into a low-voltage high-current signal.

[0218] Example 65 relates to a microelectronic assembly comprising: a package substrate having a surface including a first conductive path electrically coupled to a power source; a first microelectronic component having a first surface electrically coupled to the surface of the package substrate and an opposing second surface, embedded in an insulating material on the surface of the package substrate; a second microelectronic component having a first surface electrically coupled to the surface of the package substrate and an opposing second surface, embedded in an insulating material and including a through-substrate via (TSV) electrically coupled to the first conductive path; and a redistribution layer (RDL) on the insulating material including a second conductive path electrically coupled to the TSV, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.

[0219] Example 66 may include the object of Example 65, and may further specify the first surface of the first microelectronic component as the active side and the second surface of the first microelectronic component as the back side.

[0220] Example 67 may include the object of Example 65, and may further specify the first surface of the first microelectronic component as the back side and the second surface of the first microelectronic component as the active side.

[0221] Example 68 may include the object of Example 65, and may further specify the first surface of the second microelectronic component as the active side and the second surface of the second microelectronic component as the back side.

[0222] Example 69 may include the object of Example 65, and may further specify the first surface of the second microelectronic component as the back side and the second surface of the second microelectronic component as the active side.

[0223] Example 70 may include the object of Example 65, and may further specify that the RDL has a first surface and an opposite second surface and an insulating material at the first surface of the RDL, and may further include an inductor at the second surface of the RDL and electrically coupled to a second conductive path.

[0224] Example 71 may include the object of Example 70 and may further include a capacitor element having a first surface and an opposite second surface, located between the inductor and the second surface of RDL, wherein the capacitor element is electrically coupled to the inductor and electrically coupled to the second conductive path.

[0225] Example 72 may include the object of Example 65 and may further specify that the power supply is mounted on the package substrate.

[0226] Example 73 may include the object of Example 65, and may further specify that the surface of the package substrate is a second surface and the package substrate further includes a surface opposite to the first surface, and may further include a circuit board electrically coupled to the first surface of the package substrate, wherein the power supply is on the circuit board.

[0227] Example 74 may include the object of Example 73 and may further include a capacitor element located on a first surface of the package substrate and electrically coupled to a first conductive path.

[0228] Example 75 may include the object of Example 65 and may further include a heat transfer structure at the second surface of the RDL.

[0229] Example 76 may include the object of Example 65, and may further specify that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

[0230] Example 77 may include the object of Example 65 and may further specify a second microelectronic component as a voltage regulator.

[0231] Example 78 is a microelectronic assembly comprising: a circuit board including a power supply; a package substrate on the circuit board including a first conductive path electrically coupled to the power supply; an insulating material on the package substrate; a first microelectronic component having a first surface and an opposite second surface at the package substrate, embedded in the insulating material and including a first through-substrate via (TSV) electrically coupled to the first conductive path; a second microelectronic component having a first surface and an opposite second surface at the package substrate, embedded in the insulating material and including a second TSV electrically coupled to the first conductive path; and a redistribution layer (RDL) on the insulating material including a second conductive path electrically coupled to the first and second TSVs, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.

[0232] Example 79 may include the object of Example 78, and may further specify the first surface of the first microelectronic component as the active side and the second surface of the first microelectronic component as the back side.

[0233] Example 80 may include the object of Example 78, and may further specify the first surface of the first microelectronic component as the back side and the second surface of the first microelectronic component as the active side.

[0234] Example 81 may include the object of Example 78, and may further specify the first surface of the second microelectronic component as the active side and the second surface of the second microelectronic component as the back side.

[0235] Example 82 may include the object of Example 78, and may further specify the first surface of the second microelectronic component as the back side and the second surface of the second microelectronic component as the active side.

[0236] Example 83 may include the object of Example 78 and may further include a capacitor element that is between the package substrate and the circuit board and electrically coupled to the first conductive path.

[0237] Example 84 may include the object of Example 78 and may further include a heat transfer structure on the RDL.

[0238] Example 85 may include the object of Example 78, and may further specify that the RDL has a first surface and an opposite second surface and an insulating material at the first surface of the RDL, and may further include an inductor at the second surface of the RDL and electrically coupled to a second conductive path.

[0239] Example 86 may include the object of Example 85 and may further include a capacitor element having a first surface and an opposite second surface, located between the inductor and the second surface of RDL, wherein the capacitor element is electrically coupled to the inductor and electrically coupled to the second conductive path.

[0240] Example 87 may include the object of Example 78, and may further specify that the insulating material is a dielectric material or a mold material.

[0241] Example 88 may include the object of Example 78, and may further specify that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

[0242] Example 89 may include the object of Example 78, and may further specify a second microelectronic component as a voltage regulator.

[0243] Example 90 may include the object of Example 89, and may further specify that the voltage regulator is configured to convert a low current high voltage signal into a low voltage high current signal.

[0244] Example 91 may include the object of Example 78 and may further include a third microelectronic component having a first surface electrically coupled to a package substrate and an opposite second surface, embedded in an insulating material and including a third TSV electrically coupled to a first conductive path and a second conductive path.

[0245] Example 92 may include the object of Example 91, and may further specify that the third microelectronic component includes the die of the input and output circuit system.

[0246] Example 93 is a microelectronic assembly comprising: a package substrate having a surface including a first conductive path electrically coupled to a power source; a first microelectronic component having a first surface electrically coupled to the surface of the package substrate and an opposing second surface, embedded in an insulating material on the surface of the package substrate and including a through-substrate via (TSV) electrically coupled to the first conductive path; a redistribution layer (RDL) having a first surface and an opposing second surface on the insulating material, including a second conductive path electrically coupled to the TSV; and a second microelectronic component located at the second surface of the RDL and electrically coupled to the second conductive path, wherein the second conductive path electrically couples the TSV, the second microelectronic component, and the second surface of the first microelectronic component.

[0247] Example 94 may include the object of Example 93, and may further specify the first surface of the first microelectronic component as the active side and the second surface of the first microelectronic component as the back side.

[0248] Example 95 may include the object of Example 93, and may further specify the first surface of the first microelectronic component as the back side and the second surface of the first microelectronic component as the active side.

[0249] Example 96 may include the object of Example 93 and may further include a third microelectronic component, which is adjacent to the second microelectronic component at the second surface of the RDL and electrically coupled to the second conductive path.

[0250] Example 97 may include the object of Example 93, and may further specify that the second microelectronic component has a first surface and an opposite second surface at the second surface of the RDL, and may further include a third microelectronic component at the second surface of the second microelectronic component and electrically coupled to the second conductive path.

[0251] Example 98 may include the object of Example 93, and may further specify that the power supply is mounted on the package substrate.

[0252] Example 99 may include the object of Example 93, and may further specify that the surface of the package substrate is a second surface and the package substrate further includes a circuit board relative to the first surface, and may further include a circuit board electrically coupled to the first surface of the package substrate, wherein the power supply is on the circuit board.

[0253] Example 100 may include the object of Example 99 and may further include a capacitor element located on a first surface of the package substrate and electrically coupled to a first conductive path.

[0254] Example 101 may include the object of Example 93, and may further specify that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

[0255] Example 102 may include the object of Example 93, and may further specify a second microelectronic component as a voltage regulator.

[0256] Example 103 may include the object of Example 102, and may further specify that the voltage regulator is configured to convert a low current high voltage signal into a low voltage high current signal.

[0257] Example 104 may include the object of Example 96, and may further specify a third microelectronic component system inductor.

[0258] Example 105 may include the object of Example 97 and may further specify a third microelectronic component system inductor.

[0259] Example 106 may include the object of Example 93 and may further include a heat transfer structure at the second surface of the RDL.

[0260] Example 107 is a microelectronic assembly comprising: a circuit board including a power supply; a package substrate having a first surface and an opposing second surface, located on the circuit board and including a first conductive path electrically coupled to the power supply at the first surface of the package substrate; a first microelectronic component having a first surface and an opposing second surface electrically coupled to the second surface of the package substrate, embedded in an insulating material on the second surface of the package substrate and including a through-substrate via (TSV) electrically coupled to the first conductive path; a second microelectronic component having a first surface and an opposing second surface electrically coupled to the second surface of the package substrate, embedded in an insulating material and including a second TSV electrically coupled to the first conductive path; a redistribution layer (RDL) having a first surface and an opposing second surface on the insulating material, including a second conductive path electrically coupled to the first and second TSVs; and a third microelectronic component located at the second surface of the RDL and electrically coupled to the second conductive path, wherein the second conductive path electrically couples the first and second TSVs, the third microelectronic component, and the second surface of the first microelectronic component.

[0261] Example 108 may include the object of Example 107, and may further specify the first surface of the first microelectronic component as the active side and the second surface of the first microelectronic component as the back side.

[0262] Example 109 may include the object of Example 107, and may further specify the first surface of the first microelectronic component as the back side and the second surface of the first microelectronic component as the active side.

[0263] Example 110 may include the object of Example 107, and may further specify the first surface of the second microelectronic component as the active side and the second surface of the second microelectronic component as the back side.

[0264] Example 111 may include the object of Example 107, and may further specify the first surface of the second microelectronic component as the back side and the second surface of the second microelectronic component as the active side.

[0265] Example 112 may include the object of Example 107 and may further include a capacitor element located on a first surface of the package substrate and electrically coupled to a first conductive path.

[0266] Example 113 may include the object of Example 107 and may further include a fourth microelectronic component, which is adjacent to the third microelectronic component at the second surface of the RDL and electrically coupled to the second conductive path.

[0267] Example 114 may include the object of Example 107, and may further specify that the third microelectronic component has a first surface and an opposite second surface at the second surface of the RDL, and may further include a fourth microelectronic component at the second surface of the third microelectronic component and electrically coupled to the second conductive path.

[0268] Example 115 may include the object of Example 107, and may further specify that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

[0269] Example 116 may include the subject matter of Example 107, and may further specify that the second microelectronic component includes a die of an input / output circuit system.

[0270] Example 117 may include the object of Example 107 and may further specify a third microelectronic component as a voltage regulator.

[0271] Example 118 may include the object of Example 113, and may further specify the fourth microelectronic component as an inductor or capacitor element.

[0272] Example 119 may include the object of Example 114, and may further specify the fourth microelectronic component as an inductor or capacitor element.

[0273] Example 120 relates to a microelectronic assembly comprising: a package substrate having a surface including a first conductive path electrically coupled to a power source; a first microelectronic component having a first surface electrically coupled to the surface of the package substrate and an opposing second surface, embedded in an insulating material on the surface of the package substrate and including a through-substrate via (TSV) electrically coupled to the first conductive path; a redistribution layer (RDL) having a first surface and an opposing second surface on the insulating material, including a second conductive path electrically coupled to the TSV; a second microelectronic component located on the second surface of the RDL and electrically coupled to the second conductive path, wherein the second conductive path electrically couples the TSV, the second microelectronic component, and the second surface of the first microelectronic component; and a third microelectronic component located on the second surface of the RDL and electrically coupled to the second conductive path.

[0274] Example 121 may include the object of Example 120, and may further specify the first surface of the first microelectronic component as the active side and the second surface of the first microelectronic component as the back side.

[0275] Example 122 may include the object of Example 120, and may further specify the first surface of the first microelectronic component as the back side and the second surface of the first microelectronic component as the active side.

[0276] Example 123 may include the object of Example 120, and may further specify a second microelectronic component adjacent to the second surface of the RDL.

[0277] Example 124 may include the object of Example 120, and may further specify that the second microelectronic component has a first surface and a relative second surface at the second surface of the RDL, wherein the third microelectronic component is on the second surface of the second microelectronic component.

[0278] Example 125 may include the object of Example 120, and may further specify that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

[0279] Example 126 may include the object of Example 120, and may further specify a second microelectronic component as a voltage regulator.

[0280] Example 127 may include the object of Example 120 and may further specify a third microelectronic component system inductor.

[0281] Example 128 may include the object of Example 120 and may further include a heat transfer structure at the second surface of the RDL.

[0282] Example 129 may include the object of Example 120, and may further specify that the power supply is mounted on the package substrate.

[0283] Example 130 may include the object of Example 120, and may further specify that the surface of the package substrate is a second surface and the package substrate further includes a surface opposite to the first surface, and may further include a circuit board electrically coupled to the first surface of the package substrate, wherein the power supply is on the circuit board.

[0284] Example 131 may include the object of Example 130, and may further include a capacitor element located on a first surface of the package substrate and electrically coupled to a first conductive path.

[0285] Example 132 is a microelectronic assembly comprising: a package substrate having a surface including a first conductive path electrically coupled to a power source; a mold material on the surface of the package substrate, the mold material including a first microelectronic component having a first surface and an opposing second surface embedded therein, a second microelectronic component embedded therein, and a through-hole (TMV) between the first microelectronic component and the second microelectronic component, the TMV being electrically coupled to the first conductive path; a redistribution layer (RDL) having a first surface and an opposing second surface on the mold material, including a second conductive path electrically coupled to the TMV; and a third microelectronic component located on the second surface of the redistribution layer and electrically coupled to the second conductive path, wherein the second conductive path is electrically coupled to the TMV, the third microelectronic component, and the second surface of the first microelectronic component.

[0286] Example 133 may include the object of Example 132, and may further specify the first surface of the first microelectronic component as the active side and the second surface of the first microelectronic component as the back side.

[0287] Example 134 may include the object of Example 132, and may further specify the first surface of the first microelectronic component as the back side and the second surface of the first microelectronic component as the active side.

[0288] Example 135 may include the object of Example 132 and may further include a fourth microelectronic component, which is adjacent to the third microelectronic component at the second surface of the RDL and electrically coupled to the second conductive path.

[0289] Example 136 may include the object of Example 132, and may further specify that the second microelectronic component has a first surface and an opposite second surface at the second surface of the RDL, and may further include a fourth microelectronic component at the second surface of the third microelectronic component and electrically coupled to the second conductive path.

[0290] Example 137 may include the object of Example 132, and may further specify that the power supply is mounted on the package substrate.

[0291] Example 138 may include the object of Example 132, and may further specify that the surface of the package substrate is a second surface and the package substrate further includes a surface opposite to the first surface, and may further include a circuit board electrically coupled to the first surface of the package substrate, wherein the power supply is on the circuit board.

[0292] Example 139 may include the object of Example 138 and may further include a capacitor element located on a first surface of the package substrate and electrically coupled to a first conductive path.

[0293] Example 140 may include the object of Example 132, and may further specify that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

[0294] Example 141 may include the object of Example 132, and may further specify a third microelectronic component as a voltage regulator.

[0295] Example 142 may include the object of Example 141, and may further specify that the voltage regulator is configured to convert a low current high voltage signal into a low voltage high current signal.

[0296] Example 143 may include the object of Example 135 and may further specify a fourth microelectronic component system inductor.

[0297] Example 144 may include the object of Example 136 and may further specify a fourth microelectronic component system inductor.

[0298] Example 145 may include the object of Example 132 and may further include a heat transfer structure at the second surface of the RDL.

[0299] Example 146 is a microelectronic assembly comprising: a circuit board including a power supply; a package substrate having a first surface and an opposing second surface, situated on the circuit board and including a first conductive path electrically coupled to the power supply; a first microelectronic component having a first surface and an opposing second surface, embedded in a mold material on the second surface of the package substrate; a second microelectronic component embedded in the mold material; a through-mold via (TMV) extending through the mold material between the first microelectronic component and the second microelectronic component and electrically coupled to the first conductive path; a redistribution layer (RDL) having a first surface and an opposing second surface, situated on the mold material, including a second conductive path electrically coupled to the TMV, wherein the first surface faces the mold material; and a third microelectronic component situated on the second surface of the RDL and electrically coupled to the second conductive path, wherein the second conductive path electrically couples the TMV, the third microelectronic component, and the second surface of the first microelectronic component.

[0300] Example 147 may include the object of Example 146, and may further specify the first surface of the first microelectronic component as the active side and the second surface of the first microelectronic component as the back side.

[0301] Example 148 may include the object of Example 146, and may further specify the first surface of the first microelectronic component as the back side and the second surface of the first microelectronic component as the active side.

[0302] Example 149 may include the object of Example 146 and may further include a fourth microelectronic component, which is adjacent to the third microelectronic component at the second surface of the RDL and electrically coupled to the second conductive path.

[0303] Example 150 may include the object of Example 146, and may further specify that the second microelectronic component has a first surface and an opposite second surface at the second surface of the RDL, and may further include a fourth microelectronic component at the second surface of the second microelectronic component and electrically coupled to the second conductive path.

[0304] Example 151 may include the object of Example 146, and may further specify that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

[0305] Example 152 may include the object of Example 146, and may further specify a third microelectronic component as a voltage regulator.

[0306] Example 153 may include the object of Example 152, and may further specify that the voltage regulator is configured to convert a low current high voltage signal into a low voltage high current signal.

[0307] Example 154 may include the object of Example 149 and may further specify a fourth microelectronic component system inductor.

[0308] Example 155 may include the object of Example 150 and may further specify a fourth microelectronic component system inductor.

[0309] Example 156 may include the object of Example 146 and may further include a capacitor element located on a first surface of the package substrate and electrically coupled to a first conductive path.

[0310] Example 157 may include the object of Example 146 and may further include a heat transfer structure at the second surface of the RDL.

[0311] Example 158 may include the subject matter of Example 146, and may further specify that the mold material includes organic materials.

[0312] Example 159 is a microelectronic assembly comprising: a package substrate having a surface including a first conductive path electrically coupled to a power source; a first microelectronic component having a first surface and an opposing second surface, embedded in a mold material on the second surface of the package substrate; a through-mold via (TMV) adjacent to the first microelectronic component, extending through the mold material and electrically coupled to the first conductive path; a redistribution layer (RDL) having a first surface and an opposing second surface on the mold material, including a second conductive path electrically coupled to the TMV, wherein the first surface faces the mold material; a second microelectronic component located on the second surface of the RDL and electrically coupled to the second conductive path, wherein the second conductive path is electrically coupled to the TMV, the second microelectronic component, and the second surface of the first microelectronic component; and a third microelectronic component located on the second surface of the RDL and electrically coupled to the second conductive path.

[0313] Example 160 may include the object of Example 159, and may further specify the first surface of the first microelectronic component as the active side and the second surface of the first microelectronic component as the back side.

[0314] Example 161 may include the object of Example 159, and may further specify the first surface of the first microelectronic component as the back side and the second surface of the first microelectronic component as the active side.

[0315] Example 162 may include the object of Example 159, and may further specify a second microelectronic component adjacent to the second surface of the RDL.

[0316] Example 163 may include the subject of Example 159 and may further specify that the second microelectronic component has a first surface and an opposite second surface at the second surface of the RDL, wherein the third microelectronic component is on the second surface of the second microelectronic component.

[0317] Example 164 may include the object of Example 159, and may further specify that the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

[0318] Example 165 may include the subject matter of Example 159 and may further specify a second microelectronic component as a voltage regulator.

[0319] Example 166 may include the object of Example 159 and may further specify a third microelectronic component system inductor.

[0320] Example 167 may include the object of Example 159 and may further include a heat transfer structure at the second surface of the RDL.

[0321] Example 168 may include the object of Example 159, and may further specify that the power supply is mounted on the package substrate.

[0322] Example 169 may include the object of Example 159, and may further specify that the surface of the package substrate is a second surface and the package substrate further includes a circuit board relative to the first surface, and may further include a circuit board electrically coupled to the first surface of the package substrate, wherein the power supply is on the circuit board.

[0323] Example 170 may include the object of Example 169, and may further include a capacitor element coupled to a first surface of the package substrate and electrically coupled to a first conductive path. [Simplified Explanation of the Diagram]

[0005] The embodiments will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Similar reference numerals are used to designate similar structural elements to aid this description. The embodiments are illustrated in the accompanying drawings by way of example rather than limitation.

[0006] Figure 1 is a side cross-sectional view of an example microelectronic assembly according to various embodiments.

[0007] Figure 2 is a side cross-sectional view of an example microelectronic assembly according to various embodiments.

[0008] Figure 3 is a side cross-sectional view of an example microelectronic assembly according to various embodiments.

[0009] Figure 4 is a side cross-sectional view of an example microelectronic assembly according to various embodiments.

[0010] Figures 5A and 5B are side cross-sectional views of example microelectronic assemblies according to various embodiments.

[0011] Figures 6A to 6G are side cross-sectional views of various stages in the example process for manufacturing the microelectronic assembly of Figure 1 according to various embodiments.

[0012] Figures 7A to 7G are side cross-sectional views of various stages in another example of the manufacturing process for the microelectronic assembly of Figure 1 according to various embodiments.

[0013] Figures 8A to 8H are side cross-sectional views of various stages in the example process for manufacturing the microelectronic assembly of Figure 5A according to various embodiments.

[0014] Figures 9A to 9I are side cross-sectional views of various stages in the example process for manufacturing the microelectronic assembly of Figure 5B according to various embodiments.

[0015] Figure 10 is a side cross-sectional view of an example microelectronic assembly according to various embodiments.

[0016] Figures 11A to 11G are side cross-sectional views of various stages in the example process for manufacturing the microelectronic assembly of Figure 10 according to various embodiments.

[0017] Figures 12A and 12B are side cross-sectional views of example microelectronic assemblies according to various embodiments.

[0018] Figures 13A and 13B are side cross-sectional views of example microelectronic assemblies according to various embodiments.

[0019] Figures 14A to 14I are side cross-sectional views of various stages in the example process for manufacturing the microelectronic assembly of Figure 13B according to various embodiments.

[0020] Figure 15 is a top view of a wafer and die that may be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0021] FIG16 is a cross-sectional side view of an IC device that may be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0022] FIG17 is a cross-sectional side view of an IC device assembly that may include a microelectronic assembly according to any of the embodiments disclosed herein.

[0023] FIG18 is a block diagram of an example electrical device that may include a microelectronic assembly according to any of the embodiments disclosed herein.

Claims

1. A microelectronic assembly comprising: a package substrate having a surface including a first conductive path electrically coupled to a power source; a mold material on the surface of the package substrate including a first microelectronic component having a first surface and an opposing second surface embedded therein, a second microelectronic component embedded therein, and a through-hole (TMV) between the first microelectronic component and the second microelectronic component, the TMV being electrically coupled to the first conductive path; a redistributable layer (RDL) having a first surface and an opposing second surface on the mold material, including a second conductive path electrically coupled to the TMV; and a third microelectronic component located on the second surface of the RDL and electrically coupled to the second conductive path, wherein the second conductive path is electrically coupled to the TMV, the third microelectronic component, and the second surface of the first microelectronic component.

2. The microelectronic assembly of claim 1, further comprising: a fourth microelectronic component located at the second surface of the RDL and electrically coupled to the second conductive path.

3. The microelectronic assembly of claim 1, wherein the surface of the package substrate is a second surface and the package substrate further includes an opposing first surface, and the microelectronic assembly further includes: a circuit board electrically coupled to the first surface of the package substrate, wherein the power supply is located on the circuit board.

4. The microelectronic assembly of claim 3 further includes: a capacitor element located on the first surface of the package substrate and electrically coupled to the first conductive path.

5. A microelectronic assembly as claimed in any of claims 1 to 4, wherein the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor, or a cryptographic processor.

6. A microelectronic assembly as claimed in any of claims 1 to 4, wherein the third microelectronic component is a voltage regulator.

7. The microelectronic assembly of claim 2, wherein the fourth microelectronic component is an inductor.

8. The microelectronic assembly of any one of claims 1 to 4 further comprises: a heat transfer structure at the second surface of the RDL.

9. A microelectronic assembly comprising: a circuit board including a power supply; a package substrate having a first surface and an opposing second surface, the package substrate being disposed on the circuit board and including a first conductive path electrically coupled to the power supply; and a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component being embedded in a mold material on the second surface of the package substrate. A second microelectronic component embedded in the mold material; a through-mold via (TMV) between the first and second microelectronic components, the TMV extending through the mold material and electrically coupled to the first conductive path; a re-laid layer (RDL) having a first surface and an opposing second surface, the RDL being situated on the mold material with the first surface facing the mold material, the RDL including a second conductive path electrically coupled to one of the TMVs; And a third microelectronic component, which is located on the second surface of the RDL and electrically coupled to the second conductive path, wherein the second conductive path is electrically coupled to the TMV, the third microelectronic component and the second surface of the first microelectronic component.

10. The microelectronic assembly of claim 9, further comprising: a fourth microelectronic component located at the second surface of the RDL and electrically coupled to the second conductive path.

11. The microelectronic assembly of claim 9 or 10, wherein the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

12. The microelectronic assembly of claim 9 or 10, wherein the third microelectronic component is a voltage regulator.

13. The microelectronic assembly of claim 10, wherein the fourth microelectronic component is an inductor.

14. The microelectronic assembly of claim 9, further comprising: a heat transfer structure at the second surface of the RDL.

15. The microelectronic assembly of claim 9, wherein the mold material comprises an organic material.

16. A microelectronic assembly comprising: a package substrate having a surface, the package substrate including a first conductive path electrically coupled to a power source; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component being embedded in a mold material on the second surface of the package substrate; a through-mold via (TMV) adjacent to the first microelectronic component, the TMV extending through the mold material and electrically coupled to the first conductive path; and a redistributable layer (RDL) having a first surface and an opposing second surface, the RDL being disposed on the mold material with the first surface facing the mold material, the RDL including a second conductive path electrically coupled to the TMV; A second microelectronic component is located on the second surface of the RDL and electrically coupled to the second conductive path, wherein the second conductive path is electrically coupled to the TMV, the second microelectronic component and the second surface of the first microelectronic component; And a third microelectronic component, which is located on the second surface of the RDL and electrically coupled to the second conductive path.

17. The microelectronic assembly of claim 16, wherein the first microelectronic component is a central processing unit, a graphics processing unit, a digital signal processor, a special application integrated circuit, a server processor or a cryptographic processor.

18. The microelectronic assembly of claim 16, wherein the second microelectronic component is a voltage regulator.

19. The microelectronic assembly of claim 16, wherein the third microelectronic component is an inductor.

20. A microelectronic assembly of any one of claims 16 to 19, wherein the surface of the package substrate is a second surface and the package substrate further includes an opposing first surface, and the microelectronic assembly further includes: a circuit board electrically coupled to the first surface of the package substrate, wherein the power supply is located on the circuit board.

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